From bee3d9d5c6de10f8e4e687e7937c7a9af5583cd7 Mon Sep 17 00:00:00 2001 From: Rafal Bielski <rafal.bielski@cern.ch> Date: Tue, 1 Dec 2020 14:14:37 +0100 Subject: [PATCH] Update Trigger CI references --- .../share/ref_RDOtoRDOTrig_v1Dev_build.ref | 8 ++++---- .../TriggerTest/share/ref_data_v1Dev_build.ref | 12 ++++++------ 2 files changed, 10 insertions(+), 10 deletions(-) diff --git a/Trigger/TrigValidation/TrigAnalysisTest/share/ref_RDOtoRDOTrig_v1Dev_build.ref b/Trigger/TrigValidation/TrigAnalysisTest/share/ref_RDOtoRDOTrig_v1Dev_build.ref index d147e2b573e..f1300dfd45b 100644 --- a/Trigger/TrigValidation/TrigAnalysisTest/share/ref_RDOtoRDOTrig_v1Dev_build.ref +++ b/Trigger/TrigValidation/TrigAnalysisTest/share/ref_RDOtoRDOTrig_v1Dev_build.ref @@ -1393,7 +1393,7 @@ HLT_j0_vbenfSEP30etSEP34mass35SEP50fbet_L1J20: stepCounts: 0: 15 stepFeatures: - 0: 402 + 0: 398 HLT_j225_subjesgscIS_ftf_bmv2c1040_split_L1J100: eventCount: 0 stepCounts: @@ -1597,13 +1597,13 @@ HLT_j45_subjesgscIS_ftf_011jvt_L1J15: 0: 20 1: 44 HLT_j45_subjesgscIS_ftf_015jvt_L1J15: - eventCount: 18 + eventCount: 17 stepCounts: 0: 20 - 1: 18 + 1: 17 stepFeatures: 0: 20 - 1: 44 + 1: 42 HLT_j45_subjesgscIS_ftf_059jvt_L1J15: eventCount: 17 stepCounts: diff --git a/Trigger/TrigValidation/TriggerTest/share/ref_data_v1Dev_build.ref b/Trigger/TrigValidation/TriggerTest/share/ref_data_v1Dev_build.ref index ac15eb5b79a..96e60e9bb18 100644 --- a/Trigger/TrigValidation/TriggerTest/share/ref_data_v1Dev_build.ref +++ b/Trigger/TrigValidation/TriggerTest/share/ref_data_v1Dev_build.ref @@ -1745,13 +1745,13 @@ HLT_xe30_mht_L1XE10: stepFeatures: 0: 14 HLT_xe30_mhtpufit_em_subjesgscIS_L1XE10: - eventCount: 4 + eventCount: 2 stepCounts: 0: 20 - 1: 4 + 1: 2 stepFeatures: 0: 20 - 1: 4 + 1: 2 HLT_xe30_mhtpufit_pf_subjesgscIS_L1XE10: eventCount: 2 stepCounts: @@ -1799,13 +1799,13 @@ HLT_xe30_tcpufit_L1XE10: stepFeatures: 0: 6 HLT_xe30_trkmht_L1XE10: - eventCount: 7 + eventCount: 6 stepCounts: 0: 20 - 1: 7 + 1: 6 stepFeatures: 0: 20 - 1: 7 + 1: 6 HLT_xe65_cell_L1XE50: eventCount: 0 HLT_xe65_cell_xe110_tcpufit_L1XE50: -- GitLab