From c705343fe11daff0558e96ec81a187b4a62c4c9a Mon Sep 17 00:00:00 2001
From: Stewart Martin-Haugh <smh@cern.ch>
Date: Fri, 31 Jul 2020 19:06:30 +0200
Subject: [PATCH] Remove now-unused AthRegSeq
---
Control/AthenaCommon/python/AppMgr.py | 8 +-------
.../python/ConfigurationShelve.py | 2 --
.../share/GenerateBootstrapTest.ref | 12 ++++++------
Control/AthenaCommon/share/bootstrap.pkl | Bin 7958 -> 6949 bytes
.../AthenaCommon/share/bootstrap_threaded.pkl | Bin 9405 -> 8382 bytes
.../python/ComponentAccumulator.py | 1 -
.../python/MainServicesConfig.py | 1 -
7 files changed, 7 insertions(+), 17 deletions(-)
diff --git a/Control/AthenaCommon/python/AppMgr.py b/Control/AthenaCommon/python/AppMgr.py
index da5b9ac5661..d660fa209a5 100755
--- a/Control/AthenaCommon/python/AppMgr.py
+++ b/Control/AthenaCommon/python/AppMgr.py
@@ -24,7 +24,6 @@ __all__ = [ 'theApp', 'ServiceMgr', 'ToolSvc', 'AuditorSvc', 'theAuditorSvc',
'athCondSeq',
'athAlgSeq', 'topSequence',
'athOutSeq',
- 'athRegSeq',
]
### helpers ------------------------------------------------------------------
@@ -263,7 +262,7 @@ class AthAppMgr( AppMgr ):
def __build_master_sequence (self):
"""helper method to build the top-level AthSequencer from all bits and
- pieces : AthMasterSeq, AthAlgSeq, AthOutSeq, AthRegSeq
+ pieces : AthMasterSeq, AthAlgSeq, AthOutSeq
"""
from . import AlgSequence as _as
from AthenaServices.AthenaServicesConf import AthIncFirerAlg as IFA
@@ -277,7 +276,6 @@ class AthAppMgr( AppMgr ):
athAlgSeq = _as.AthSequencer ("AthAlgSeq",IgnoreFilterPassed=True, StopOverride=True)
athEndSeq = _as.AthSequencer ("AthEndSeq",Sequential=True)
athOutSeq = _as.AthSequencer ("AthOutSeq", StopOverride=True)
- athRegSeq = _as.AthSequencer ("AthRegSeq", StopOverride=True)
athAllAlgSeq = _as.AthSequencer ("AthAllAlgSeq", StopOverride=True)
athAlgEvtSeq = _as.AthSequencer ("AthAlgEvtSeq",Sequential = True, StopOverride=True)
# transfer old TopAlg to new AthAlgSeq
@@ -337,7 +335,6 @@ class AthAppMgr( AppMgr ):
athMasterSeq += athAlgEvtSeq
athMasterSeq += athOutSeq
- athMasterSeq += athRegSeq
Logging.log.debug ("building master sequence... [done]")
return athMasterSeq
@@ -998,12 +995,9 @@ def AuditorSvc(): # backwards compatibility
# +--- athEndSeq
# |
# +--- athOutSeq
-# |
-# +--- athRegSeq
athMasterSeq = AlgSequence.AthSequencer( "AthMasterSeq" )
athCondSeq = AlgSequence.AthSequencer( "AthCondSeq" )
athAlgSeq = AlgSequence.AthSequencer( "AthAlgSeq" )
athOutSeq = AlgSequence.AthSequencer( "AthOutSeq" )
-athRegSeq = AlgSequence.AthSequencer( "AthRegSeq" )
topSequence = AlgSequence.AlgSequence( "TopAlg" ) # for backward compatibility
diff --git a/Control/AthenaCommon/python/ConfigurationShelve.py b/Control/AthenaCommon/python/ConfigurationShelve.py
index 461bd058add..c085893405c 100644
--- a/Control/AthenaCommon/python/ConfigurationShelve.py
+++ b/Control/AthenaCommon/python/ConfigurationShelve.py
@@ -110,7 +110,6 @@ class ConfigurationJar( object ):
self.TopSequence = _as.AlgSequence ("TopAlg")
self.athAlgSeq = _as.AthSequencer ("AthAlgSeq")
self.athOutSeq = _as.AthSequencer ("AthOutSeq")
- self.athRegSeq = _as.AthSequencer ("AthRegSeq")
self.AppMgr = theApp
self.ServiceMgr = ServiceMgr # takes care of AuditorSvc & ToolSvc
@@ -131,7 +130,6 @@ class ConfigurationJar( object ):
d[ 'AthAlgSeq' ] = self.athAlgSeq
d[ 'TopSequence' ] = self.TopSequence
d[ 'AthOutSeq' ] = self.athOutSeq
- d[ 'AthRegSeq' ] = self.athRegSeq
d[ 'AppMgr' ] = self.AppMgr
d[ 'Streams' ] = self.AppMgr._streams
d[ 'ServiceMgr' ] = self.ServiceMgr #takes care of {Auditor,Tool}Svc
diff --git a/Control/AthenaCommon/share/GenerateBootstrapTest.ref b/Control/AthenaCommon/share/GenerateBootstrapTest.ref
index f192f34d093..1cd0c9012f0 100644
--- a/Control/AthenaCommon/share/GenerateBootstrapTest.ref
+++ b/Control/AthenaCommon/share/GenerateBootstrapTest.ref
@@ -1,16 +1,16 @@
Willing to acquire file bootstrap.pkl from
-/build/mnowak/work/sealsvc/build/x86_64-centos7-gcc8-opt/share/bootstrap.pkl
+/afs/cern.ch/work/s/smh/ol_reggie/bld/x86_64-centos7-gcc8-opt/share/bootstrap.pkl
copy bootstrap.pkl
... Read 2 items from python pickle file: bootstrap.pkl
... Read 2 items from python pickle file: bootstrap_test.pkl
Given list of size 0. Not looking for differences.
-Step 1: reference file #components: 27
-Step 2: file to check #components: 27
+Step 1: reference file #components: 26
+Step 2: file to check #components: 26
Willing to acquire file bootstrap_threaded.pkl from
-/build/mnowak/work/sealsvc/build/x86_64-centos7-gcc8-opt/share/bootstrap_threaded.pkl
+/afs/cern.ch/work/s/smh/ol_reggie/bld/x86_64-centos7-gcc8-opt/share/bootstrap_threaded.pkl
copy bootstrap_threaded.pkl
... Read 2 items from python pickle file: bootstrap_threaded.pkl
... Read 2 items from python pickle file: bootstrap_threaded_test.pkl
Given list of size 0. Not looking for differences.
-Step 1: reference file #components: 33
-Step 2: file to check #components: 33
+Step 1: reference file #components: 32
+Step 2: file to check #components: 32
diff --git a/Control/AthenaCommon/share/bootstrap.pkl b/Control/AthenaCommon/share/bootstrap.pkl
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diff --git a/Control/AthenaCommon/share/bootstrap_threaded.pkl b/Control/AthenaCommon/share/bootstrap_threaded.pkl
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diff --git a/Control/AthenaConfiguration/python/ComponentAccumulator.py b/Control/AthenaConfiguration/python/ComponentAccumulator.py
index a6cff972939..a3ffde4ec5f 100644
--- a/Control/AthenaConfiguration/python/ComponentAccumulator.py
+++ b/Control/AthenaConfiguration/python/ComponentAccumulator.py
@@ -1066,7 +1066,6 @@ def appendCAtoAthena(ca):
preconfigured = [athCondSeq,athOutSeq,athAlgSeq,topSequence]
- #preconfigured = ["AthMasterSeq", "AthCondSeq", "AthAlgSeq", "AthOutSeq", "AthRegSeq"]
for seq in ca._allSequences:
merged = False
diff --git a/Control/AthenaConfiguration/python/MainServicesConfig.py b/Control/AthenaConfiguration/python/MainServicesConfig.py
index 9a9d69b62a5..83dacda189f 100644
--- a/Control/AthenaConfiguration/python/MainServicesConfig.py
+++ b/Control/AthenaConfiguration/python/MainServicesConfig.py
@@ -39,7 +39,6 @@ def MainServicesCfg(cfgFlags):
#Build standard sequences:
cfg.addSequence(AthSequencer('AthAlgEvtSeq',Sequential=True, StopOverride=True),parentName="AthMasterSeq")
cfg.addSequence(AthSequencer('AthOutSeq',StopOverride=True),parentName="AthMasterSeq")
- cfg.addSequence(AthSequencer('AthRegSeq',StopOverride=True),parentName="AthMasterSeq")
cfg.addSequence(AthSequencer('AthBeginSeq',Sequential=True),parentName='AthAlgEvtSeq')
cfg.addSequence(AthSequencer('AthAllAlgSeq',StopOverride=True),parentName='AthAlgEvtSeq')
--
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