diff --git a/Trigger/TrigT1/L1CaloFEX/L1CaloFEXSim/L1CaloFEXSim/eFEXFPGA.h b/Trigger/TrigT1/L1CaloFEX/L1CaloFEXSim/L1CaloFEXSim/eFEXFPGA.h
index d2753e1d767405f4032cac7002391e008f50e3e3..7552b150a0f944d219cb6a0c5de196defee8b7bc 100644
--- a/Trigger/TrigT1/L1CaloFEX/L1CaloFEXSim/L1CaloFEXSim/eFEXFPGA.h
+++ b/Trigger/TrigT1/L1CaloFEX/L1CaloFEXSim/L1CaloFEXSim/eFEXFPGA.h
@@ -24,6 +24,7 @@
#include "CaloIdentifier/CaloIdManager.h"
#include "CaloIdentifier/CaloCell_SuperCell_ID.h"
#include "L1CaloFEXSim/eFEXOutputCollection.h"
+#include <vector>
namespace LVL1 {
@@ -55,6 +56,8 @@ namespace LVL1 {
virtual void SetTowersAndCells_SG( int [][6] ) override ;
+ virtual void SetIsoWP(std::vector<unsigned int> &, std::vector<unsigned int> &, unsigned int &) override ;
+
/** Internal data */
private:
diff --git a/Trigger/TrigT1/L1CaloFEX/L1CaloFEXSim/L1CaloFEXSim/eFEXegAlgo.h b/Trigger/TrigT1/L1CaloFEX/L1CaloFEXSim/L1CaloFEXSim/eFEXegAlgo.h
index 88adfe9581cd4cb1e50492c306a6b9ba4b939768..b21a74fc04703a40a0617c3ab9b6b438b6142982 100644
--- a/Trigger/TrigT1/L1CaloFEX/L1CaloFEXSim/L1CaloFEXSim/eFEXegAlgo.h
+++ b/Trigger/TrigT1/L1CaloFEX/L1CaloFEXSim/L1CaloFEXSim/eFEXegAlgo.h
@@ -46,7 +46,7 @@ namespace LVL1 {
virtual StatusCode safetyTest() override;
virtual void setup(int inputTable[3][3]) override;
- virtual std::vector<unsigned int> getReta() override;
+ virtual void getReta(std::vector<unsigned int> & ) override;
virtual void getRhad(std::vector<unsigned int> & ) override;
virtual void getWstot(std::vector<unsigned int> & ) override;
virtual void getRealPhi(float & phi) override;
@@ -59,7 +59,7 @@ namespace LVL1 {
virtual void getCoreEMTowerET(unsigned int & et) override;
virtual void getCoreHADTowerET(unsigned int & et) override;
private:
- virtual void setSeed() override;
+ void setSeed();
bool m_seed_UnD = false;
unsigned int m_seedID = 999;
int m_eFEXegAlgoTowerID[3][3];
diff --git a/Trigger/TrigT1/L1CaloFEX/L1CaloFEXSim/src/eFEXFPGA.cxx b/Trigger/TrigT1/L1CaloFEX/L1CaloFEXSim/src/eFEXFPGA.cxx
index 94e6609d10348be5558781bab26f46309c8c7e7b..69c66efb0c6f68d3a6f392eabbd33710d3575e28 100644
--- a/Trigger/TrigT1/L1CaloFEX/L1CaloFEXSim/src/eFEXFPGA.cxx
+++ b/Trigger/TrigT1/L1CaloFEX/L1CaloFEXSim/src/eFEXFPGA.cxx
@@ -114,9 +114,28 @@ StatusCode eFEXFPGA::execute(){
// temporarily(?) removed for debugging
//if (eFEXFPGA_egAlgo->haveSeed() == false) continue;
- std::vector<unsigned int> RetaND = m_eFEXegAlgoTool->getReta();
- std::vector<unsigned int> RhadND; m_eFEXegAlgoTool->getRhad(RhadND);
+ // Get Reta and Rhad outputs
+ std::vector<unsigned int> RetaCoreEnv;
+ m_eFEXegAlgoTool->getReta(RetaCoreEnv);
+ std::vector<unsigned int> RhadCoreEnv;
+ m_eFEXegAlgoTool->getRhad(RhadCoreEnv);
+ std::vector<unsigned int> WstotCoreEnv;
+ m_eFEXegAlgoTool->getWstot(WstotCoreEnv);
+
+ // temp thresholds that will come from Trigger menu
+ std::vector<unsigned int> tempThrs;
+ tempThrs.push_back(40);
+ tempThrs.push_back(30);
+ tempThrs.push_back(20);
+ // Set Reta, Rhad and Wstot WP
+ unsigned int RetaWP = 0;
+ unsigned int RhadWP = 0;
+ unsigned int WstotWP = 0;
+ SetIsoWP(RetaCoreEnv,tempThrs,RetaWP);
+ SetIsoWP(RhadCoreEnv,tempThrs,RhadWP);
+ SetIsoWP(WstotCoreEnv,tempThrs,WstotWP);
+
std::unique_ptr<eFEXegTOB> tmp_tob = m_eFEXegAlgoTool->geteFEXegTOB();
tmp_tob->setFPGAID(m_id);
@@ -200,6 +219,45 @@ void eFEXFPGA::SetTowersAndCells_SG(int tmp_eTowersIDs_subset[][6]){
}
}
+
+void eFEXFPGA::SetIsoWP(std::vector<unsigned int> & CoreEnv, std::vector<unsigned int> & thresholds, unsigned int & workingPoint) {
+
+ bool CoreOverflow = false;
+ bool EnvOverflow = false;
+ bool ThrEnvOverflowL = false;
+ bool ThrEnvOverflowM = false;
+ bool ThrEnvOverflowT = false;
+
+ if (CoreEnv[0] > 0xffff) CoreOverflow = true;
+ if (CoreEnv[1] > 0xffff) EnvOverflow = true;
+ if (CoreEnv[1]*thresholds[0] > 0xffff) ThrEnvOverflowL = true;
+ if (CoreEnv[1]*thresholds[1] > 0xffff) ThrEnvOverflowM = true;
+ if (CoreEnv[1]*thresholds[2] > 0xffff) ThrEnvOverflowT = true;
+
+ if (CoreOverflow == false) {
+ if (EnvOverflow == false) {
+ if ( (CoreEnv[0] > (thresholds[2]*CoreEnv[1])) && ThrEnvOverflowT == false ) {
+ workingPoint = 3;
+ }
+ else if ( (CoreEnv[0] > (thresholds[1]*CoreEnv[1])) && ThrEnvOverflowM == false ) {
+ workingPoint = 2;
+ }
+ else if ( (CoreEnv[0] > (thresholds[0]*CoreEnv[1])) && ThrEnvOverflowL == false ) {
+ workingPoint = 1;
+ }
+ else {
+ workingPoint = 0;
+ }
+ } else {
+ workingPoint = 0; //env overflow
+ }
+ }
+ else {
+ workingPoint = 3; // core overflow
+ }
+
+}
+
} // end of namespace bracket
diff --git a/Trigger/TrigT1/L1CaloFEX/L1CaloFEXSim/src/eFEXegAlgo.cxx b/Trigger/TrigT1/L1CaloFEX/L1CaloFEXSim/src/eFEXegAlgo.cxx
index a99a3773f035631f7981d692eb992134a186e415..5689f0ab5873cbe95a01b7232d712173adabe842 100644
--- a/Trigger/TrigT1/L1CaloFEX/L1CaloFEXSim/src/eFEXegAlgo.cxx
+++ b/Trigger/TrigT1/L1CaloFEX/L1CaloFEXSim/src/eFEXegAlgo.cxx
@@ -100,9 +100,8 @@ void LVL1::eFEXegAlgo::getRealEta(float & eta) {
}
-std::vector<unsigned int> eFEXegAlgo::getReta() {
+void eFEXegAlgo::getReta(std::vector<unsigned int> & retavec) {
- std::vector<unsigned int> retavec;
unsigned int coresum = 0; // 3x2 L2 sum : core
unsigned int totalsum = 0; // 7x3 L2 sum : total
unsigned int envsum = 0; // total - core : env
@@ -141,7 +140,6 @@ std::vector<unsigned int> eFEXegAlgo::getReta() {
retavec.push_back(coresum);
retavec.push_back(envsum);
- return retavec;
}
void eFEXegAlgo::getRhad(std::vector<unsigned int> & rhadvec) {
@@ -196,8 +194,9 @@ void LVL1::eFEXegAlgo::getWstot(std::vector<unsigned int> & output){
den += eT;
}
}
- output.push_back(numer);
+
output.push_back(den);
+ output.push_back(numer);
}
@@ -238,7 +237,7 @@ std::unique_ptr<eFEXegTOB> LVL1::eFEXegAlgo::geteFEXegTOB() {
getRhad(temvector);
out->setRhadNum(temvector[1]);
out->setRhadDen(temvector[0] + temvector[1]);
- temvector = getReta();
+ getReta(temvector);
out->setRetaNum(temvector[0]);
out->setRetaDen(temvector[0] + temvector[1]);
out->setSeedUnD(m_seed_UnD);
diff --git a/Trigger/TrigT1/L1CaloFEXToolInterfaces/L1CaloFEXToolInterfaces/IeFEXFPGA.h b/Trigger/TrigT1/L1CaloFEXToolInterfaces/L1CaloFEXToolInterfaces/IeFEXFPGA.h
index b8ee1663a1a489b860b214292b925c7c20d340cc..b862b6eafd5dfc32bbcd04048636e04a729e361d 100644
--- a/Trigger/TrigT1/L1CaloFEXToolInterfaces/L1CaloFEXToolInterfaces/IeFEXFPGA.h
+++ b/Trigger/TrigT1/L1CaloFEXToolInterfaces/L1CaloFEXToolInterfaces/IeFEXFPGA.h
@@ -40,6 +40,8 @@ Interface definition for eFEXFPGA
virtual int ID() = 0;
virtual void SetTowersAndCells_SG(int [][6]) = 0;
+
+ virtual void SetIsoWP(std::vector<unsigned int> &, std::vector<unsigned int> &, unsigned int &) = 0;
private:
diff --git a/Trigger/TrigT1/L1CaloFEXToolInterfaces/L1CaloFEXToolInterfaces/IeFEXegAlgo.h b/Trigger/TrigT1/L1CaloFEXToolInterfaces/L1CaloFEXToolInterfaces/IeFEXegAlgo.h
index 4df595db7d02103c054e4878754acd465e2cd2ae..dc66d529eb5969a96590d80d1965a934eefc019f 100644
--- a/Trigger/TrigT1/L1CaloFEXToolInterfaces/L1CaloFEXToolInterfaces/IeFEXegAlgo.h
+++ b/Trigger/TrigT1/L1CaloFEXToolInterfaces/L1CaloFEXToolInterfaces/IeFEXegAlgo.h
@@ -31,7 +31,7 @@ Interface definition for eFEXegAlgo
virtual StatusCode safetyTest() = 0;
virtual void setup(int inputTable[3][3]) = 0;
- virtual std::vector<unsigned int> getReta() = 0;
+ virtual void getReta(std::vector<unsigned int> & ) = 0;
virtual void getRhad(std::vector<unsigned int> & ) = 0;
virtual void getWstot(std::vector<unsigned int> & ) = 0;
virtual void getRealPhi(float & phi) = 0;
@@ -43,9 +43,6 @@ Interface definition for eFEXegAlgo
virtual void getCoreEMTowerET(unsigned int & et) = 0;
virtual void getCoreHADTowerET(unsigned int & et) = 0;
- private:
- virtual void setSeed() = 0;
-
};
inline const InterfaceID& LVL1::IeFEXegAlgo::interfaceID()