diff --git a/Trigger/TrigValidation/TrigAnalysisTest/share/ref_RDOtoRDOTrig_v1Dev_build.ref b/Trigger/TrigValidation/TrigAnalysisTest/share/ref_RDOtoRDOTrig_v1Dev_build.ref
index 9cd69c76f47dfa90df1c54246cc962905f07ffce..82a6966296a1535ed0b5dbd81bf4c750c3978312 100644
--- a/Trigger/TrigValidation/TrigAnalysisTest/share/ref_RDOtoRDOTrig_v1Dev_build.ref
+++ b/Trigger/TrigValidation/TrigAnalysisTest/share/ref_RDOtoRDOTrig_v1Dev_build.ref
@@ -1,1146 +1,2722 @@
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+HLT_tau25_idperf_track_L1TAU12IM:
+ eventCount: 13
+ stepCounts:
+ 0: 14
+ 1: 13
+ 2: 13
+ 3: 13
+ 4: 13
+ stepFeatures:
+ 0: 24
+ 1: 16
+ 2: 16
+ 3: 16
+ 4: 16
+HLT_tau25_idperf_tracktwoMVA_L1TAU12IM:
+ eventCount: 11
+ stepCounts:
+ 0: 14
+ 1: 13
+ 2: 12
+ 3: 11
+ 4: 11
+ stepFeatures:
+ 0: 24
+ 1: 17
+ 2: 14
+ 3: 13
+ 4: 13
+HLT_tau25_idperf_tracktwo_L1TAU12IM:
+ eventCount: 11
+ stepCounts:
+ 0: 14
+ 1: 13
+ 2: 12
+ 3: 12
+ 4: 11
+ 5: 11
+ stepFeatures:
+ 0: 24
+ 1: 17
+ 2: 14
+ 3: 14
+ 4: 13
+ 5: 13
+HLT_tau25_looseRNN_tracktwoMVA_L1TAU12IM:
+ eventCount: 8
+ stepCounts:
+ 0: 12
+ 1: 11
+ 2: 10
+ 3: 9
+ 4: 8
+ stepFeatures:
+ 0: 22
+ 1: 15
+ 2: 12
+ 3: 11
+ 4: 9
+HLT_tau25_looseRNN_tracktwo_L1TAU12IM:
+ eventCount: 0
+ stepCounts:
+ 0: 12
+ 1: 11
+ 2: 10
+ stepFeatures:
+ 0: 22
+ 1: 15
+ 2: 12
+HLT_tau25_medium1_tracktwoEF_L1TAU12IM:
+ eventCount: 0
+ stepCounts:
+ 0: 12
+ 1: 11
+ 2: 10
+ 3: 9
+ stepFeatures:
+ 0: 22
+ 1: 15
+ 2: 12
+ 3: 11
+HLT_tau25_medium1_tracktwoMVA_L1TAU12IM:
+ eventCount: 0
+ stepCounts:
+ 0: 12
+ 1: 11
+ 2: 10
+ 3: 9
+ stepFeatures:
+ 0: 22
+ 1: 15
+ 2: 12
+ 3: 11
+HLT_tau25_medium1_tracktwo_L1TAU12IM:
+ eventCount: 0
+ stepCounts:
+ 0: 12
+ 1: 11
+ 2: 10
+ stepFeatures:
+ 0: 22
+ 1: 15
+ 2: 12
+HLT_tau25_mediumRNN_tracktwoMVA_L1TAU12IM:
+ eventCount: 5
+ stepCounts:
+ 0: 12
+ 1: 11
+ 2: 10
+ 3: 9
+ 4: 5
+ stepFeatures:
+ 0: 22
+ 1: 15
+ 2: 12
+ 3: 11
+ 4: 5
+HLT_tau25_mediumRNN_tracktwo_L1TAU12IM:
+ eventCount: 0
+ stepCounts:
+ 0: 12
+ 1: 11
+ 2: 10
+ stepFeatures:
+ 0: 22
+ 1: 15
+ 2: 12
+HLT_tau25_perf_tracktwoMVA_L1TAU12IM:
+ eventCount: 11
+ stepCounts:
+ 0: 14
+ 1: 13
+ 2: 12
+ 3: 11
+ 4: 11
+ stepFeatures:
+ 0: 24
+ 1: 17
+ 2: 14
+ 3: 13
+ 4: 13
+HLT_tau25_perf_tracktwo_L1TAU12IM:
+ eventCount: 11
+ stepCounts:
+ 0: 14
+ 1: 13
+ 2: 12
+ 3: 12
+ 4: 11
+ 5: 11
+ stepFeatures:
+ 0: 24
+ 1: 17
+ 2: 14
+ 3: 14
+ 4: 13
+ 5: 13
+HLT_tau25_tightRNN_tracktwoMVA_L1TAU12IM:
+ eventCount: 4
+ stepCounts:
+ 0: 12
+ 1: 11
+ 2: 10
+ 3: 9
+ 4: 4
+ stepFeatures:
+ 0: 22
+ 1: 15
+ 2: 12
+ 3: 11
+ 4: 4
+HLT_tau25_tightRNN_tracktwo_L1TAU12IM:
+ eventCount: 0
+ stepCounts:
+ 0: 12
+ 1: 11
+ 2: 10
+ stepFeatures:
+ 0: 22
+ 1: 15
+ 2: 12
+HLT_tau25_verylooseRNN_tracktwoMVA_L1TAU12IM:
+ eventCount: 8
+ stepCounts:
+ 0: 12
+ 1: 11
+ 2: 10
+ 3: 9
+ 4: 8
+ stepFeatures:
+ 0: 22
+ 1: 15
+ 2: 12
+ 3: 11
+ 4: 9
+HLT_tau25_verylooseRNN_tracktwo_L1TAU12IM:
+ eventCount: 0
+ stepCounts:
+ 0: 12
+ 1: 11
+ 2: 10
+ stepFeatures:
+ 0: 22
+ 1: 15
+ 2: 12
+HLT_tau35_mediumRNN_tracktwoMVA_L1TAU12IM:
+ eventCount: 4
+ stepCounts:
+ 0: 11
+ 1: 10
+ 2: 9
+ 3: 8
+ 4: 4
+ stepFeatures:
+ 0: 20
+ 1: 14
+ 2: 11
+ 3: 10
+ 4: 4
+HLT_tau35_mediumRNN_tracktwoMVA_tau25_mediumRNN_tracktwoMVA_L1DR-TAU20ITAU12I-J25:
+ eventCount: 0
+ stepCounts:
+ 0: 6
+ 1: 3
+ 2: 2
+ 3: 2
+ stepFeatures:
+ 0: 15
+ 1: 6
+ 2: 4
+ 3: 4
+HLT_tau80_medium1_tracktwo_L1TAU60:
+ eventCount: 0
+ stepCounts:
+ 0: 4
+ 1: 2
+ 2: 2
+ stepFeatures:
+ 0: 5
+ 1: 2
+ 2: 2
+HLT_tau80_mediumRNN_tracktwoMVA_tau35_mediumRNN_tracktwoMVA_L1TAU60_DR-TAU20ITAU12I:
+ eventCount: 0
+ stepCounts:
+ 0: 2
+ stepFeatures:
+ 0: 6
+HLT_tau80_mediumRNN_tracktwoMVA_tau60_mediumRNN_tracktwoMVA_L1TAU60_2TAU40:
+ eventCount: 0
+ stepCounts:
+ 0: 2
+ stepFeatures:
+ 0: 5
+HLT_tilecalib_laser_TilePEB_L1CALREQ2:
+ eventCount: 0
+HLT_timeburner_L1All:
+ eventCount: 0
+HLT_unconvtrk120_isohpttrack_icummedium_L1XE50:
+ eventCount: 0
+HLT_unconvtrk120_isohpttrack_imedium_L1XE50:
+ eventCount: 6
+ stepCounts:
+ 0: 6
+ stepFeatures:
+ 0: 6
+HLT_xe100_cvfpufit_L1XE50:
+ eventCount: 6
+ stepCounts:
+ 0: 10
+ 1: 6
+ stepFeatures:
+ 0: 10
+ 1: 6
+HLT_xe100_mht_L1XE50:
+ eventCount: 9
+ stepCounts:
+ 0: 9
+ stepFeatures:
+ 0: 9
+HLT_xe100_mhtpufit_em_subjesgscIS_L1XE50:
+ eventCount: 5
+ stepCounts:
+ 0: 10
+ 1: 5
+ stepFeatures:
+ 0: 10
+ 1: 5
+HLT_xe100_mhtpufit_pf_subjesgscIS_L1XE50:
+ eventCount: 4
+ stepCounts:
+ 0: 10
+ 1: 4
+ stepFeatures:
+ 0: 10
+ 1: 4
+HLT_xe100_pfopufit_L1XE50:
+ eventCount: 3
+ stepCounts:
+ 0: 10
+ 1: 3
+ stepFeatures:
+ 0: 10
+ 1: 3
+HLT_xe100_pfsum_L1XE50:
+ eventCount: 3
+ stepCounts:
+ 0: 10
+ 1: 3
+ stepFeatures:
+ 0: 10
+ 1: 3
+HLT_xe100_tcpufit_L1XE50:
+ eventCount: 6
+ stepCounts:
+ 0: 6
+ stepFeatures:
+ 0: 6
+HLT_xe100_trkmht_L1XE50:
+ eventCount: 7
+ stepCounts:
+ 0: 10
+ 1: 7
+ stepFeatures:
+ 0: 10
+ 1: 7
+HLT_xe100_trkmht_xe85_tcpufit_xe65_cell_L1XE50:
+ eventCount: 5
+ stepCounts:
+ 0: 6
+ 1: 5
+ stepFeatures:
+ 0: 6
+ 1: 5
+HLT_xe110_mht_L1XE50:
+ eventCount: 7
+ stepCounts:
+ 0: 7
+ stepFeatures:
+ 0: 7
+HLT_xe110_tc_em_L1XE50:
+ eventCount: 5
+ stepCounts:
+ 0: 5
+ stepFeatures:
+ 0: 5
+HLT_xe110_tcpufit_L1XE50:
+ eventCount: 6
+ stepCounts:
+ 0: 6
+ stepFeatures:
+ 0: 6
+HLT_xe30_cell_L1XE10:
+ eventCount: 17
+ stepCounts:
+ 0: 17
+ stepFeatures:
+ 0: 17
+HLT_xe30_cell_xe30_tcpufit_L1XE10:
+ eventCount: 14
+ stepCounts:
+ 0: 14
+ stepFeatures:
+ 0: 14
+HLT_xe30_cvfpufit_L1XE10:
+ eventCount: 14
+ stepCounts:
+ 0: 19
+ 1: 14
+ stepFeatures:
+ 0: 19
+ 1: 14
+HLT_xe30_mht_L1XE10:
+ eventCount: 19
+ stepCounts:
+ 0: 19
+ stepFeatures:
+ 0: 19
+HLT_xe30_mhtpufit_em_subjesgscIS_L1XE10:
+ eventCount: 12
+ stepCounts:
+ 0: 19
+ 1: 12
+ stepFeatures:
+ 0: 19
+ 1: 12
+HLT_xe30_mhtpufit_pf_subjesgscIS_L1XE10:
+ eventCount: 14
+ stepCounts:
+ 0: 19
+ 1: 14
+ stepFeatures:
+ 0: 19
+ 1: 14
+HLT_xe30_pfopufit_L1XE10:
+ eventCount: 15
+ stepCounts:
+ 0: 19
+ 1: 15
+ stepFeatures:
+ 0: 19
+ 1: 15
+HLT_xe30_pfsum_L1XE10:
+ eventCount: 16
+ stepCounts:
+ 0: 19
+ 1: 16
+ stepFeatures:
+ 0: 19
+ 1: 16
+HLT_xe30_tcpufit_L1XE10:
+ eventCount: 14
+ stepCounts:
+ 0: 14
+ stepFeatures:
+ 0: 14
+HLT_xe30_trkmht_L1XE10:
+ eventCount: 15
+ stepCounts:
+ 0: 19
+ 1: 15
+ stepFeatures:
+ 0: 19
+ 1: 15
+HLT_xe65_cell_L1XE50:
+ eventCount: 7
+ stepCounts:
+ 0: 7
+ stepFeatures:
+ 0: 7
+HLT_xe65_cell_xe110_tcpufit_L1XE50:
+ eventCount: 5
+ stepCounts:
+ 0: 5
+ stepFeatures:
+ 0: 5
+HLT_xe80_tcpufit_unconvtrk120_isohpttrack_icummedium_L1XE50:
+ eventCount: 0
+HLT_xe80_tcpufit_unconvtrk120_isohpttrack_imedium_L1XE50:
+ eventCount: 5
+ stepCounts:
+ 0: 5
+ stepFeatures:
+ 0: 5
+HLT_xe80_tcpufit_unconvtrk80_isohpttrack_imedium_L1XE50:
+ eventCount: 6
+ stepCounts:
+ 0: 6
+ stepFeatures:
+ 0: 6
+HLT_xe95_trkmht_xe90_tcpufit_xe75_cell_L1XE50:
+ eventCount: 4
+ stepCounts:
+ 0: 4
+ 1: 4
+ stepFeatures:
+ 0: 4
+ 1: 4
diff --git a/Trigger/TrigValidation/TrigAnalysisTest/test/test_trigAna_RDOtoRDOTrig_v1Dev_build.py b/Trigger/TrigValidation/TrigAnalysisTest/test/test_trigAna_RDOtoRDOTrig_v1Dev_build.py
index 4b812d2da731745aee6cec83a5f6473b53422d41..4f9c61a1faa0a064613760676e4e76e47255c334 100755
--- a/Trigger/TrigValidation/TrigAnalysisTest/test/test_trigAna_RDOtoRDOTrig_v1Dev_build.py
+++ b/Trigger/TrigValidation/TrigAnalysisTest/test/test_trigAna_RDOtoRDOTrig_v1Dev_build.py
@@ -27,13 +27,13 @@ test.art_type = 'build'
test.exec_steps = [ex]
test.check_steps = CheckSteps.default_check_steps(test)
-# Add a step comparing counts in the log against reference
-refcomp = CheckSteps.RegTestStep("CountRefComp")
-refcomp.input_base_name = 'athena.merged'
-refcomp.regex = r'TrigSignatureMoniMT\s*INFO\sHLT_.*|TrigSignatureMoniMT\s*INFO\s-- #[0-9]+ (Events|Features).*'
-refcomp.reference = 'TrigAnalysisTest/ref_RDOtoRDOTrig_v1Dev_build.ref'
+# Add a step comparing counts against a reference
+chaindump = test.get_step("ChainDump")
+chaindump.args = '--json --yaml ref_RDOtoRDOTrig_v1Dev_build.new'
+refcomp = CheckSteps.ChainCompStep("CountRefComp")
+refcomp.input_file = 'ref_RDOtoRDOTrig_v1Dev_build.new'
refcomp.required = True # Final exit code depends on this step
-CheckSteps.add_step_after_type(test.check_steps, CheckSteps.LogMergeStep, refcomp)
+CheckSteps.add_step_after_type(test.check_steps, CheckSteps.ChainDumpStep, refcomp)
import sys
sys.exit(test.run())
diff --git a/Trigger/TrigValidation/TrigValTools/bin/chainComp.py b/Trigger/TrigValidation/TrigValTools/bin/chainComp.py
new file mode 100755
index 0000000000000000000000000000000000000000..2057052fd04099d56d33b69d1b97524122ad1086
--- /dev/null
+++ b/Trigger/TrigValidation/TrigValTools/bin/chainComp.py
@@ -0,0 +1,230 @@
+#!/usr/bin/env python
+#
+# Copyright (C) 2002-2020 CERN for the benefit of the ATLAS collaboration
+#
+
+'''
+Script to compare trigger chain counts in YAML format produced by
+chainDump.py --yaml and providing information and instructions for
+updating counts reference in the athena repository.
+'''
+
+import sys
+import os
+import argparse
+import logging
+import yaml
+import glob
+import subprocess
+from AthenaCommon.Utils import unixtools
+from TrigValTools.TrigValSteering.Common import package_prefix_dict as packages
+from TrigValTools.TrigValSteering.Common import running_in_CI
+
+
+def get_parser():
+ parser = argparse.ArgumentParser(usage='%(prog)s [options] inputFile',
+ description=__doc__)
+ parser.add_argument('inputFile',
+ metavar='PATH',
+ help='Name of input counts file')
+ parser.add_argument('-r', '--referenceFile',
+ metavar='PATH',
+ help='Name of reference counts file. If empty, try to guess from inputFile')
+ parser.add_argument('-s', '--sourceRepository',
+ metavar='PATH',
+ help='Path to the git checkout of the athena repository.'
+ 'If empty, try to guess from the environment')
+ parser.add_argument('-v', '--verbose',
+ action='store_true',
+ help='Increase output verbosity')
+ return parser
+
+
+def find_reference(inputFile):
+ ref_path = None
+ if inputFile.endswith('.new'):
+ inp_name = os.path.split(inputFile)[-1]
+ ref_name = inp_name[0:-4] + '.ref'
+ logging.debug('Searching for file %s in DATAPATH', ref_name)
+ for pkg_name in packages:
+ ref_path = unixtools.find_datafile(pkg_name+'/'+ref_name)
+ if ref_path:
+ break
+ if ref_path:
+ logging.debug('Found %s', ref_path)
+ else:
+ logging.debug('Not found')
+ return ref_path
+
+
+def find_repository(ref_path):
+ '''
+ Try to find the athena git repository based on paths in env.
+ Needs to work both in local WorkDir build and in full/incremental CI build.
+ '''
+ logging.debug('Searching for the source repository path')
+ search_str = '/Trigger/TrigValidation'
+ def try_path(p):
+ logging.debug('Trying %s', p)
+ if os.path.islink(p) and os.path.isfile(p) and search_str in os.path.realpath(p):
+ candidate = os.path.realpath(p).split(search_str)[0]
+ logging.debug('Candidate %s', candidate)
+ if os.path.isdir(candidate + '/.git'):
+ return candidate
+ return None
+
+ result = try_path(ref_path)
+ if result:
+ return result
+
+ env_vars = ['DATAPATH', 'JOBOPTSEARCHPATH', 'CALIBPATH', 'XMLPATH']
+ path_lists = [os.getenv(var).split(os.pathsep) for var in env_vars]
+ max_len = max([len(pl) for pl in path_lists])
+ max_len = min(max_len, 2) # Limit to first two paths to avoid very deep and slow search
+ for i in range(max_len):
+ for pl in path_lists:
+ if i >= len(pl):
+ continue
+ paths = glob.glob(pl[i]+'/**', recursive=True)
+ for p in paths:
+ result = try_path(p)
+ if result:
+ return result
+ return None
+
+
+def load_yaml(path):
+ result = None
+ if not os.path.isfile(path):
+ logging.error('Not a file: %s', path)
+ return result
+ with open(path) as f:
+ result = yaml.safe_load(f)
+ return result
+
+
+def print_event_diff(inp_data, ref_data, key):
+ if inp_data[key] != ref_data[key]:
+ logging.info(' %s: %d -> %d', key, ref_data[key], inp_data[key])
+
+
+def print_step_diff(inp_data, ref_data, key):
+ if inp_data[key] != ref_data[key]:
+ logging.info(' %s:', key)
+ for step in range(max(len(inp_data[key]), len(ref_data[key]))):
+ inp_count = inp_data[key][step] if step in inp_data[key] else 0
+ ref_count = ref_data[key][step] if step in ref_data[key] else 0
+ if inp_count != ref_count:
+ logging.info(' %d: %d -> %d', step, ref_count, inp_count)
+
+
+def print_diff(inp_dict, ref_dict):
+ retcode = 0
+ chains_not_in_ref = [c[0] for c in inp_dict.items() if c[0] not in ref_dict]
+ chains_not_in_inp = [c[0] for c in ref_dict.items() if c[0] not in inp_dict]
+ chains_count_diff = [c[0] for c in inp_dict.items() if c[0] in ref_dict and c[1] != ref_dict[c[0]]]
+
+ # New chains (missing in reference)
+ n_new_chains = len(chains_not_in_ref)
+ if n_new_chains > 0:
+ retcode = 1
+ logging.info('Found %d new chain%s added:', n_new_chains, 's' if n_new_chains > 1 else '')
+ for chain_name in chains_not_in_ref:
+ logging.info(' %s', chain_name)
+
+ # Removed chains (missing in test file)
+ n_removed_chains = len(chains_not_in_inp)
+ if n_removed_chains > 0:
+ retcode = 1
+ logging.info('Found %d chain%s removed:', n_removed_chains, 's' if n_removed_chains > 1 else '')
+ for chain_name in chains_not_in_inp:
+ logging.info(' %s', chain_name)
+
+ # Count differences
+ n_diff_chains = len(chains_count_diff)
+ if n_diff_chains > 0:
+ retcode = 1
+ logging.info('Found %d chain%s with count differences:', n_diff_chains, 's' if n_diff_chains > 1 else '')
+ for chain_name in chains_count_diff:
+ logging.info(' %s:', chain_name)
+ inp_data = inp_dict[chain_name]
+ ref_data = ref_dict[chain_name]
+ print_event_diff(inp_data, ref_data, 'eventCount')
+ print_step_diff(inp_data, ref_data, 'stepCounts')
+ print_step_diff(inp_data, ref_data, 'stepFeatures')
+
+ return retcode
+
+
+def create_patch(inp_path, ref_path):
+ def find_ref_package():
+ for path in [ref_path, find_reference(inp_path), find_reference(ref_path)]:
+ for pkg in packages:
+ if '/data/'+pkg in ref_path:
+ return pkg, os.path.split(path)[1]
+ return None, None
+ package_name, ref_file_name = find_ref_package()
+ if not package_name:
+ logging.warning('Failed to find reference package name, cannot create git patch file')
+ return
+
+ ref_rel_path = '/Trigger/TrigValidation/' + package_name + '/share/' + ref_file_name
+
+ diff_cmd = 'diff -U 1 -b'
+ diff_cmd += ' --label a' + ref_rel_path + ' ' + ref_path
+ diff_cmd += ' --label b' + ref_rel_path + ' ' + inp_path
+
+ diff_txt = subprocess.getoutput(diff_cmd)
+ patch_name = os.path.split(ref_path)[1]
+ if patch_name.endswith('.ref') or patch_name.endswith('.new'):
+ patch_name = patch_name[0:-4]
+ patch_name += '.patch'
+ with open(patch_name, 'w') as patch_file:
+ patch_file.write('diff --git a{p:s} b{p:s}\n'.format(p=ref_rel_path))
+ patch_file.write(diff_txt + '\n')
+ logging.info('Patch file created. To apply, run in the athena source directory:')
+ logging.info('git apply %s/%s', os.getcwd(), patch_name)
+ logging.info('Then check with git diff and, if everything is correct, add and commit')
+ if running_in_CI():
+ logging.info('or see the patch below:\n')
+ subprocess.call('cat ' + patch_name, shell=True)
+ print('\n') # noqa: ATL901
+
+
+def main():
+ args = get_parser().parse_args()
+ logging.basicConfig(stream=sys.stdout,
+ format='chainComp %(levelname)-8s %(message)s',
+ level=logging.DEBUG if args.verbose else logging.INFO)
+
+ inp_path = args.inputFile
+ ref_path = args.referenceFile or find_reference(inp_path)
+ if not ref_path:
+ logging.error('No reference file specified and couldn\'t guess from '
+ 'input name. Please use the -r argument (see --help).')
+ return 1
+
+ logging.info('Test file: %s', inp_path)
+ logging.info('Reference file: %s', ref_path)
+
+ # Currently not used, but ready for implementing checks against upstream
+ # src_path = args.sourceRepository or find_repository(ref_path)
+ # logging.info('Repository path: %s', src_path)
+
+ inp_dict = load_yaml(inp_path)
+ ref_dict = load_yaml(ref_path)
+ if (not inp_dict) or (not ref_dict):
+ return 1
+
+ retcode = print_diff(inp_dict, ref_dict)
+ if retcode:
+ logging.error('Trigger counts differ from the reference. If the above differences are intended, update the reference')
+ create_patch(inp_path, ref_path)
+ else:
+ logging.info('Trigger counts match the reference')
+
+ return retcode
+
+
+if '__main__' in __name__:
+ sys.exit(main())
diff --git a/Trigger/TrigValidation/TrigValTools/bin/runTrigART.py b/Trigger/TrigValidation/TrigValTools/bin/runTrigART.py
index fccc693b67e13d76dc5610c3f6b24ea91da60233..fdf516b859589bcae8749beec7ad2229c5076574 100755
--- a/Trigger/TrigValidation/TrigValTools/bin/runTrigART.py
+++ b/Trigger/TrigValidation/TrigValTools/bin/runTrigART.py
@@ -145,6 +145,32 @@ def print_summary(all_test_results, failed_tests):
logging.info("==================================================")
+def print_failed_ref_comp(all_test_results, failed_tests):
+ if len(failed_tests) == 0:
+ return
+
+ step_name = 'CountRefComp'
+ for test_name in failed_tests:
+ athena_failed = False
+ refcomp_failed = False
+ test_results = all_test_results[test_name]
+ for step in test_results['result']:
+ if step['name'] in ['athena', 'athenaHLT', 'Reco_tf', 'CheckLog'] and step['result'] != 0:
+ athena_failed = True
+ if step['name'] == step_name and step['result'] != 0:
+ refcomp_failed = True
+
+ # Print only if athena didn't fail, as a failed job will always give wrong counts
+ if refcomp_failed and not athena_failed:
+ log_path = 'results/runTrigART/{:s}/{:s}.log'.format(os.path.splitext(test_name)[0], step_name)
+ if not os.path.isfile(log_path):
+ continue
+ logging.info("==================================================")
+ logging.info('Printing output of failed CountRefComp for %s', test_name)
+ subprocess.call('cat ' + log_path, shell=True)
+ logging.info("==================================================")
+
+
def prep_dirs(topdir, scripts):
""" Creates test result structure if missing, if present clears the area only for the tests to be run"""
import errno
@@ -217,6 +243,7 @@ def main():
logging.warning("Selected %d tests but ART executed only %d. Please check why some tests did not run!")
failed_tests = analyse_results(all_test_results)
print_summary(all_test_results, failed_tests)
+ print_failed_ref_comp(all_test_results, failed_tests)
if len(failed_tests) > 0:
success = False
diff --git a/Trigger/TrigValidation/TrigValTools/python/TrigValSteering/CheckSteps.py b/Trigger/TrigValidation/TrigValTools/python/TrigValSteering/CheckSteps.py
index 7d1aa4b3bac8b738e14eff018a05f98e6fa9305c..4793d995a30035bcb9ab1f2208e363bc0abb167e 100644
--- a/Trigger/TrigValidation/TrigValTools/python/TrigValSteering/CheckSteps.py
+++ b/Trigger/TrigValidation/TrigValTools/python/TrigValSteering/CheckSteps.py
@@ -475,6 +475,27 @@ class ChainDumpStep(InputDependentStep):
super(ChainDumpStep, self).configure(test)
+class ChainCompStep(Step):
+ '''
+ Execute chainComp.py to compare counts from chainDump.py to a reference
+ '''
+
+ def __init__(self, name='ChainComp'):
+ super(ChainCompStep, self).__init__(name)
+ self.input_file = 'chainDump.yml'
+ self.reference = None
+ self.executable = 'chainComp.py'
+ self.args = ''
+ self.auto_report_result = True
+ self.output_stream = Step.OutputStream.FILE_AND_STDOUT
+
+ def configure(self, test):
+ if self.reference:
+ self.args += ' -r ' + self.reference
+ self.args += ' ' + self.input_file
+ super(ChainCompStep, self).configure(test)
+
+
class TrigTestJsonStep(Step):
'''Execute trig-test-json.py to create extra-results.json file'''
diff --git a/Trigger/TrigValidation/TriggerTest/share/ref_data_v1Dev_build.ref b/Trigger/TrigValidation/TriggerTest/share/ref_data_v1Dev_build.ref
index 693baf88e03d1e837027d79c4ed5d40f23f387ed..3c3185943ca28aba5d09b57de9f941be7c42b36b 100644
--- a/Trigger/TrigValidation/TriggerTest/share/ref_data_v1Dev_build.ref
+++ b/Trigger/TrigValidation/TriggerTest/share/ref_data_v1Dev_build.ref
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+HLT_mu28_ivarmedium_L1MU20:
+ eventCount: 0
+ stepCounts:
+ 0: 1
+ 1: 1
+ stepFeatures:
+ 0: 1
+ 1: 1
+HLT_mu28_mu8noL1_L1MU20:
+ eventCount: 0
+ stepCounts:
+ 0: 1
+ 1: 1
+ stepFeatures:
+ 0: 1
+ 1: 1
+HLT_mu35_ivarmedium_L1MU20:
+ eventCount: 0
+ stepCounts:
+ 0: 1
+ 1: 1
+ stepFeatures:
+ 0: 1
+ 1: 1
+HLT_mu4_l2io_L1MU4:
+ eventCount: 0
+ stepCounts:
+ 0: 4
+ 1: 3
+ stepFeatures:
+ 0: 5
+ 1: 4
+HLT_mu50_L1MU20:
+ eventCount: 0
+ stepCounts:
+ 0: 1
+ 1: 1
+ stepFeatures:
+ 0: 1
+ 1: 1
+HLT_mu50_RPCPEBSecondaryReadout_L1MU20:
+ eventCount: 0
+ stepCounts:
+ 0: 1
+ 1: 1
+ stepFeatures:
+ 0: 1
+ 1: 1
+HLT_mu60_0eta105_msonly_L1MU20:
+ eventCount: 0
+HLT_mu60_L1MU20:
+ eventCount: 0
+ stepCounts:
+ 0: 1
+ 1: 1
+ stepFeatures:
+ 0: 1
+ 1: 1
+HLT_mu6_L1MU6:
+ eventCount: 0
+ stepCounts:
+ 0: 2
+ 1: 2
+ stepFeatures:
+ 0: 2
+ 1: 2
+HLT_mu6_idperf_L1MU6:
+ eventCount: 0
+ stepCounts:
+ 0: 2
+ 1: 2
+ stepFeatures:
+ 0: 2
+ 1: 2
+HLT_mu6_ivarmedium_L1MU6:
+ eventCount: 0
+ stepCounts:
+ 0: 2
+ 1: 2
+ stepFeatures:
+ 0: 2
+ 1: 2
+HLT_mu6_j45_nojcalib_L1J20:
+ eventCount: 0
+HLT_mu6_msonly_L1MU6:
+ eventCount: 0
+ stepCounts:
+ 0: 2
+ stepFeatures:
+ 0: 2
+HLT_mu6_mu4_L12MU4:
+ eventCount: 0
+ stepCounts:
+ 0: 1
+ 1: 1
+ stepFeatures:
+ 0: 2
+ 1: 2
+HLT_mu6_mu6noL1_L1MU6:
+ eventCount: 0
+ stepCounts:
+ 0: 2
+ 1: 2
+ stepFeatures:
+ 0: 2
+ 1: 2
+HLT_mu6_xe30_mht_L1XE10:
+ eventCount: 0
+ stepCounts:
+ 0: 2
+ 1: 2
+ stepFeatures:
+ 0: 2
+ 1: 2
+HLT_mu80_L1MU20:
+ eventCount: 0
+ stepCounts:
+ 0: 1
+ 1: 1
+ stepFeatures:
+ 0: 1
+ 1: 1
+HLT_mu80_msonly_3layersEC_L1MU20:
+ eventCount: 0
+ stepCounts:
+ 0: 1
+ stepFeatures:
+ 0: 1
+HLT_mu8_L1MU6:
+ eventCount: 0
+ stepCounts:
+ 0: 2
+ 1: 2
+ stepFeatures:
+ 0: 2
+ 1: 2
+HLT_noalg_L1All:
+ eventCount: 20
+HLT_noalg_L1Calo:
+ eventCount: 20
+HLT_noalg_L1Calo_EMPTY:
+ eventCount: 20
+HLT_noalg_L1EM10VH:
+ eventCount: 20
+HLT_noalg_L1EM12:
+ eventCount: 20
+HLT_noalg_L1EM15:
+ eventCount: 20
+HLT_noalg_L1EM15VH:
+ eventCount: 20
+HLT_noalg_L1EM20VH:
+ eventCount: 20
+HLT_noalg_L1EM22VHI:
+ eventCount: 20
+HLT_noalg_L1EM3:
+ eventCount: 20
+HLT_noalg_L1EM7:
+ eventCount: 20
+HLT_noalg_L1EM8VH:
+ eventCount: 20
+HLT_noalg_L1J100:
+ eventCount: 20
+HLT_noalg_L1J15:
+ eventCount: 20
+HLT_noalg_L1J20:
+ eventCount: 20
+HLT_noalg_L1J25:
+ eventCount: 20
+HLT_noalg_L1J30:
+ eventCount: 20
+HLT_noalg_L1J40:
+ eventCount: 20
+HLT_noalg_L1J400:
+ eventCount: 20
+HLT_noalg_L1J50:
+ eventCount: 20
+HLT_noalg_L1J75:
+ eventCount: 20
+HLT_noalg_L1J85:
+ eventCount: 20
+HLT_noalg_L1MBTS_1_1_EMPTY:
+ eventCount: 20
+HLT_noalg_L1MBTS_1_EMPTY:
+ eventCount: 20
+HLT_noalg_L1MBTS_2_EMPTY:
+ eventCount: 20
+HLT_noalg_L1RD0_EMPTY:
+ eventCount: 20
+HLT_noalg_L1RD0_FILLED:
+ eventCount: 20
+HLT_noalg_L1Standby:
+ eventCount: 20
+HLT_noalg_L1TAU12:
+ eventCount: 20
+HLT_noalg_L1TAU12IM:
+ eventCount: 20
+HLT_noalg_L1TAU20IM:
+ eventCount: 20
+HLT_noalg_L1TAU30:
+ eventCount: 20
+HLT_noalg_L1TAU40:
+ eventCount: 20
+HLT_noalg_L1TAU60:
+ eventCount: 20
+HLT_noalg_L1XE10:
+ eventCount: 20
+HLT_noalg_L1XE30:
+ eventCount: 20
+HLT_noalg_L1XE300:
+ eventCount: 20
+HLT_noalg_L1XE35:
+ eventCount: 20
+HLT_noalg_L1XE40:
+ eventCount: 20
+HLT_noalg_L1XE45:
+ eventCount: 20
+HLT_noalg_L1XE50:
+ eventCount: 20
+HLT_noalg_L1XE55:
+ eventCount: 20
+HLT_noalg_L1XE60:
+ eventCount: 20
+HLT_noalg_L1XE70:
+ eventCount: 20
+HLT_noalg_L1XE80:
+ eventCount: 20
+HLT_noalg_bkg_L1Bkg:
+ eventCount: 20
+HLT_noalg_cosmiccalo_L1EM3_EMPTY:
+ eventCount: 15
+HLT_noalg_cosmiccalo_L1EM7_EMPTY:
+ eventCount: 9
+HLT_noalg_cosmiccalo_L1J12_EMPTY:
+ eventCount: 8
+HLT_noalg_cosmiccalo_L1J12_FIRSTEMPTY:
+ eventCount: 8
+HLT_noalg_cosmiccalo_L1J30_31ETA49_EMPTY:
+ eventCount: 1
+HLT_noalg_cosmiccalo_L1J30_EMPTY:
+ eventCount: 4
+HLT_noalg_cosmiccalo_L1J30_FIRSTEMPTY:
+ eventCount: 4
+HLT_noalg_cosmiccalo_L1RD1_EMPTY:
+ eventCount: 20
+HLT_noalg_eb_L1ABORTGAPNOTCALIB_noPS:
+ eventCount: 20
+HLT_noalg_eb_L1EMPTY_noPS:
+ eventCount: 20
+HLT_noalg_eb_L1FIRSTEMPTY_noPS:
+ eventCount: 20
+HLT_noalg_eb_L1PhysicsHigh_noPS:
+ eventCount: 20
+HLT_noalg_eb_L1PhysicsVeryHigh_noPS:
+ eventCount: 20
+HLT_noalg_eb_L1RD3_EMPTY:
+ eventCount: 20
+HLT_noalg_eb_L1RD3_FILLED:
+ eventCount: 20
+HLT_noalg_eb_L1UNPAIRED_ISO_noPS:
+ eventCount: 20
+HLT_noalg_eb_L1UNPAIRED_NONISO_noPS:
+ eventCount: 20
+HLT_noalg_idmon_L1RD0_EMPTY:
+ eventCount: 20
+HLT_noalg_idmon_L1RD0_FILLED:
+ eventCount: 20
+HLT_noalg_idmon_L1RD0_UNPAIRED_ISO:
+ eventCount: 20
+HLT_noalg_l1calo_L1J400:
+ eventCount: 20
+HLT_noalg_mb_L1RD2_EMPTY:
+ eventCount: 20
+HLT_noalg_zb_L1ZB:
+ eventCount: 20
+HLT_sct_noise_SCTPEB_L1RD0_EMPTY:
+ eventCount: 20
+ stepCounts:
+ 0: 20
+ stepFeatures:
+ 0: 20
+HLT_tau0_perf_ptonly_L1TAU100:
+ eventCount: 0
+HLT_tau0_perf_ptonly_L1TAU12:
+ eventCount: 4
+ stepCounts:
+ 0: 4
+ 1: 4
+ 2: 4
+ 3: 4
+ stepFeatures:
+ 0: 5
+ 1: 5
+ 2: 4
+ 3: 4
+HLT_tau0_perf_ptonly_L1TAU60:
+ eventCount: 0
+HLT_tau160_idperf_track_L1TAU100:
+ eventCount: 0
+HLT_tau160_idperf_tracktwoMVA_L1TAU100:
+ eventCount: 0
+HLT_tau160_idperf_tracktwo_L1TAU100:
+ eventCount: 0
+HLT_tau160_medium1_tracktwoEF_L1TAU100:
+ eventCount: 0
+HLT_tau160_medium1_tracktwo_L1TAU100:
+ eventCount: 0
+HLT_tau160_mediumRNN_tracktwoMVA_L1TAU100:
+ eventCount: 0
+HLT_tau160_perf_tracktwoMVA_L1TAU100:
+ eventCount: 0
+HLT_tau160_perf_tracktwo_L1TAU100:
+ eventCount: 0
+HLT_tau200_medium1_tracktwoEF_L1TAU100:
+ eventCount: 0
+HLT_tau200_mediumRNN_tracktwoMVA_L1TAU100:
+ eventCount: 0
+HLT_tau25_idperf_track_L1TAU12IM:
+ eventCount: 3
+ stepCounts:
+ 0: 3
+ 1: 3
+ 2: 3
+ 3: 3
+ 4: 3
+ stepFeatures:
+ 0: 4
+ 1: 4
+ 2: 4
+ 3: 3
+ 4: 3
+HLT_tau25_idperf_tracktwoMVA_L1TAU12IM:
+ eventCount: 3
+ stepCounts:
+ 0: 3
+ 1: 3
+ 2: 3
+ 3: 3
+ 4: 3
+ stepFeatures:
+ 0: 4
+ 1: 4
+ 2: 3
+ 3: 3
+ 4: 3
+HLT_tau25_idperf_tracktwo_L1TAU12IM:
+ eventCount: 3
+ stepCounts:
+ 0: 3
+ 1: 3
+ 2: 3
+ 3: 3
+ 4: 3
+ 5: 3
+ stepFeatures:
+ 0: 4
+ 1: 4
+ 2: 3
+ 3: 3
+ 4: 3
+ 5: 3
+HLT_tau25_looseRNN_tracktwoMVA_L1TAU12IM:
+ eventCount: 2
+ stepCounts:
+ 0: 3
+ 1: 3
+ 2: 3
+ 3: 3
+ 4: 2
+ stepFeatures:
+ 0: 4
+ 1: 4
+ 2: 3
+ 3: 3
+ 4: 2
+HLT_tau25_looseRNN_tracktwo_L1TAU12IM:
+ eventCount: 0
+ stepCounts:
+ 0: 3
+ 1: 3
+ 2: 3
+ stepFeatures:
+ 0: 4
+ 1: 4
+ 2: 3
+HLT_tau25_medium1_tracktwoEF_L1TAU12IM:
+ eventCount: 0
+ stepCounts:
+ 0: 3
+ 1: 3
+ 2: 3
+ 3: 3
+ stepFeatures:
+ 0: 4
+ 1: 4
+ 2: 3
+ 3: 3
+HLT_tau25_medium1_tracktwoMVA_L1TAU12IM:
+ eventCount: 0
+ stepCounts:
+ 0: 3
+ 1: 3
+ 2: 3
+ 3: 3
+ stepFeatures:
+ 0: 4
+ 1: 4
+ 2: 3
+ 3: 3
+HLT_tau25_medium1_tracktwo_L1TAU12IM:
+ eventCount: 0
+ stepCounts:
+ 0: 3
+ 1: 3
+ 2: 3
+ stepFeatures:
+ 0: 4
+ 1: 4
+ 2: 3
+HLT_tau25_mediumRNN_tracktwoMVA_L1TAU12IM:
+ eventCount: 1
+ stepCounts:
+ 0: 3
+ 1: 3
+ 2: 3
+ 3: 3
+ 4: 1
+ stepFeatures:
+ 0: 4
+ 1: 4
+ 2: 3
+ 3: 3
+ 4: 1
+HLT_tau25_mediumRNN_tracktwo_L1TAU12IM:
+ eventCount: 0
+ stepCounts:
+ 0: 3
+ 1: 3
+ 2: 3
+ stepFeatures:
+ 0: 4
+ 1: 4
+ 2: 3
+HLT_tau25_perf_tracktwoMVA_L1TAU12IM:
+ eventCount: 3
+ stepCounts:
+ 0: 3
+ 1: 3
+ 2: 3
+ 3: 3
+ 4: 3
+ stepFeatures:
+ 0: 4
+ 1: 4
+ 2: 3
+ 3: 3
+ 4: 3
+HLT_tau25_perf_tracktwo_L1TAU12IM:
+ eventCount: 3
+ stepCounts:
+ 0: 3
+ 1: 3
+ 2: 3
+ 3: 3
+ 4: 3
+ 5: 3
+ stepFeatures:
+ 0: 4
+ 1: 4
+ 2: 3
+ 3: 3
+ 4: 3
+ 5: 3
+HLT_tau25_tightRNN_tracktwoMVA_L1TAU12IM:
+ eventCount: 1
+ stepCounts:
+ 0: 3
+ 1: 3
+ 2: 3
+ 3: 3
+ 4: 1
+ stepFeatures:
+ 0: 4
+ 1: 4
+ 2: 3
+ 3: 3
+ 4: 1
+HLT_tau25_tightRNN_tracktwo_L1TAU12IM:
+ eventCount: 0
+ stepCounts:
+ 0: 3
+ 1: 3
+ 2: 3
+ stepFeatures:
+ 0: 4
+ 1: 4
+ 2: 3
+HLT_tau25_verylooseRNN_tracktwoMVA_L1TAU12IM:
+ eventCount: 2
+ stepCounts:
+ 0: 3
+ 1: 3
+ 2: 3
+ 3: 3
+ 4: 2
+ stepFeatures:
+ 0: 4
+ 1: 4
+ 2: 3
+ 3: 3
+ 4: 2
+HLT_tau25_verylooseRNN_tracktwo_L1TAU12IM:
+ eventCount: 0
+ stepCounts:
+ 0: 3
+ 1: 3
+ 2: 3
+ stepFeatures:
+ 0: 4
+ 1: 4
+ 2: 3
+HLT_tau35_mediumRNN_tracktwoMVA_L1TAU12IM:
+ eventCount: 1
+ stepCounts:
+ 0: 3
+ 1: 3
+ 2: 3
+ 3: 3
+ 4: 1
+ stepFeatures:
+ 0: 4
+ 1: 4
+ 2: 3
+ 3: 3
+ 4: 1
+HLT_tau35_mediumRNN_tracktwoMVA_tau25_mediumRNN_tracktwoMVA_L1DR-TAU20ITAU12I-J25:
+ eventCount: 0
+ stepCounts:
+ 0: 1
+ 1: 1
+ stepFeatures:
+ 0: 2
+ 1: 2
+HLT_tau80_medium1_tracktwo_L1TAU60:
+ eventCount: 0
+HLT_tau80_mediumRNN_tracktwoMVA_tau35_mediumRNN_tracktwoMVA_L1TAU60_DR-TAU20ITAU12I:
+ eventCount: 0
+HLT_tau80_mediumRNN_tracktwoMVA_tau60_mediumRNN_tracktwoMVA_L1TAU60_2TAU40:
+ eventCount: 0
+HLT_tilecalib_laser_TilePEB_L1CALREQ2:
+ eventCount: 20
+ stepCounts:
+ 0: 20
+ stepFeatures:
+ 0: 20
+HLT_timeburner_L1All:
+ eventCount: 0
+HLT_unconvtrk120_isohpttrack_icummedium_L1XE50:
+ eventCount: 3
+ stepCounts:
+ 0: 3
+ stepFeatures:
+ 0: 4
+HLT_unconvtrk120_isohpttrack_imedium_L1XE50:
+ eventCount: 9
+ stepCounts:
+ 0: 9
+ stepFeatures:
+ 0: 13
+HLT_xe100_cvfpufit_L1XE50:
+ eventCount: 0
+ stepCounts:
+ 0: 20
+ stepFeatures:
+ 0: 20
+HLT_xe100_mht_L1XE50:
+ eventCount: 1
+ stepCounts:
+ 0: 1
+ stepFeatures:
+ 0: 1
+HLT_xe100_mhtpufit_em_subjesgscIS_L1XE50:
+ eventCount: 0
+ stepCounts:
+ 0: 20
+ stepFeatures:
+ 0: 20
+HLT_xe100_mhtpufit_pf_subjesgscIS_L1XE50:
+ eventCount: 1
+ stepCounts:
+ 0: 20
+ 1: 1
+ stepFeatures:
+ 0: 20
+ 1: 1
+HLT_xe100_pfopufit_L1XE50:
+ eventCount: 0
+ stepCounts:
+ 0: 20
+ stepFeatures:
+ 0: 20
+HLT_xe100_pfsum_L1XE50:
+ eventCount: 1
+ stepCounts:
+ 0: 20
+ 1: 1
+ stepFeatures:
+ 0: 20
+ 1: 1
+HLT_xe100_tcpufit_L1XE50:
+ eventCount: 0
+HLT_xe100_trkmht_L1XE50:
+ eventCount: 0
+ stepCounts:
+ 0: 20
+ stepFeatures:
+ 0: 20
+HLT_xe100_trkmht_xe85_tcpufit_xe65_cell_L1XE50:
+ eventCount: 0
+HLT_xe110_mht_L1XE50:
+ eventCount: 1
+ stepCounts:
+ 0: 1
+ stepFeatures:
+ 0: 1
+HLT_xe110_tc_em_L1XE50:
+ eventCount: 0
+HLT_xe110_tcpufit_L1XE50:
+ eventCount: 0
+HLT_xe30_cell_L1XE10:
+ eventCount: 3
+ stepCounts:
+ 0: 3
+ stepFeatures:
+ 0: 3
+HLT_xe30_cell_xe30_tcpufit_L1XE10:
+ eventCount: 3
+ stepCounts:
+ 0: 3
+ stepFeatures:
+ 0: 3
+HLT_xe30_cvfpufit_L1XE10:
+ eventCount: 6
+ stepCounts:
+ 0: 20
+ 1: 6
+ stepFeatures:
+ 0: 20
+ 1: 6
+HLT_xe30_mht_L1XE10:
+ eventCount: 14
+ stepCounts:
+ 0: 14
+ stepFeatures:
+ 0: 14
+HLT_xe30_mhtpufit_em_subjesgscIS_L1XE10:
+ eventCount: 5
+ stepCounts:
+ 0: 20
+ 1: 5
+ stepFeatures:
+ 0: 20
+ 1: 5
+HLT_xe30_mhtpufit_pf_subjesgscIS_L1XE10:
+ eventCount: 5
+ stepCounts:
+ 0: 20
+ 1: 5
+ stepFeatures:
+ 0: 20
+ 1: 5
+HLT_xe30_pfopufit_L1XE10:
+ eventCount: 4
+ stepCounts:
+ 0: 20
+ 1: 4
+ stepFeatures:
+ 0: 20
+ 1: 4
+HLT_xe30_pfsum_L1XE10:
+ eventCount: 7
+ stepCounts:
+ 0: 20
+ 1: 7
+ stepFeatures:
+ 0: 20
+ 1: 7
+HLT_xe30_tcpufit_L1XE10:
+ eventCount: 6
+ stepCounts:
+ 0: 6
+ stepFeatures:
+ 0: 6
+HLT_xe30_trkmht_L1XE10:
+ eventCount: 6
+ stepCounts:
+ 0: 20
+ 1: 6
+ stepFeatures:
+ 0: 20
+ 1: 6
+HLT_xe65_cell_L1XE50:
+ eventCount: 0
+HLT_xe65_cell_xe110_tcpufit_L1XE50:
+ eventCount: 0
+HLT_xe80_tcpufit_unconvtrk120_isohpttrack_icummedium_L1XE50:
+ eventCount: 0
+HLT_xe80_tcpufit_unconvtrk120_isohpttrack_imedium_L1XE50:
+ eventCount: 0
+HLT_xe80_tcpufit_unconvtrk80_isohpttrack_imedium_L1XE50:
+ eventCount: 0
+HLT_xe95_trkmht_xe90_tcpufit_xe75_cell_L1XE50:
+ eventCount: 0
diff --git a/Trigger/TrigValidation/TriggerTest/test/test_trig_data_v1Dev_build.py b/Trigger/TrigValidation/TriggerTest/test/test_trig_data_v1Dev_build.py
index 606462a0cc42f12d9b4481801b52f89c5cfd67fd..c54c98f1955e3236d8fbd65dc1f59139594fe93b 100755
--- a/Trigger/TrigValidation/TriggerTest/test/test_trig_data_v1Dev_build.py
+++ b/Trigger/TrigValidation/TriggerTest/test/test_trig_data_v1Dev_build.py
@@ -40,12 +40,13 @@ msgcount.thresholds = {
}
msgcount.required = True # make the test exit code depend on this step
-# Add a step comparing counts in the log against reference
-refcomp = CheckSteps.RegTestStep("CountRefComp")
-refcomp.regex = r'TrigSignatureMoniMT\s*INFO\sHLT_.*|TrigSignatureMoniMT\s*INFO\s-- #[0-9]+ (Events|Features).*'
-refcomp.reference = 'TriggerTest/ref_data_v1Dev_build.ref'
+# Add a step comparing counts against a reference
+chaindump = test.get_step("ChainDump")
+chaindump.args = '--json --yaml ref_data_v1Dev_build.new'
+refcomp = CheckSteps.ChainCompStep("CountRefComp")
+refcomp.input_file = 'ref_data_v1Dev_build.new'
refcomp.required = True # Final exit code depends on this step
-CheckSteps.add_step_after_type(test.check_steps, CheckSteps.LogMergeStep, refcomp)
+CheckSteps.add_step_after_type(test.check_steps, CheckSteps.ChainDumpStep, refcomp)
import sys
sys.exit(test.run())