uGT Zero Suppression final OR of only first 64 algo bits

A typo in the zs_ugt.vhd module is causing the final OR of only the first 64 bits. Luckily, this typo saved us from including the L1_AlwaysTrue in the final OR... A good idea would be to introduce some registers (that we can control via PCIe) to mask some algo bits that we are not interested to.