Broken Pipe since commit c9711e28
Hi,
with the merge of "CI for ITkPixV1" (c9711e28) I keep getting [basil.HL.RegisterHardwareLayer] - ERROR [Errno 32] Broken pipe when running the ITkPixV1 simulation. With a previous commit (57c020d6) I don't have this issue at all. Below is the output when running test_SimDigitalScan.py. The error continues infinitely.
Cheers
Lingxin
2020-06-01 17:28:06,670 [BDAQ53 ] - SUCCESS Found board SIMULATION with Cocotb running firmware version 1.1
2020-06-01 17:28:06,671 [BDAQ53 ] - INFO Board has 1 Aurora receiver channels
2020-06-01 17:28:12,171 [BDAQ53 ] - INFO Aurora receiver(s) running at 1.28Gb/s
2020-06-01 17:28:12,232 [DigitalScan ] - INFO Initializing chips...
2020-06-01 17:28:12,350 [ITkPixV1 - 0x0001] - INFO Initializing communication...
# *** Warning: The analog data file design.txt for XADC instance tb.fpga.i_xadc_ug480.XADC_INST was not found. Use the SIM_MONITOR_FILE parameter to specify the analog data file name or use the default name: design.txt.
#
# ** Warning: (vsim-PLI-3020) $deposit : Second argument is wider than first argument. Truncating upper bits.
# Time: 0 ps Iteration: 0 Process: /tb/#INITIAL#465 File: /home/lmeng/scratch/bdaq53/bdaq53/tests/ITkPixV1/hdl/bdaq53_tb.v Line: 472
# ** Warning: (vsim-PLI-3020) $deposit : Second argument is wider than first argument. Truncating upper bits.
# Time: 0 ps Iteration: 0 Process: /tb/#INITIAL#465 File: /home/lmeng/scratch/bdaq53/bdaq53/tests/ITkPixV1/hdl/bdaq53_tb.v Line: 473
# ** Warning: (vsim-8315) No condition is true in the unique/priority if/case statement.
# Time: 0 ps Iteration: 0 Process: /tb/dut/ChipBottom/DigitalChipBottom/AuroraMultilaneTop/multi_lanes[3]/gearbox20/#ALWAYS#55 File: /home/lmeng/scratch/RD53B/rtl/eoc/aurora/AuroraGearbox66to20.sv Line: 56
# ** Warning: (vsim-8315) No condition is true in the unique/priority if/case statement.
# Time: 0 ps Iteration: 0 Process: /tb/dut/ChipBottom/DigitalChipBottom/AuroraMultilaneTop/multi_lanes[2]/gearbox20/#ALWAYS#55 File: /home/lmeng/scratch/RD53B/rtl/eoc/aurora/AuroraGearbox66to20.sv Line: 56
# ** Warning: (vsim-8315) No condition is true in the unique/priority if/case statement.
# Time: 0 ps Iteration: 0 Process: /tb/dut/ChipBottom/DigitalChipBottom/AuroraMultilaneTop/multi_lanes[1]/gearbox20/#ALWAYS#55 File: /home/lmeng/scratch/RD53B/rtl/eoc/aurora/AuroraGearbox66to20.sv Line: 56
# ** Warning: (vsim-8315) No condition is true in the unique/priority if/case statement.
# Time: 0 ps Iteration: 0 Process: /tb/dut/ChipBottom/DigitalChipBottom/AuroraMultilaneTop/multi_lanes[0]/gearbox20/#ALWAYS#55 File: /home/lmeng/scratch/RD53B/rtl/eoc/aurora/AuroraGearbox66to20.sv Line: 56
# 45.00ns INFO cocotb.tb Test.py:69 in socket_test Waiting for incoming connection on localhost:35242
# 45.00ns INFO cocotb.tb Test.py:71 in socket_test New connection from 127.0.0.1:37172
2020-06-01 17:28:31,378 [ITkPixV1 - 0x0001] - INFO Chip is running at 1.28Gb/s
2020-06-01 17:28:31,378 [ITkPixV1 - 0x0001] - INFO 2 Aurora lanes active
# DRC Error : Reset is unsuccessful at time 187838048. WREN must be low for at least two WRCLK clock cycles after RST deasserted.
# DRC Error : Reset is unsuccessful at time 187838048. WREN must be low for at least two WRCLK clock cycles after RST deasserted.
# ** Note: $finish : /eda/software/Xilinx/Vivado/2018.1/data/verilog/src/unisims/FIFO36E1.v(1088)
# Time: 187838049 ps Iteration: 0 Region: /tb/fpga/i_aurora_rx/i_aurora_rx_core/aurora_frame/aurora_64b66b_2lanes_block_i/aurora_64b66b_2lanes_i/inst/aurora_64b66b_2lanes_wrapper_i/cbcc_gtx0_i/data_fifo/INT_FIFO/genblk1
# 187838.05ns ERROR cocotb.scheduler __init__.py:198 in _sim_event Failing test at simulator request before test run completion: Simulator shutdown prematurely
# 187838.05ns ERROR cocotb.regression regression.py:312 in handle_result Test error has lead to simulator shutting us down
# cocotb.result.SimFailure: Failing test at simulator request before test run completion: Simulator shutdown prematurely
# 187838.05ns ERROR cocotb.regression regression.py:210 in tear_down Failed 1 out of 1 tests (1 skipped)
# 187838.05ns INFO cocotb.regression regression.py:400 in _log_test_summary *******************************************************************************************
# ** TEST PASS/FAIL SIM TIME(NS) REAL TIME(S) RATIO(NS/S) **
# *******************************************************************************************
# ** basil.utils.sim.Test.bringup_test N/A 0.00 0.00 0.00 **
# ** basil.utils.sim.Test.socket_test FAIL 187838.05 89.60 2096.50 **
# *******************************************************************************************
#
# 187838.05ns INFO cocotb.regression regression.py:417 in _log_sim_summary *************************************************************************************
# ** ERRORS : 1 **
# *************************************************************************************
# ** SIM TIME : 187838.05 NS **
# ** REAL TIME : 89.63 S **
# ** SIM / REAL TIME : 2095.73 NS/S **
# *************************************************************************************
#
# 187838.05ns INFO cocotb.regression regression.py:222 in tear_down Shutting down...
# ** Note: $finish : /eda/software/Xilinx/Vivado/2018.1/data/verilog/src/unisims/FIFO36E1.v(1088)
# Time: 187838049 ps Iteration: 0 Region: /tb/fpga/i_aurora_rx/i_aurora_rx_core/aurora_frame/aurora_64b66b_2lanes_block_i/aurora_64b66b_2lanes_i/inst/aurora_64b66b_2lanes_wrapper_i/cbcc_gtx0_i/data_fifo/INT_FIFO/genblk1
# End time: 17:29:32 on Jun 01,2020, Elapsed time: 0:01:51
# Errors: 0, Warnings: 28, Suppressed Warnings: 80
2020-06-01 17:29:32,031 [basil.HL.RegisterHardwareLayer] - ERROR [Errno 104] Connection reset by peer
2020-06-01 17:29:32,031 [basil.HL.RegisterHardwareLayer] - ERROR [Errno 32] Broken pipe