Hardware/FPGA-configuration.md

@@ -92,15 +92,3 @@ The IP address can be changed in different ways:
 
        ![kc705](/uploads/bdcb6cdb7454a2a6c284deb10e2a973c/kc705.png)    
        *Fig. 6: KC705 ip setting (example for .13.12). The arrow points to pin 1.* 
-
-##### Firmware synthesis
-   If you want to synthesize your own firmware, make sure to modify the following line in `/firmware/SiTCP/WRAP_SiTCP_GMII_XC7K_32_K.V`:
-
-   Replace this line 
-   ```verilog
-assign MY_IP_ADDR[31:0] = (~FORCE_DEFAULTn | (EXT_IP_ADDR[31:0]==32'd0) ? DEFAULT_IP_ADDR[31:0] : EXT_IP_ADDR[31:0] );
-   ```
-   with
-   ```verilog
-   assign MY_IP_ADDR[31:0] = EXT_IP_ADDR[31:0];
-   ```
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