Hardware/FPGA-configuration.md

@@ -41,7 +41,7 @@ The flash memory will now be configured. This takes a few seconds.
 
 
 #### IP address configuration
-In order to use multiple readout systems with one PC, every readout needs it's own IP address (Ethernet interface).
+In order to use multiple readout systems with one PC, every readout needs its own IP address (Ethernet interface).
 The IP address can be changed in different ways:
 ##### BDAQ53 and USBPIX(=MIO3/MMC3) hardware (supported in the [ip_addr_selection](https://gitlab.cern.ch/silab/bdaq53/tree/ip_addr_selection) branch).
    - Jumper settings:
@@ -83,3 +83,15 @@ The IP address can be changed in different ways:
 
        ![kc705](/uploads/bdcb6cdb7454a2a6c284deb10e2a973c/kc705.png)
        *Fig. 6: KC705 ip setting (example for .19)* 
+
+##### Firmware synthesis
+   If you want to synthesize your own firmware, make sure to modify the following line in `/firmware/SiTCP/WRAP_SiTCP_GMII_XC7K_32_K.V`:
+
+   Replace this line 
+   ```verilog
+assign MY_IP_ADDR[31:0] = (~FORCE_DEFAULTn | (EXT_IP_ADDR[31:0]==32'd0) ? DEFAULT_IP_ADDR[31:0] : EXT_IP_ADDR[31:0] );
+   ```
+   with
+   ```verilog
+   assign MY_IP_ADDR[31:0] = EXT_IP_ADDR[31:0];
+   ```
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