diff --git a/Trigger/TrigValidation/TrigAnalysisTest/share/ref_RDOtoRDOTrig_v1Dev_build.ref b/Trigger/TrigValidation/TrigAnalysisTest/share/ref_RDOtoRDOTrig_v1Dev_build.ref
index 788dda71f59c8d74d426e70b1d55d6bf4904efd9..a9cfdd3ee6f2ad2f7f6ddef9ee857a36b61e162c 100644
--- a/Trigger/TrigValidation/TrigAnalysisTest/share/ref_RDOtoRDOTrig_v1Dev_build.ref
+++ b/Trigger/TrigValidation/TrigAnalysisTest/share/ref_RDOtoRDOTrig_v1Dev_build.ref
@@ -642,35 +642,11 @@ HLT_2mu6_bBmumu_Lxy0_L1BPH-2M9-2DR15-2MU6:
HLT_2mu6_bBmumux_BpmumuKp_L1BPH-2M9-2DR15-2MU6:
eventCount: 0
HLT_2mu6_bBmumux_BpmumuKp_L1LFV-MU6:
- eventCount: 1
- stepCounts:
- 0: 2
- 1: 1
- 2: 1
- 3: 1
- 4: 1
- stepFeatures:
- 0: 4
- 1: 2
- 2: 2
- 3: 2
- 4: 2
+ eventCount: 0
HLT_2mu6_bBmumux_BsmumuPhi_L1BPH-2M9-2DR15-2MU6:
eventCount: 0
HLT_2mu6_bBmumux_BsmumuPhi_L1LFV-MU6:
- eventCount: 1
- stepCounts:
- 0: 2
- 1: 1
- 2: 1
- 3: 1
- 4: 1
- stepFeatures:
- 0: 4
- 1: 2
- 2: 2
- 3: 2
- 4: 2
+ eventCount: 0
HLT_2mu6_bDimu_L12MU6:
eventCount: 1
stepCounts:
@@ -688,42 +664,15 @@ HLT_2mu6_bDimu_L12MU6:
HLT_2mu6_bDimu_L1BPH-2M9-2DR15-2MU6:
eventCount: 0
HLT_2mu6_bDimu_L1LFV-MU6:
- eventCount: 1
- stepCounts:
- 0: 2
- 1: 1
- 2: 1
- 3: 1
- 4: 1
- stepFeatures:
- 0: 4
- 1: 2
- 2: 2
- 3: 2
- 4: 2
+ eventCount: 0
HLT_2mu6_bJpsimumu_L1BPH-2M9-2DR15-2MU6:
eventCount: 0
HLT_2mu6_bJpsimumu_Lxy0_L1BPH-2M9-2DR15-2MU6:
eventCount: 0
HLT_2mu6_bPhi_L1LFV-MU6:
eventCount: 0
- stepCounts:
- 0: 2
- 1: 1
- 2: 1
- 3: 1
- stepFeatures:
- 0: 4
- 1: 2
- 2: 2
- 3: 2
- 4: 2
HLT_2mu6_bUpsimumu_L1BPH-8M15-0DR22-2MU6:
eventCount: 0
- stepCounts:
- 0: 1
- stepFeatures:
- 0: 2
HLT_2mu6_l2io_L12MU6:
eventCount: 3
stepCounts:
@@ -6114,12 +6063,6 @@ HLT_mu10_lateMu_L1LATE-MU10_XE50:
eventCount: 0
HLT_mu11_mu6_bBmumu_L1LFV-MU11:
eventCount: 0
- stepCounts:
- 0: 2
- stepFeatures:
- 0: 7
- 1: 6
- 2: 4
HLT_mu11_mu6_bBmumu_L1MU11_2MU6:
eventCount: 0
stepCounts:
@@ -6154,12 +6097,6 @@ HLT_mu11_mu6_bBmumux_BdmumuKst_L1MU11_2MU6:
3: 4
HLT_mu11_mu6_bBmumux_BpmumuKp_L1LFV-MU11:
eventCount: 0
- stepCounts:
- 0: 2
- stepFeatures:
- 0: 7
- 1: 6
- 2: 4
HLT_mu11_mu6_bBmumux_BpmumuKp_L1MU11_2MU6:
eventCount: 0
stepCounts:
@@ -6192,12 +6129,6 @@ HLT_mu11_mu6_bBmumux_LbPqKm_L1MU11_2MU6:
3: 4
HLT_mu11_mu6_bDimu2700_L1LFV-MU11:
eventCount: 0
- stepCounts:
- 0: 2
- stepFeatures:
- 0: 7
- 1: 6
- 2: 4
HLT_mu11_mu6_bDimu2700_L1MU11_2MU6:
eventCount: 0
stepCounts:
@@ -6224,12 +6155,6 @@ HLT_mu11_mu6_bDimu2700_Lxy0_L1MU11_2MU6:
4: 4
HLT_mu11_mu6_bDimu_L1LFV-MU11:
eventCount: 0
- stepCounts:
- 0: 2
- stepFeatures:
- 0: 7
- 1: 6
- 2: 4
HLT_mu11_mu6_bDimu_L1MU11_2MU6:
eventCount: 0
stepCounts:
@@ -6256,12 +6181,6 @@ HLT_mu11_mu6_bDimu_Lxy0_L1MU11_2MU6:
4: 4
HLT_mu11_mu6_bJpsimumu_L1LFV-MU11:
eventCount: 0
- stepCounts:
- 0: 2
- stepFeatures:
- 0: 7
- 1: 6
- 2: 4
HLT_mu11_mu6_bJpsimumu_L1MU11_2MU6:
eventCount: 0
stepCounts:
@@ -6288,12 +6207,6 @@ HLT_mu11_mu6_bJpsimumu_Lxy0_L1MU11_2MU6:
4: 4
HLT_mu11_mu6_bPhi_L1LFV-MU11:
eventCount: 0
- stepCounts:
- 0: 2
- stepFeatures:
- 0: 7
- 1: 6
- 2: 4
HLT_mu11_mu6_bPhi_L1MU11_2MU6:
eventCount: 0
stepCounts:
@@ -6308,12 +6221,6 @@ HLT_mu11_mu6_bPhi_L1MU11_2MU6:
4: 4
HLT_mu11_mu6_bTau_L1LFV-MU11:
eventCount: 0
- stepCounts:
- 0: 2
- stepFeatures:
- 0: 7
- 1: 6
- 2: 4
HLT_mu11_mu6_bTau_L1MU11_2MU6:
eventCount: 0
stepCounts:
@@ -6328,12 +6235,6 @@ HLT_mu11_mu6_bTau_L1MU11_2MU6:
4: 4
HLT_mu11_mu6_bUpsimumu_L1LFV-MU11:
eventCount: 0
- stepCounts:
- 0: 2
- stepFeatures:
- 0: 7
- 1: 6
- 2: 4
HLT_mu11_mu6_bUpsimumu_L1MU11_2MU6:
eventCount: 0
stepCounts:
@@ -6557,13 +6458,13 @@ HLT_mu20_2mu4noL1_L1MU20:
1: 6
2: 6
3: 6
- 4: 1
+ 4: 2
stepFeatures:
0: 10
1: 7
2: 7
3: 7
- 4: 3
+ 4: 6
HLT_mu20_L1MU6:
eventCount: 6
stepCounts:
@@ -6670,7 +6571,7 @@ HLT_mu20_ivarmedium_mu4noL1_10invm70_L1MU20:
2: 7
3: 7
4: 4
- 5: 5
+ 5: 6
6: 4
HLT_mu20_ivarmedium_mu8noL1_L1MU20:
eventCount: 1
@@ -6699,17 +6600,13 @@ HLT_mu20_msonly_L1MU20:
0: 10
1: 7
HLT_mu20_msonly_iloosems_mu6noL1_msonly_nscan_L110DR-MU20-MU6:
- eventCount: 1
+ eventCount: 0
stepCounts:
- 0: 3
- 1: 3
- 2: 1
- 3: 1
+ 0: 2
+ 1: 2
stepFeatures:
- 0: 5
- 1: 4
- 2: 1
- 3: 2
+ 0: 4
+ 1: 3
HLT_mu20_msonly_iloosems_mu6noL1_msonly_nscan_L1MU20_J40:
eventCount: 1
stepCounts:
@@ -6721,7 +6618,7 @@ HLT_mu20_msonly_iloosems_mu6noL1_msonly_nscan_L1MU20_J40:
0: 5
1: 4
2: 1
- 3: 2
+ 3: 3
HLT_mu20_msonly_iloosems_mu6noL1_msonly_nscan_L1MU20_XE30:
eventCount: 1
stepCounts:
@@ -6733,7 +6630,7 @@ HLT_mu20_msonly_iloosems_mu6noL1_msonly_nscan_L1MU20_XE30:
0: 6
1: 5
2: 1
- 3: 2
+ 3: 3
HLT_mu20_mu2noL1_invmJPsi_os_L1MU20:
eventCount: 0
stepCounts:
@@ -6747,7 +6644,7 @@ HLT_mu20_mu2noL1_invmJPsi_os_L1MU20:
1: 7
2: 7
3: 7
- 4: 7
+ 4: 8
5: 7
HLT_mu22_2mu4noL1_L1MU20:
eventCount: 0
@@ -6756,13 +6653,13 @@ HLT_mu22_2mu4noL1_L1MU20:
1: 6
2: 6
3: 6
- 4: 1
+ 4: 2
stepFeatures:
0: 10
1: 7
2: 7
3: 7
- 4: 3
+ 4: 6
HLT_mu22_mu10noL1_L1MU20:
eventCount: 2
stepCounts:
@@ -6838,29 +6735,29 @@ HLT_mu24_LRT_d0tight_L1MU20:
1: 1
2: 1
HLT_mu24_LRT_idperf_L1MU20:
- eventCount: 6
+ eventCount: 5
stepCounts:
+ 0: 5
+ 1: 5
+ 2: 5
+ 3: 5
+ stepFeatures:
0: 6
1: 6
2: 6
3: 6
- stepFeatures:
- 0: 7
- 1: 7
- 2: 7
- 3: 7
HLT_mu24_idperf_L1MU20:
- eventCount: 6
+ eventCount: 5
stepCounts:
+ 0: 5
+ 1: 5
+ 2: 5
+ 3: 5
+ stepFeatures:
0: 6
1: 6
2: 6
3: 6
- stepFeatures:
- 0: 7
- 1: 7
- 2: 7
- 3: 7
HLT_mu24_ivarmedium_L1MU20:
eventCount: 4
stepCounts:
@@ -6904,27 +6801,8 @@ HLT_mu24_ivarmedium_mu6_ivarmedium_L1MU20:
4: 3
HLT_mu24_ivarmedium_mu6_ivarmedium_probe_L1MU20:
eventCount: 0
- stepCounts:
- 0: 8
- 1: 6
- 2: 6
- 3: 6
- 4: 4
- 5: 2
- 6: 1
- 7: 1
- 8: 1
stepFeatures:
0: 10
- 1: 7
- 2: 7
- 3: 7
- 4: 4
- 5: 6
- 6: 3
- 7: 2
- 8: 2
- 9: 1
HLT_mu24_ivarmedium_mu6_ivarperf_L1MU20:
eventCount: 1
stepCounts:
@@ -6940,51 +6818,13 @@ HLT_mu24_ivarmedium_mu6_ivarperf_L1MU20:
3: 7
4: 5
HLT_mu24_ivarmedium_mu6_ivarperf_probe_L1MU20:
- eventCount: 1
- stepCounts:
- 0: 8
- 1: 6
- 2: 6
- 3: 6
- 4: 4
- 5: 2
- 6: 1
- 7: 1
- 8: 1
- 9: 1
+ eventCount: 0
stepFeatures:
0: 10
- 1: 7
- 2: 7
- 3: 7
- 4: 4
- 5: 6
- 6: 3
- 7: 2
- 8: 2
- 9: 2
HLT_mu24_ivarmedium_mu6_probe_L1MU20:
- eventCount: 1
- stepCounts:
- 0: 8
- 1: 6
- 2: 6
- 3: 6
- 4: 4
- 5: 2
- 6: 1
- 7: 1
- 8: 1
+ eventCount: 0
stepFeatures:
0: 10
- 1: 7
- 2: 7
- 3: 7
- 4: 4
- 5: 6
- 6: 3
- 7: 2
- 8: 2
HLT_mu24_mu10noL1_L1MU20:
eventCount: 2
stepCounts:
@@ -7014,25 +6854,9 @@ HLT_mu24_mu6_L1MU20:
2: 7
3: 7
HLT_mu24_mu6_probe_L1MU20:
- eventCount: 2
- stepCounts:
- 0: 8
- 1: 6
- 2: 6
- 3: 6
- 4: 3
- 5: 2
- 6: 2
- 7: 2
+ eventCount: 0
stepFeatures:
0: 10
- 1: 7
- 2: 7
- 3: 7
- 4: 9
- 5: 5
- 6: 4
- 7: 4
HLT_mu24_mu8noL1_L1MU20:
eventCount: 2
stepCounts:
@@ -7574,12 +7398,12 @@ HLT_mu4_j70_0eta320_j50_0eta490_j0_DJMASS1000j50_xe50_tcpufit_L1MJJ-500-NFF:
HLT_mu4_l2io_L1MU4:
eventCount: 11
stepCounts:
- 0: 11
+ 0: 12
1: 11
2: 11
3: 11
stepFeatures:
- 0: 15
+ 0: 16
1: 23
2: 19
3: 17
@@ -7764,7 +7588,7 @@ HLT_mu6_mu6noL1_L1MU6:
1: 13
2: 15
3: 15
- 4: 11
+ 4: 12
5: 6
HLT_mu6_noL2Comb_mu4_noL2Comb_bJpsimumu_L1MU6_2MU4:
eventCount: 1
diff --git a/Trigger/TrigValidation/TriggerTest/share/ref_data_v1Dev_build.ref b/Trigger/TrigValidation/TriggerTest/share/ref_data_v1Dev_build.ref
index 2ac32ff04d6b9d5e21167f2a429439b2df966449..b02b9b46b193428480dfac64795c3bf526176f41 100644
--- a/Trigger/TrigValidation/TriggerTest/share/ref_data_v1Dev_build.ref
+++ b/Trigger/TrigValidation/TriggerTest/share/ref_data_v1Dev_build.ref
@@ -251,10 +251,18 @@ HLT_2mu50_msonly_L1MU20:
eventCount: 0
HLT_2mu6_10invm70_L1MU6:
eventCount: 0
+ stepCounts:
+ 0: 1
+ stepFeatures:
+ 0: 2
HLT_2mu6_2j50_0eta490_j0_DJMASS900j50_L1MJJ-500-NFF:
eventCount: 0
HLT_2mu6_L12MU6:
eventCount: 0
+ stepCounts:
+ 0: 1
+ stepFeatures:
+ 0: 2
HLT_2mu6_bBmumu_L1BPH-2M9-2DR15-2MU6:
eventCount: 0
HLT_2mu6_bBmumu_Lxy0_L1BPH-2M9-2DR15-2MU6:
@@ -269,6 +277,10 @@ HLT_2mu6_bBmumux_BsmumuPhi_L1LFV-MU6:
eventCount: 0
HLT_2mu6_bDimu_L12MU6:
eventCount: 0
+ stepCounts:
+ 0: 1
+ stepFeatures:
+ 0: 2
HLT_2mu6_bDimu_L1BPH-2M9-2DR15-2MU6:
eventCount: 0
HLT_2mu6_bDimu_L1LFV-MU6:
@@ -283,14 +295,27 @@ HLT_2mu6_bUpsimumu_L1BPH-8M15-0DR22-2MU6:
eventCount: 0
HLT_2mu6_l2io_L12MU6:
eventCount: 0
+ stepCounts:
+ 0: 1
+ stepFeatures:
+ 0: 2
HLT_2mu6_mu4_bTau_L12MU6_3MU4:
eventCount: 0
HLT_2mu6_mu4_bUpsi_L12MU6_3MU4:
eventCount: 0
HLT_2mu6_muonqual_L12MU6:
eventCount: 0
+ stepCounts:
+ 0: 1
+ stepFeatures:
+ 0: 2
HLT_2mu6_noL2Comb_bJpsimumu_L12MU6:
eventCount: 0
+ stepCounts:
+ 0: 1
+ stepFeatures:
+ 0: 2
+ 1: 2
HLT_3j200_L1J100:
eventCount: 0
HLT_3j200_ftf_L1J100:
@@ -994,11 +1019,11 @@ HLT_eb_low_L1RD2_FILLED:
stepFeatures:
0: 9
HLT_eb_medium_L1RD2_FILLED:
- eventCount: 7
+ eventCount: 6
stepCounts:
- 0: 7
+ 0: 6
stepFeatures:
- 0: 7
+ 0: 6
HLT_g0_hiptrt_L1EM22VHI:
eventCount: 0
stepCounts:
@@ -2467,48 +2492,108 @@ HLT_mu11_mu6_bBmumu_L1LFV-MU11:
eventCount: 0
HLT_mu11_mu6_bBmumu_L1MU11_2MU6:
eventCount: 0
+ stepCounts:
+ 0: 1
+ stepFeatures:
+ 0: 3
HLT_mu11_mu6_bBmumux_BcmumuPi_L1MU11_2MU6:
eventCount: 0
+ stepCounts:
+ 0: 1
+ stepFeatures:
+ 0: 3
HLT_mu11_mu6_bBmumux_BdmumuKst_L1MU11_2MU6:
eventCount: 0
+ stepCounts:
+ 0: 1
+ stepFeatures:
+ 0: 3
HLT_mu11_mu6_bBmumux_BpmumuKp_L1LFV-MU11:
eventCount: 0
HLT_mu11_mu6_bBmumux_BpmumuKp_L1MU11_2MU6:
eventCount: 0
+ stepCounts:
+ 0: 1
+ stepFeatures:
+ 0: 3
HLT_mu11_mu6_bBmumux_BsmumuPhi_L1MU11_2MU6:
eventCount: 0
+ stepCounts:
+ 0: 1
+ stepFeatures:
+ 0: 3
HLT_mu11_mu6_bBmumux_LbPqKm_L1MU11_2MU6:
eventCount: 0
+ stepCounts:
+ 0: 1
+ stepFeatures:
+ 0: 3
HLT_mu11_mu6_bDimu2700_L1LFV-MU11:
eventCount: 0
HLT_mu11_mu6_bDimu2700_L1MU11_2MU6:
eventCount: 0
+ stepCounts:
+ 0: 1
+ stepFeatures:
+ 0: 3
HLT_mu11_mu6_bDimu2700_Lxy0_L1MU11_2MU6:
eventCount: 0
+ stepCounts:
+ 0: 1
+ stepFeatures:
+ 0: 3
HLT_mu11_mu6_bDimu_L1LFV-MU11:
eventCount: 0
HLT_mu11_mu6_bDimu_L1MU11_2MU6:
eventCount: 0
+ stepCounts:
+ 0: 1
+ stepFeatures:
+ 0: 3
HLT_mu11_mu6_bDimu_Lxy0_L1MU11_2MU6:
eventCount: 0
+ stepCounts:
+ 0: 1
+ stepFeatures:
+ 0: 3
HLT_mu11_mu6_bJpsimumu_L1LFV-MU11:
eventCount: 0
HLT_mu11_mu6_bJpsimumu_L1MU11_2MU6:
eventCount: 0
+ stepCounts:
+ 0: 1
+ stepFeatures:
+ 0: 3
HLT_mu11_mu6_bJpsimumu_Lxy0_L1MU11_2MU6:
eventCount: 0
+ stepCounts:
+ 0: 1
+ stepFeatures:
+ 0: 3
HLT_mu11_mu6_bPhi_L1LFV-MU11:
eventCount: 0
HLT_mu11_mu6_bPhi_L1MU11_2MU6:
eventCount: 0
+ stepCounts:
+ 0: 1
+ stepFeatures:
+ 0: 3
HLT_mu11_mu6_bTau_L1LFV-MU11:
eventCount: 0
HLT_mu11_mu6_bTau_L1MU11_2MU6:
eventCount: 0
+ stepCounts:
+ 0: 1
+ stepFeatures:
+ 0: 3
HLT_mu11_mu6_bUpsimumu_L1LFV-MU11:
eventCount: 0
HLT_mu11_mu6_bUpsimumu_L1MU11_2MU6:
eventCount: 0
+ stepCounts:
+ 0: 1
+ stepFeatures:
+ 0: 3
HLT_mu14_L1MU10:
eventCount: 0
stepCounts:
@@ -2542,7 +2627,7 @@ HLT_mu20_L1MU6:
stepCounts:
0: 1
stepFeatures:
- 0: 1
+ 0: 2
HLT_mu20_L1MU6_AFP_A_AND_C:
eventCount: 0
HLT_mu20_L1MU6_AFP_A_OR_C:
@@ -2579,10 +2664,6 @@ HLT_mu20_msonly_L1MU20:
0: 1
HLT_mu20_msonly_iloosems_mu6noL1_msonly_nscan_L110DR-MU20-MU6:
eventCount: 0
- stepCounts:
- 0: 1
- stepFeatures:
- 0: 1
HLT_mu20_msonly_iloosems_mu6noL1_msonly_nscan_L1MU20_J40:
eventCount: 0
HLT_mu20_msonly_iloosems_mu6noL1_msonly_nscan_L1MU20_XE30:
@@ -2671,8 +2752,6 @@ HLT_mu24_ivarmedium_mu6_ivarmedium_L1MU20:
0: 3
HLT_mu24_ivarmedium_mu6_ivarmedium_probe_L1MU20:
eventCount: 0
- stepCounts:
- 0: 1
stepFeatures:
0: 1
HLT_mu24_ivarmedium_mu6_ivarperf_L1MU20:
@@ -2683,14 +2762,10 @@ HLT_mu24_ivarmedium_mu6_ivarperf_L1MU20:
0: 3
HLT_mu24_ivarmedium_mu6_ivarperf_probe_L1MU20:
eventCount: 0
- stepCounts:
- 0: 1
stepFeatures:
0: 1
HLT_mu24_ivarmedium_mu6_probe_L1MU20:
eventCount: 0
- stepCounts:
- 0: 1
stepFeatures:
0: 1
HLT_mu24_mu10noL1_L1MU20:
@@ -2707,8 +2782,6 @@ HLT_mu24_mu6_L1MU20:
0: 3
HLT_mu24_mu6_probe_L1MU20:
eventCount: 0
- stepCounts:
- 0: 1
stepFeatures:
0: 1
HLT_mu24_mu8noL1_L1MU20:
@@ -2878,29 +2951,29 @@ HLT_mu6_L1MU6:
stepCounts:
0: 1
stepFeatures:
- 0: 1
+ 0: 2
HLT_mu6_LRT_idperf_L1MU6:
eventCount: 0
stepCounts:
0: 1
1: 1
stepFeatures:
- 0: 1
- 1: 1
+ 0: 2
+ 1: 2
HLT_mu6_idperf_L1MU6:
eventCount: 0
stepCounts:
0: 1
1: 1
stepFeatures:
- 0: 1
- 1: 1
+ 0: 2
+ 1: 2
HLT_mu6_ivarmedium_L1MU6:
eventCount: 0
stepCounts:
0: 1
stepFeatures:
- 0: 1
+ 0: 2
HLT_mu6_j45_nojcalib_L1J20:
eventCount: 0
HLT_mu6_msonly_L1MU6:
@@ -2908,7 +2981,7 @@ HLT_mu6_msonly_L1MU6:
stepCounts:
0: 1
stepFeatures:
- 0: 1
+ 0: 2
HLT_mu6_mu4_L12MU4:
eventCount: 0
stepCounts:
@@ -2930,7 +3003,7 @@ HLT_mu6_mu4_bDimu_L1MU6_2MU4:
stepCounts:
0: 1
stepFeatures:
- 0: 3
+ 0: 4
HLT_mu6_mu4_bJpsimumu_L1BPH-2M9-0DR15-MU6MU4:
eventCount: 0
HLT_mu6_mu4_bJpsimumu_Lxy0_L1BPH-2M9-0DR15-MU6MU4:
@@ -2942,14 +3015,14 @@ HLT_mu6_mu6noL1_L1MU6:
stepCounts:
0: 1
stepFeatures:
- 0: 1
+ 0: 2
HLT_mu6_noL2Comb_mu4_noL2Comb_bJpsimumu_L1MU6_2MU4:
eventCount: 0
stepCounts:
0: 1
stepFeatures:
- 0: 3
- 1: 3
+ 0: 4
+ 1: 4
HLT_mu6_xe30_mht_L1XE30:
eventCount: 0
HLT_mu80_L1MU20:
@@ -2969,7 +3042,7 @@ HLT_mu8_L1MU6:
stepCounts:
0: 1
stepFeatures:
- 0: 1
+ 0: 2
HLT_noalg_AlfaPEB_L1ALFA_ANY:
eventCount: 0
HLT_noalg_CIS_TilePEB_L1CALREQ1:
diff --git a/Trigger/TriggerCommon/TriggerJobOpts/share/runHLT_standalone.py b/Trigger/TriggerCommon/TriggerJobOpts/share/runHLT_standalone.py
index f882e9b70433592854f5f9a245fe060a9521ec07..ab47b954770101e6708917a8be80dce1fc2c56ec 100644
--- a/Trigger/TriggerCommon/TriggerJobOpts/share/runHLT_standalone.py
+++ b/Trigger/TriggerCommon/TriggerJobOpts/share/runHLT_standalone.py
@@ -41,7 +41,6 @@ class opt:
endJobAfterGenerate = False # Finish job after menu generation
strictDependencies = False # Sets SGInputLoader.FailIfNoProxy=True and AlgScheduler.DataLoaderAlg=""
forceEnableAllChains = False # if True, all HLT chains will run even if the L1 item is false
-# enableL1Phase1 = False # Enable Run-3 LVL1 simulation and/or decoding
enableL1MuonPhase1 = False # Enable Run-3 LVL1 muon simulation and/or decoding
enableL1CaloPhase1 = False # Enable Run-3 LVL1 calo simulation and/or decoding
enableL1CaloLegacy = True # Enable Run-2 L1Calo simulation and/or decoding (possible even if enablePhase1 is True)
@@ -210,9 +209,13 @@ if 'enableL1CaloPhase1' not in globals():
log.info('Setting default enableL1CaloPhase1=%s because doL1Sim=%s and ConfigFlags.Input.Format=%s',
opt.enableL1CaloPhase1, opt.doL1Sim, ConfigFlags.Input.Format)
+# Set default enableL1MuonPhase1 option to True if running L1Sim (ATR-23973)
+if 'enableL1MuonPhase1' not in globals():
+ opt.enableL1MuonPhase1 = opt.doL1Sim
+ log.info('Setting default enableL1MuonPhase1=%s because doL1Sim=%s', opt.enableL1MuonPhase1, opt.doL1Sim)
+
# Translate opts to flags for LVL1
ConfigFlags.Trigger.doLVL1 = opt.doL1Sim
-#ConfigFlags.Trigger.enableL1Phase1 = opt.enableL1Phase1
ConfigFlags.Trigger.enableL1MuonPhase1 = opt.enableL1MuonPhase1
ConfigFlags.Trigger.enableL1CaloPhase1 = opt.enableL1CaloPhase1
ConfigFlags.Trigger.enableL1CaloLegacy = opt.enableL1CaloLegacy