Verified Commit 8d75c659 authored by Tadej Novak's avatar Tadej Novak
Browse files

Explicitly load calo overlay inputs

parent 6b14ab7e
Pipeline #3987703 passed with stage
in 0 seconds
......@@ -124,14 +124,35 @@ def LArPileUpToolCfg(flags, name="LArPileUpTool", **kwargs):
acc.merge(InputOverwriteCfg("LArHitContainer","LArHitHEC","LArHitFloatContainer","LArHitHEC"))
acc.merge(InputOverwriteCfg("LArHitContainer","LArHitFCAL","LArHitFloatContainer","LArHitFCAL"))
kwargs.setdefault("LArHitContainers", [])
if flags.Common.ProductionStep == ProductionStep.Overlay:
from SGComps.SGInputLoaderConfig import SGInputLoaderCfg
acc.merge(SGInputLoaderCfg(flags, [
"LArHitFloatContainer#LArHitEMB",
"LArHitFloatContainer#LArHitEMEC",
"LArHitFloatContainer#LArHitFCAL",
"LArHitFloatContainer#LArHitHEC",
]))
else:
kwargs.setdefault("LArHitFloatContainers", [])
if flags.Common.ProductionStep == ProductionStep.Overlay:
from SGComps.SGInputLoaderConfig import SGInputLoaderCfg
acc.merge(SGInputLoaderCfg(flags, [
"LArHitContainer#LArHitEMB",
"LArHitContainer#LArHitEMEC",
"LArHitContainer#LArHitFCAL",
"LArHitContainer#LArHitHEC",
]))
if flags.Common.ProductionStep == ProductionStep.Overlay:
kwargs.setdefault("OnlyUseContainerName", False)
if flags.Overlay.DataOverlay:
kwargs.setdefault("InputDigitContainer", flags.Overlay.BkgPrefix + "FREE")
kwargs.setdefault("InputDigitContainer", f"{flags.Overlay.BkgPrefix}FREE")
else:
kwargs.setdefault("InputDigitContainer", flags.Overlay.BkgPrefix + "LArDigitContainer_MC")
kwargs.setdefault("InputDigitContainer", f"{flags.Overlay.BkgPrefix}LArDigitContainer_MC")
from SGComps.SGInputLoaderConfig import SGInputLoaderCfg
acc.merge(SGInputLoaderCfg(flags, [f'LArDigitContainer#{kwargs["InputDigitContainer"]}']))
else:
kwargs.setdefault("OnlyUseContainerName", flags.Digitization.PileUp)
LArPileUpTool = CompFactory.LArPileUpTool
......@@ -319,9 +340,12 @@ def LArSCL1MakerCfg(flags, **kwargs):
kwargs.setdefault("RndmSvc",
acc.getPrimaryAndMerge(AthRNGSvcCfg(flags)).name)
if flags.Common.ProductionStep == ProductionStep.PileUpPresampling:
kwargs.setdefault("SCL1ContainerName",flags.Overlay.BkgPrefix + "LArDigitSCL2") # Output - why L2??
kwargs.setdefault("SCL1ContainerName", f"{flags.Overlay.BkgPrefix}LArDigitSCL2") # Output - why L2??
if flags.Common.ProductionStep == ProductionStep.Overlay:
kwargs.setdefault("BkgDigitKey", flags.Overlay.BkgPrefix + "LArDigitSCL2")
kwargs.setdefault("BkgDigitKey", f"{flags.Overlay.BkgPrefix}LArDigitSCL2")
from SGComps.SGInputLoaderConfig import SGInputLoaderCfg
acc.merge(SGInputLoaderCfg(flags, [f'LArDigitContainer#{kwargs["BkgDigitKey"]}']))
kwargs.setdefault("SCL1ContainerName","LArDigitSCL2") # Output - why L2??
acc.addEventAlgo(CompFactory.LArSCL1Maker(**kwargs))
return acc
......
......@@ -63,16 +63,19 @@ def TileDigitsMakerCfg(flags, **kwargs):
if flags.Overlay.DataOverlay:
from ByteStreamCnvSvc.ByteStreamConfig import ByteStreamReadCfg
acc.merge(ByteStreamReadCfg(flags, type_names=[
'TileDigitsContainer/' + flags.Overlay.BkgPrefix + 'TileDigitsCnt',
'TileRawChannelContainer/' + flags.Overlay.BkgPrefix + 'TileRawChannelCnt']
f'TileDigitsContainer/{flags.Overlay.BkgPrefix}TileDigitsCnt',
f'TileRawChannelContainer/{flags.Overlay.BkgPrefix}TileRawChannelCnt']
))
from TileRecUtils.TileDQstatusConfig import TileDQstatusAlgCfg
acc.merge(TileDQstatusAlgCfg(flags))
kwargs['InputTileDigitContainer'] = flags.Overlay.BkgPrefix + 'TileDigitsCnt'
kwargs['InputTileDigitContainer'] = f'{flags.Overlay.BkgPrefix}TileDigitsCnt'
kwargs['TileDQstatus'] = 'TileDQstatus'
from SGComps.SGInputLoaderConfig import SGInputLoaderCfg
acc.merge(SGInputLoaderCfg(flags, [f'TileDigitsContainer#{kwargs["InputTileDigitContainer"]}']))
if tileNoise or tileCoherNoise or kwargs['RndmEvtOverlay']:
if 'RndmSvc' not in kwargs:
from RngComps.RandomServices import AthRNGSvcCfg
......
......@@ -61,6 +61,10 @@ def TileHitVecToCntToolCfg(flags, **kwargs):
kwargs.setdefault('TileHitVectors', ['TileHitVec'])
kwargs.setdefault('TileHitContainer', 'TileHitCnt')
if flags.Common.ProductionStep == ProductionStep.Overlay:
from SGComps.SGInputLoaderConfig import SGInputLoaderCfg
acc.merge(SGInputLoaderCfg(flags, [f'TileHitVector#{vec}' for vec in kwargs['TileHitVectors']]))
kwargs.setdefault('DoHSTruthReconstruction', flags.Digitization.DoDigiTruth)
if kwargs['DoHSTruthReconstruction']:
kwargs.setdefault('TileHitContainer_DigiHSTruth', 'TileHitCnt_DigiHSTruth')
......
"""Define functions for TTL1 Overlay with ComponentAccumulator
Copyright (C) 2002-2021 CERN for the benefit of the ATLAS collaboration
Copyright (C) 2002-2022 CERN for the benefit of the ATLAS collaboration
"""
from AthenaConfiguration.ComponentAccumulator import ComponentAccumulator
......@@ -15,20 +15,21 @@ def LArTTL1OverlayCfg(flags, name="LArTTL1Overlay", **kwargs):
acc = ComponentAccumulator()
acc.merge(LArOverlayTriggerDigitizationBasicCfg(flags))
kwargs.setdefault("BkgEmTTL1Key",
flags.Overlay.BkgPrefix + "LArTTL1EM")
kwargs.setdefault("SignalEmTTL1Key",
flags.Overlay.SigPrefix + "LArTTL1EM")
kwargs.setdefault("BkgEmTTL1Key", f"{flags.Overlay.BkgPrefix}LArTTL1EM")
kwargs.setdefault("SignalEmTTL1Key", f"{flags.Overlay.SigPrefix}LArTTL1EM")
kwargs.setdefault("OutputEmTTL1Key", "LArTTL1EM")
kwargs.setdefault("BkgHadTTL1Key",
flags.Overlay.BkgPrefix + "LArTTL1HAD")
kwargs.setdefault("SignalHadTTL1Key",
flags.Overlay.SigPrefix + "LArTTL1HAD")
kwargs.setdefault("BkgHadTTL1Key", f"{flags.Overlay.BkgPrefix}LArTTL1HAD")
kwargs.setdefault("SignalHadTTL1Key", f"{flags.Overlay.SigPrefix}LArTTL1HAD")
kwargs.setdefault("OutputHadTTL1Key", "LArTTL1HAD")
LArTTL1Overlay = CompFactory.LVL1.LArTTL1Overlay
acc.addEventAlgo(LArTTL1Overlay(name, **kwargs))
from SGComps.SGInputLoaderConfig import SGInputLoaderCfg
acc.merge(SGInputLoaderCfg(flags, [
f'LArTTL1Container#{kwargs["BkgEmTTL1Key"]}',
f'LArTTL1Container#{kwargs["BkgHadTTL1Key"]}',
]))
acc.addEventAlgo(CompFactory.LVL1.LArTTL1Overlay(name, **kwargs))
if flags.Output.doWriteRDO:
from OutputStreamAthenaPool.OutputStreamConfig import OutputStreamCfg
......@@ -40,8 +41,8 @@ def LArTTL1OverlayCfg(flags, name="LArTTL1Overlay", **kwargs):
if flags.Output.doWriteRDO_SGNL:
from OutputStreamAthenaPool.OutputStreamConfig import OutputStreamCfg
acc.merge(OutputStreamCfg(flags, streamName='RDO_SGNL', ItemList=[
'LArTTL1Container#' + flags.Overlay.SigPrefix + 'LArTTL1EM',
'LArTTL1Container#' + flags.Overlay.SigPrefix + 'LArTTL1HAD',
f'LArTTL1Container#{flags.Overlay.SigPrefix}LArTTL1EM',
f'LArTTL1Container#{flags.Overlay.SigPrefix}LArTTL1HAD',
]))
return acc
......@@ -52,25 +53,25 @@ def TileTTL1OverlayCfg(flags, name="TileTTL1Overlay", **kwargs):
acc = ComponentAccumulator()
acc.merge(TileHitToTTL1Cfg(flags))
kwargs.setdefault("BkgTileTTL1Key",
flags.Overlay.BkgPrefix + "TileTTL1Cnt")
kwargs.setdefault("SignalTileTTL1Key",
flags.Overlay.SigPrefix + "TileTTL1Cnt")
kwargs.setdefault("BkgTileTTL1Key", f"{flags.Overlay.BkgPrefix}TileTTL1Cnt")
kwargs.setdefault("SignalTileTTL1Key", f"{flags.Overlay.SigPrefix}TileTTL1Cnt")
kwargs.setdefault("OutputTileTTL1Key", "TileTTL1Cnt")
inputs = [f'TileTTL1Container#{kwargs["BkgTileTTL1Key"]}']
if flags.Detector.EnableMBTS:
kwargs.setdefault("BkgTileMBTSTTL1Key",
flags.Overlay.BkgPrefix + "TileTTL1MBTS")
kwargs.setdefault("SignalTileMBTSTTL1Key",
flags.Overlay.SigPrefix + "TileTTL1MBTS")
kwargs.setdefault("BkgTileMBTSTTL1Key", f"{flags.Overlay.BkgPrefix}TileTTL1MBTS")
kwargs.setdefault("SignalTileMBTSTTL1Key", f"{flags.Overlay.SigPrefix}TileTTL1MBTS")
kwargs.setdefault("OutputTileMBTSTTL1Key", "TileTTL1MBTS")
inputs.append(f'TileTTL1Container#{kwargs["BkgTileMBTSTTL1Key"]}')
else:
kwargs.setdefault("BkgTileMBTSTTL1Key", "")
kwargs.setdefault("SignalTileMBTSTTL1Key", "")
kwargs.setdefault("OutputTileMBTSTTL1Key", "")
TileTTL1Overlay = CompFactory.LVL1.TileTTL1Overlay
acc.addEventAlgo(TileTTL1Overlay(name, **kwargs))
from SGComps.SGInputLoaderConfig import SGInputLoaderCfg
acc.merge(SGInputLoaderCfg(flags, inputs))
acc.addEventAlgo(CompFactory.LVL1.TileTTL1Overlay(name, **kwargs))
if flags.Output.doWriteRDO:
from OutputStreamAthenaPool.OutputStreamConfig import OutputStreamCfg
......@@ -82,8 +83,8 @@ def TileTTL1OverlayCfg(flags, name="TileTTL1Overlay", **kwargs):
if flags.Output.doWriteRDO_SGNL:
from OutputStreamAthenaPool.OutputStreamConfig import OutputStreamCfg
acc.merge(OutputStreamCfg(flags, streamName='RDO_SGNL', ItemList=[
'TileTTL1Container#' + flags.Overlay.SigPrefix + 'TileTTL1Cnt',
'TileTTL1Container#' + flags.Overlay.SigPrefix + 'TileTTL1MBTS',
f'TileTTL1Container#{flags.Overlay.SigPrefix}TileTTL1Cnt',
f'TileTTL1Container#{flags.Overlay.SigPrefix}TileTTL1MBTS',
]))
return acc
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