Yosys design caching?
There might be an opportunity to cache the yosys design, in order to not re-synthesize the RTL files every time verification is re-run without any changes to the files. The modification times (or md5sums?) of all inputs files could be somehow combined and stored together with the write_ilang output, and cocotb-fault-injection can decide whether to just read_ilang or read_verilog/hier/proc the files.