Commit 69551862 authored by Mauro Dinardo's avatar Mauro Dinardo
Browse files

Fixed bug with AURORA at 640 Mbit/s

parent cd8cf4be
......@@ -19,8 +19,8 @@ void ThrEqualizationHistograms::book(TFile* theOutputFile, const DetectorContain
// #######################
// # Retrieve parameters #
// #######################
nEvents = this->findValueInSettings(settingsMap, "nEvents");
size_t TDACsize = RD53Shared::setBits(RD53Constants::NBIT_TDAC) + 1;
nEvents = this->findValueInSettings(settingsMap, "nEvents");
size_t TDACsize = RD53Shared::setBits(RD53Constants::NBIT_TDAC) + 1;
const size_t colStart = this->findValueInSettings(settingsMap, "COLstart");
const size_t colStop = this->findValueInSettings(settingsMap, "COLstop");
......
......@@ -29,16 +29,19 @@
// #########################
namespace RD53Constants
{
const uint8_t BROADCAST_CHIPID = 0x8; // Broadcast chip ID used to send the command to multiple chips
const uint8_t NREGIONS_LONGCMD = 6; // Number of regions to program with long write commands
const uint8_t FIELDS_SHORTCMD = 8; // Number of fields for the short write command
const uint8_t FIELDS_LONGCMD = 24; // Number of fields for the long write command
const uint8_t NBIT_TDAC = 4; // Number of TDAC bits
const uint8_t NBIT_MAXREG = 16; // Maximum number of bits for a chip register
const uint8_t NPIX_REGION = 4; // Number of pixels in a region (1x4)
const uint8_t NROW_CORE = 8; // Number of rows in a core
const uint8_t NBIT_ADDR = 9; // Number of address bits
const uint8_t NSYNC_WORS = 32; // Number of Sync words for synchronization
const uint8_t BROADCAST_CHIPID = 0x8; // Broadcast chip ID used to send the command to multiple chips
const uint8_t NREGIONS_LONGCMD = 6; // Number of regions to program with long write commands
const uint8_t FIELDS_SHORTCMD = 8; // Number of fields for the short write command
const uint8_t FIELDS_LONGCMD = 24; // Number of fields for the long write command
const uint8_t NBIT_TDAC = 4; // Number of TDAC bits
const uint8_t NBIT_MAXREG = 16; // Maximum number of bits for a chip register
const uint8_t NPIX_REGION = 4; // Number of pixels in a region (1x4)
const uint8_t NROW_CORE = 8; // Number of rows in a core
const uint8_t NBIT_ADDR = 9; // Number of address bits
const uint8_t NSYNC_WORS = 32; // Number of Sync words for synchronization
const uint8_t CDRCONFIG_ADDR = 0x40; // Address of CDR_CONFIG register
const uint16_t CDRCONFIG_1Gbit = 1048; // Value for 1.28 Gbit/s
const uint16_t CDRCONFIG_640Mbit = 1049; // Value for 640 Mbit/s
} // namespace RD53Constants
// ############
......
......@@ -152,7 +152,11 @@ void RD53FWInterface::ConfigureBoard(const BeBoard* pBoard)
// ##############################
// # AURORA lock on data stream #
// ##############################
while(RD53FWInterface::CheckChipCommunication() == false) RD53FWInterface::InitHybridByHybrid(pBoard);
if(RD53FWInterface::CheckChipCommunication() == false)
{
RD53FWInterface::InitHybridByHybrid(pBoard);
RD53FWInterface::CheckChipCommunication();
}
}
void RD53FWInterface::ConfigureFromXML(const BeBoard* pBoard)
......@@ -321,8 +325,8 @@ bool RD53FWInterface::CheckChipCommunication()
// ###############################
// # Check RD53 AURORA registers #
// ###############################
unsigned int speed_flag = ReadReg("user.stat_regs.aurora_rx.speed");
LOG(INFO) << BOLDBLUE << "\t--> Aurora speed: " << BOLDYELLOW << (speed_flag == 0 ? "1.28 Gbps" : "640 Mbps") << RESET;
auroraSpeed = ReadReg("user.stat_regs.aurora_rx.speed");
LOG(INFO) << BOLDBLUE << "\t--> Aurora speed: " << BOLDYELLOW << (auroraSpeed == 0 ? "1.28 Gbps" : "640 Mbps") << RESET;
// ########################################
// # Check communication with the chip(s) #
......@@ -356,9 +360,9 @@ void RD53FWInterface::InitHybridByHybrid(const BeBoard* pBoard)
for(const auto cOpticalGroup: *pBoard)
for(const auto cHybrid: *cOpticalGroup)
{
// #############################
// # Check if all lanes are up #
// #############################
// #################################
// # Check if all lanes are active #
// #################################
const uint32_t hybrid_id = cHybrid->getId();
const uint32_t chips_en_to_check = RD53FWInterface::GetHybridEnabledChips(cHybrid);
const uint32_t channel_up = ReadReg("user.stat_regs.aurora_rx_channel_up");
......@@ -384,12 +388,20 @@ void RD53FWInterface::InitHybridByHybrid(const BeBoard* pBoard)
for(unsigned int i = 0; i < MAXATTEMPTS; i++)
{
// ###########################
// # Set proper AURORA speed #
// ###########################
if(auroraSpeed == 0)
RD53FWInterface::WriteChipCommand(RD53Cmd::WrReg(RD53Constants::BROADCAST_CHIPID, RD53Constants::CDRCONFIG_ADDR, RD53Constants::CDRCONFIG_1Gbit).getFrames(), -1);
else
RD53FWInterface::WriteChipCommand(RD53Cmd::WrReg(RD53Constants::BROADCAST_CHIPID, RD53Constants::CDRCONFIG_ADDR, RD53Constants::CDRCONFIG_640Mbit).getFrames(), -1);
RD53FWInterface::WriteChipCommand(initSequence, hybrid_id);
usleep(DEEPSLEEP);
// #############################
// # Check if all lanes are up #
// #############################
// #################################
// # Check if all lanes are active #
// #################################
lanes_up = false;
uint32_t channel_up = ReadReg("user.stat_regs.aurora_rx_channel_up");
......@@ -408,7 +420,7 @@ void RD53FWInterface::InitHybridByHybrid(const BeBoard* pBoard)
if(lanes_up == true) break;
}
if(lanes_up == false) LOG(ERROR) << BOLDRED << "Not all data lanes are up for hybrid: " << BOLDYELLOW << hybrid_id << RESET;
if(lanes_up == false) LOG(ERROR) << BOLDRED << "Not all data lanes are active for hybrid: " << BOLDYELLOW << hybrid_id << RESET;
}
}
......
......@@ -296,6 +296,7 @@ class RD53FWInterface : public BeBoardFWInterface
D19cFpgaConfig* fpgaConfig;
size_t ddr3Offset;
bool singleChip;
unsigned int auroraSpeed;
uint16_t enabledHybrids;
};
......
......@@ -10,11 +10,11 @@
#ifndef RD53Shared_H
#define RD53Shared_H
#include <cmath>
#include <iomanip>
#include <iostream>
#include <sstream>
#include <cmath>
#include <thread>
#include <iostream>
namespace RD53Shared
{
......
......@@ -151,13 +151,15 @@
<Settings>
<!--
=== Calibration parameters ===
INJtype = 0: no injection; INJtype = 1: analog; INJtype = 2: digital
DoFast = 0: run on all pixels in the selected region; DoFast = 1: run on a subset
DisplayHisto = 0: don't display; DisplayHisto = 1: display
UpdateChipCfg = 0: don't update; UpdateChipCfg = 1: update
INJtype = 0: no injection; INJtype = 1: analog; INJtype = 2: digital
DoFast = 0: run on all pixels in the selected region; DoFast = 1: run on a subset
DisplayHisto = 0: don't display; DisplayHisto = 1: display
UpdateChipCfg = 0: don't update; UpdateChipCfg = 1: update
TargetCharge: average charge (electrons) corresponding to ToT point = max value - 1
TargetOcc: average fraction of acceptable hits per pixel
UnstuckPixels = 0: do not try to unstuck pixels; UnstuckPixels = 1: set TDAC to 0 to unstuck pixels
ThrEquResetTDAC = 0: do not reset TDAC; ThrEquResetTDAC = 1: reset TDAC
-->
<Setting name="nEvents"> 100 </Setting>
<Setting name="nEvtsBurst"> 100 </Setting>
......@@ -201,7 +203,7 @@
<!-- === Expert settings ===
SaveBinaryData = 0: do not save raw data in binary format; SaveBinaryData = 1: save raw data in binary format
nHITxCol: number of simultaneously injected pixels per column (it must be a divider of chip rows)
nClkDelays: controls the delay between two consecutive injections in terms of 100ns period
nClkDelays: controls the delay between two consecutive injections in terms of 100ns period (up to 4095)
-->
<Setting name="SaveBinaryData"> 0 </Setting>
<Setting name="nHITxCol"> 1 </Setting>
......
......@@ -614,7 +614,7 @@ int main(int argc, char** argv)
mySysCntr.fReadoutChipInterface->WriteChipReg(static_cast<RD53*>(cChip), "SER_SEL_OUT", 1, true);
}
}
else if(program == false)
else if((program == false) && (whichCalib != ""))
{
LOG(ERROR) << BOLDRED << "Option not recognized: " << BOLDYELLOW << whichCalib << RESET;
exit(EXIT_FAILURE);
......
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