Commit da0d914c authored by Kevin Connor Nash's avatar Kevin Connor Nash
Browse files

Resolve trivial conflicts

# Conflicts:
#   HWInterface/MPAInterface.cc
#   Utils/CommonVisitors.h
#   src/MPA_sync_test.cc
#   tools/LatencyScan.cc
parents 93428520 fc3c2201
......@@ -36,7 +36,7 @@ build:
run_on_IT:
stage: run
dependencies:
- build
- build
before_script:
- printf $USER_PASS | base64 -d | kinit $USER_NAME
- xrdcp -r root://eosuser.cern.ch//eos/user/c/cmstkph2/ci_repo/ci_tools .
......@@ -53,7 +53,7 @@ run_on_IT:
- cp ci_tools/Results/Run000001_ThrEqualization.root .
- cp ci_tools/Results/Run000002_SCurve.root .
artifacts:
paths:
paths:
- Run000000_PixelAlive.root
- Run000001_ThrEqualization.root
- Run000002_SCurve.root
......@@ -65,9 +65,9 @@ check_run_on_IT:
stage: check
needs: [run_on_IT]
script:
- python ci_tools/plot_canvas.py Run000000_PixelAlive.root "Detector/Board_0/OpticalGroup_0/Hybrid_0/Chip_0/D_B(0)_O(0)_M(0)_PixelAlive_Chip(0)" -o plots
- python ci_tools/plot_canvas.py Run000001_ThrEqualization.root "Detector/Board_0/OpticalGroup_0/Hybrid_0/Chip_0/D_B(0)_O(0)_M(0)_ThrEqualization_Chip(0)" -o plots
- python ci_tools/plot_canvas.py Run000002_SCurve.root "Detector/Board_0/OpticalGroup_0/Hybrid_0/Chip_0/D_B(0)_O(0)_M(0)_SCurves_Chip(0)" -o plots
- python ci_tools/plot_canvas.py Run000000_PixelAlive.root "Detector/Board_0/OpticalGroup_0/Hybrid_0/Chip_0/D_B(0)_O(0)_H(0)_PixelAlive_Chip(0)" -o plots
- python ci_tools/plot_canvas.py Run000001_ThrEqualization.root "Detector/Board_0/OpticalGroup_0/Hybrid_0/Chip_0/D_B(0)_O(0)_H(0)_ThrEqualization_Chip(0)" -o plots
- python ci_tools/plot_canvas.py Run000002_SCurve.root "Detector/Board_0/OpticalGroup_0/Hybrid_0/Chip_0/D_B(0)_O(0)_H(0)_SCurves_Chip(0)" -o plots
artifacts:
paths:
- plots
......@@ -91,7 +91,7 @@ run_on_2S:
- cp Results/*/Hybrid.root .
artifacts:
paths:
- Hybrid.root
- Hybrid.root
- ci_tools/plot_hist.py
expire_in: 1 week
......@@ -105,7 +105,6 @@ check_run_on_2S:
- plots
expire_in: 1 week
## 2S hybrid
run_on_2S_FNAL:
tags:
......@@ -124,7 +123,7 @@ run_on_2S_FNAL:
- cp Results/*/Hybrid.root .
artifacts:
paths:
- Hybrid.root
- Hybrid.root
- ci_tools/plot_hist.py
expire_in: 1 week
......@@ -137,5 +136,3 @@ check_run_on_2S_FNAL:
paths:
- plots
expire_in: 1 week
......@@ -455,7 +455,7 @@ bool D19cFWInterface::GBTLock(const BeBoard* pBoard)
} while(std::cin.get() != '\n');
// system("/home/modtest/Programming/power_supply/bin/TurnOn -c /home/modtest/Programming/power_supply/config/config.xml ");
// std::this_thread::sleep_for (std::chrono::milliseconds (1000) );
for(auto cLinkId: cLinkIds)
{
// reset here for good measure
......@@ -1685,7 +1685,6 @@ uint32_t D19cFWInterface::CountFwEvents(BeBoard* pBoard, std::vector<uint32_t>&
}
void D19cFWInterface::ReadMPACounters(BeBoard* pBoard, std::vector<uint32_t>& pData, bool cFast = true)
{
// get event type
EventType cEventType = pBoard->getEventType();
if(cEventType == EventType::MPAAS)
......@@ -1764,8 +1763,7 @@ void D19cFWInterface::ReadMPACounters(BeBoard* pBoard, std::vector<uint32_t>& pD
for(int i = 0; i < 2040; i++)
{
pData.push_back(ReadReg("fc7_daq_ctrl.physical_interface_block.fifo2_data") - 1);
LOG(DEBUG) << BOLDBLUE << "pData "<<i<<" "<< pData[i] << RESET;
LOG(DEBUG) << BOLDBLUE << "pData " << i << " " << pData[i] << RESET;
}
std::this_thread::sleep_for(std::chrono::microseconds(fWait_us));
......@@ -2187,7 +2185,6 @@ void D19cFWInterface::ReadASEvent(BeBoard* pBoard, std::vector<uint32_t>& pData)
}
bool D19cFWInterface::WaitForData(BeBoard* pBoard)
{
bool pFailed = false;
auto cNevents = this->ReadReg("fc7_daq_cnfg.fast_command_block.triggers_to_accept");
auto cTriggerSource = this->ReadReg("fc7_daq_cnfg.fast_command_block.trigger_source"); // trigger source
......@@ -4242,4 +4239,49 @@ void D19cFWInterface::Align_out()
}
}
void D19cFWInterface::ResetOptoLink(Ph2_HwDescription::Chip* pChip)
{
std::vector<std::pair<std::string, uint32_t>> cVecReg;
cVecReg.push_back({"fc7_daq_ctrl.optical_block.ic", 0x00});
cVecReg.push_back({"fc7_daq_cnfg.optical_block.ic", 0x00});
cVecReg.push_back({"fc7_daq_cnfg.optical_block.gbtx", 0x00});
this->WriteStackReg(cVecReg);
}
bool D19cFWInterface::WriteOptoLinkRegister(Ph2_HwDescription::Chip* pChip, uint32_t pAddress, uint32_t pData, bool pVerifLoop)
{
// Reset
ResetOptoLink(pChip);
// Config transaction register
this->WriteReg("fc7_daq_cnfg.optical_block.gbtx.address", flpGBTAddress);
this->WriteReg("fc7_daq_cnfg.optical_block.gbtx.data", pData);
this->WriteReg("fc7_daq_cnfg.optical_block.ic.register", pAddress);
// Perform transaction
this->WriteReg("fc7_daq_ctrl.optical_block.ic.write", 0x01);
this->WriteReg("fc7_daq_ctrl.optical_block.ic.write", 0x00);
//
this->WriteReg("fc7_daq_ctrl.optical_block.ic.start_write", 0x01);
this->WriteReg("fc7_daq_ctrl.optical_block.ic.start_write", 0x00);
return true;
}
uint32_t D19cFWInterface::ReadOptoLinkRegister(Ph2_HwDescription::Chip* pChip, uint32_t pAddress)
{
// Reset
ResetOptoLink(pChip);
// Config transaction register
this->WriteReg("fc7_daq_cnfg.optical_block.gbtx.address", flpGBTAddress);
this->WriteReg("fc7_daq_cnfg.optical_block.ic.register", pAddress);
this->WriteReg("fc7_daq_cnfg.optical_block.ic.nwords", 0x01);
// Perform transaction
this->WriteReg("fc7_daq_ctrl.optical_block.ic.start_read", 0x01);
this->WriteReg("fc7_daq_ctrl.optical_block.ic.start_read", 0x00);
//
this->WriteReg("fc7_daq_ctrl.optical_block.ic.read", 0x01);
this->WriteReg("fc7_daq_ctrl.optical_block.ic.read", 0x00);
//
uint32_t cReadBack = this->ReadReg("fc7_daq_stat.optical_block.ic.data");
return cReadBack;
}
} // namespace Ph2_HwInterface
......@@ -730,10 +730,11 @@ class D19cFWInterface : public BeBoardFWInterface
// ############################
// # Read/Write Optical Group #
// ############################
uint8_t flpGBTAddress = 0x70;
void StatusOptoLink(Ph2_HwDescription::Chip* pChip, uint32_t& isReady, uint32_t& isFIFOempty) override {}
void ResetOptoLink(Ph2_HwDescription::Chip* pChip) override {}
bool WriteOptoLinkRegister(Ph2_HwDescription::Chip* pChip, uint32_t pAddress, uint32_t pData, bool pVerifLoop = false) override { return false; }
uint32_t ReadOptoLinkRegister(Ph2_HwDescription::Chip* pChip, uint32_t pAddress) override { return 0; }
void ResetOptoLink(Ph2_HwDescription::Chip* pChip) override;
bool WriteOptoLinkRegister(Ph2_HwDescription::Chip* pChip, uint32_t pAddress, uint32_t pData, bool pVerifLoop = false) override;
uint32_t ReadOptoLinkRegister(Ph2_HwDescription::Chip* pChip, uint32_t pAddress) override;
};
} // namespace Ph2_HwInterface
......
This diff is collapsed.
......@@ -26,283 +26,159 @@ class D19clpGBTInterface : public lpGBTInterface
TC_PSROH fTC_PSROH;
#endif
// ##################################
// # LpGBT register access functions#
// ##################################
bool ConfigureChip(Ph2_HwDescription::Chip* pChip, bool pVerifLoop = true, uint32_t pBlockSize = 310) override;
// ###################################
// # LpGBT register access functions #
// ###################################
// General configuration of the lpGBT chip from register file
bool ConfigureChip(Ph2_HwDescription::Chip* pChip, bool pVerifLoop = true, uint32_t pBlockSize = 310) override;
// R/W functions using register name
bool WriteChipReg(Ph2_HwDescription::Chip* pChip, const std::string& pRegNode, uint16_t pValue, bool pVerifLoop = true) override;
uint16_t ReadChipReg(Ph2_HwDescription::Chip* pChip, const std::string& pRegNode) override;
bool WriteChipMultReg(Ph2_HwDescription::Chip* pChip, const std::vector<std::pair<std::string, uint16_t>>& RegVec, bool pVerifLoop = true) override;
bool WriteReg(Ph2_HwDescription::Chip* pChip, uint16_t pAddress, uint16_t pValue, bool pVerifLoop = true);
// R/W functions using register address
bool WriteReg(Ph2_HwDescription::Chip* pChip, uint16_t pAddress, uint16_t pValue, bool pVerifLoop = false);
uint16_t ReadReg(Ph2_HwDescription::Chip* pChip, uint16_t pAddress);
bool WriteChipMultReg(Ph2_HwDescription::Chip* pChip, const std::vector<std::pair<std::string, uint16_t>>& RegVec, bool pVerifLoop = true) override;
// ######################################
// # LpGBT block configuration functions#
// ######################################
/*!
* \brief Sets the flag used to select which lpGBT configuration interface to use
* \param pChip : pointer to Chip object
* \param pMode : configuration interface ["serial" / "i2c"]
*/
void SetConfigMode(Ph2_HwDescription::Chip* pChip, const std::string& pMode);
/*!
* \brief Configures the lpGBT Rx Groups
* \param pChip : pointer to Chip object
* \param pGroups : Rx Groups vector
* \param pChannels : Rx Channels vector
* \param pDataRate : Data Rate
* \param pTrackMode : Phase Tracking Mode
*/
void ConfigureRxGroups(Ph2_HwDescription::Chip* pChip, const std::vector<uint8_t>& pGroups, const std::vector<uint8_t>& pChannels, uint8_t pDataRate = 0, uint8_t pTrackMode = 0);
// #######################################
// # LpGBT block configuration functions #
// #######################################
// Sets the flag used to select which lpGBT configuration interface to use
void SetConfigMode(Ph2_HwDescription::Chip* pChip, const std::string& pMode, bool pToggle);
// Configures the lpGBT Rx Groups
void ConfigureRxGroups(Ph2_HwDescription::Chip* pChip, const std::vector<uint8_t>& pGroups, const std::vector<uint8_t>& pChannels, uint8_t pDataRate, uint8_t pTrackMode);
// Configure lpGBT Rx Channels
/*!
* \brief Configure lpGBT Rx Channels
* \param pChip : pointer to Chip object
* \param pGroups : Rx Groups vector
* \param pChannels : Rx Channels vector
* \param pEqual : Equalization control
* \param pTerm : 100 Ohm termination
* \param pAcBias : Common mode generation
* \param pInvert : Channel invertion
* \param pPhase : Channel phase selection
*/
void ConfigureRxChannels(Ph2_HwDescription::Chip* pChip,
const std::vector<uint8_t>& pGroups,
const std::vector<uint8_t>& pChannels,
uint8_t pEqual = 0,
uint8_t pTerm = 1,
uint8_t pAcBias = 0,
uint8_t pInvert = 0,
uint8_t pPhase = 12);
/*!
* \brief Configure lpGBT Tx Groups
* \param pChip : pointer to Chip object
* \param pGroups : Tx Groups vector
* \param pChannels : Tx Channels vector
* \param pDataRate : Data Rate
*/
void ConfigureTxGroups(Ph2_HwDescription::Chip* pChip, const std::vector<uint8_t>& pGroups, const std::vector<uint8_t>& pChannels, uint8_t pDataRate = 0);
/*!
* \brief Configure lpGBT Tx Channels
* \param pChip : pointer to Chip object
* \param pGroups : Tx Groups vector
* \param pChannels : Tx Channels vector
* \param pDriveStr : Driving strenght
* \param pPreEmphMode : Pre-Emphasis mode
* \param pPreEmphStr : Pre-Emphasis strength
* \param pPreEmphWidth : Width of the pre-emphasis pulse
* \param pInvert : Channel inversion
*/
uint8_t pEqual,
uint8_t pTerm,
uint8_t pAcBias,
uint8_t pInvert,
uint8_t pPhase);
// Configure lpGBT Tx Groups
void ConfigureTxGroups(Ph2_HwDescription::Chip* pChip, const std::vector<uint8_t>& pGroups, const std::vector<uint8_t>& pChannels, uint8_t pDataRate);
// Configure lpGBT Tx Channels
void ConfigureTxChannels(Ph2_HwDescription::Chip* pChip,
const std::vector<uint8_t>& pGroups,
const std::vector<uint8_t>& pChannels,
uint8_t pDriveStr = 0,
uint8_t pPreEmphMode = 0,
uint8_t pPreEmphStr = 0,
uint8_t pPreEmphWidth = 0,
uint8_t pInvert = 0);
/*!
* \brief Configure lpGBT Clocks
* \param pChip : pointer to Chip object
* \param pClock : Clocks vector
* \param pFreq : Frequency
* \param pDriveStr : Driving strength
* \param pInvert : Clock inversion
* \param pPreEmphWidth : Width of the pre-emphasis pulse
* \param pPreEmphMode : Pre-Emphasis mode
* \param pPreEmphStr : Pre-Emphasis strength
*/
uint8_t pDriveStr,
uint8_t pPreEmphMode,
uint8_t pPreEmphStr,
uint8_t pPreEmphWidth,
uint8_t pInvert);
// Configure lpGBT Clocks
void ConfigureClocks(Ph2_HwDescription::Chip* pChip,
const std::vector<uint8_t>& pClock,
uint8_t pFreq = 0,
uint8_t pDriveStr = 0,
uint8_t pInvert = 0,
uint8_t pPreEmphWidth = 0,
uint8_t pPreEmphMode = 0,
uint8_t pPreEmphStr = 0);
/*!
* \brief Configure lpGBT Tx and Rx polarity
* \param pChip : pointer to Chip object
* \param pTxPolarity : Tx polarity
* \param pRxPolarity : Rx polarity
*/
void ConfigureTxRxPolarity(Ph2_HwDescription::Chip* pChip, uint8_t pTxPolarity = 1, uint8_t pRxPolarity = 0);
/*!
* \brief Configure lpGBT Data Player pattern
* \param pChip : pointer to Chip object
* \param pPattern : Data player pattern
*/
uint8_t pFreq,
uint8_t pDriveStr,
uint8_t pInvert,
uint8_t pPreEmphWidth,
uint8_t pPreEmphMode,
uint8_t pPreEmphStr);
// Configure lpGBT High Speed Link Tx and Rx polarity
void ConfigureHighSpeedPolarity(Ph2_HwDescription::Chip* pChip, uint8_t pOutPolarity, uint8_t pInPolarity);
// Configure lpGBT Data Player pattern
void ConfigureDPPattern(Ph2_HwDescription::Chip* pChip, uint32_t pPattern);
/*!
* \brief Configure lpGBT Rx Pseudo-Random Binary Sequence
* \param pChip : pointer to Chip object
* \param pGroups : Rx Groups vector
* \param pChannels : Rx Channels vector
* \param pEnable : Enable Pseudo-Random Binary Sequence
*/
void ConfigureRxPRBS(Ph2_HwDescription::Chip* pChip, const std::vector<uint8_t>& pGroups, const std::vector<uint8_t>& pChannels, bool pEnable = false);
/*!
* \brief Configure lpGBT Rx Groups data source
* \param pChip : pointer to Chip object
* \param pGroups : Rx Groups vector
* \param pSource : Rx data source
*/
void ConfigureRxSource(Ph2_HwDescription::Chip* pChip, const std::vector<uint8_t>& pGroups, uint8_t pSource = 0);
/*!
* \brief Configure lpGBT Tx Groups data source
* \param pChip : pointer to Chip object
* \param pGroups : Tx Groups vector
* \param pSource : Tx data source
*/
void ConfigureTxSource(Ph2_HwDescription::Chip* pChip, const std::vector<uint8_t>& pGroups, uint8_t pSource = 0);
/*!
* \brief Configure lpGBT Rx channels phase
* \param pChip : pointer to Chip object
* \param pGroup : Rx Groups vector
* \param pChannel : Rx Channels vector
* \param pPhase : Rx phase selection
*/
void ConfigureRxPhase(Ph2_HwDescription::Chip* pChip, uint8_t pGroup, uint8_t pChannel, uint8_t pPhase = 0);
/*!
* \brief Configure lpGBT Phase Shifter
* \param pChip : pointer to Chip object
* \param pClocks : Clocks vector
* \param pFreq : Frequency
* \param pDriveStr : Driving strength
* \param pEnFTune : Enable fine deskewing
* \param pDelay : Clock delay
*/
void ConfigurePhShifter(Ph2_HwDescription::Chip* pChip, const std::vector<uint8_t>& pClocks, uint8_t pFreq = 0, uint8_t pDriveStr = 0, uint8_t pEnFTune = 0, uint16_t pDelay = 0);
// Configure lpGBT Rx Pseudo-Random Binary Sequence
void ConfigureRxPRBS(Ph2_HwDescription::Chip* pChip, const std::vector<uint8_t>& pGroups, const std::vector<uint8_t>& pChannels, bool pEnable);
// Configure lpGBT Rx Groups data source
void ConfigureRxSource(Ph2_HwDescription::Chip* pChip, const std::vector<uint8_t>& pGroups, uint8_t pSource);
// Configure lpGBT Tx Groups data source
void ConfigureTxSource(Ph2_HwDescription::Chip* pChip, const std::vector<uint8_t>& pGroups, uint8_t pSource);
// Configure lpGBT Rx channels phase
void ConfigureRxPhase(Ph2_HwDescription::Chip* pChip, uint8_t pGroup, uint8_t pChannel, uint8_t pPhase);
// Configure lpGBT Phase Shifter
void ConfigurePhShifter(Ph2_HwDescription::Chip* pChip, const std::vector<uint8_t>& pClocks, uint8_t pFreq, uint8_t pDriveStr, uint8_t pEnFTune, uint16_t pDelay);
// ####################################
// # LpGBT specific routine functions #
// ####################################
/*!
* \brief lpGBT Rx Groups(Channels) phase training
* \param pChip : pointer to Chip object
* \param pGroups : Rx Groups vector
*/
// lpGBT Rx Groups(Channels) phase training
void PhaseTrainRx(Ph2_HwDescription::Chip* pChip, const std::vector<uint8_t>& pGroups);
/*!
* \brief lpGBT Rx Groups(Channels) phase alignment
* \param pChip : pointer to Chip object
* \param pGroups : Rx Groups vector
* \param pChannels : Rx Channels vector
*/
// lpGBT Rx Groups(Channels) phase alignment
void PhaseAlignRx(Ph2_HwDescription::Chip* pChip, const std::vector<uint8_t>& pGroups, const std::vector<uint8_t>& pChannels);
// LpGBT block status functions
/*!
* \brief Print out lpGBT chip mode (data rate, FEC, transmission mode)
* \param pChip : pointer to Chip object
*/
// ################################
// # LpGBT Block Status functions #
// ################################
// Print out lpGBT chip mode (data rate, FEC, transmission mode)
void PrintChipMode(Ph2_HwDescription::Chip* pChip);
/*!
* \brief Get lpGBT Rx Group Delay-Locked-Loop state machine
* \param pChip : pointer to Chip object
* \param pGroup : Rx Groups vector
*/
// Get lpGBT Rx Group Delay-Locked-Loop state machine
uint8_t GetRxDllStatus(Ph2_HwDescription::Chip* pChip, uint8_t pGroup);
/*!
* \brief Get lpGBT Rx Channel phase
* \param pChip : pointer to Chip object
* \param pGroup : Rx Groups vector
* \param pChannel : Rx Channels vector
*/
// Get lpGBT Rx Channel phase
uint8_t GetRxPhase(Ph2_HwDescription::Chip* pChip, uint8_t pGroup, uint8_t pChannel);
/*!
* \brief Get lpGBT Rx locking status
* \param pChip : pointer to Chip object
* \param pGroup : Rx Groups vector
*/
bool IsRxLocked(Ph2_HwDescription::Chip* pChip, uint8_t pGroup);
/*!
* \brief Get lpGBT Power Up State Machine status
* \param pChip : pointer to Chip object
*/
bool IslpGBTReady(Ph2_HwDescription::Chip* pChip);
// Get lpGBT Rx locking status
bool IsRxLocked(Ph2_HwDescription::Chip* pChip, uint8_t pGroup, const std::vector<uint8_t>& pChannels);
// Get lpGBT Power Up State Machine status
uint8_t GetPUSMStatus(Ph2_HwDescription::Chip* pChip);
// ##############################################
// # LpGBT I2C Masters functions (Slow Control) #
// ##############################################
/*!
* \brief Reset I2C Masters
* \param pChip : pointer to Chip object
* \param pMasters : I2C Masters vector
*/
// Reset I2C Masters
void ResetI2C(Ph2_HwDescription::Chip* pChip, const std::vector<uint8_t>& pMasters);
/*!
* \brief Configure lpGBT I2C Master
* \param pChip : pointer to Chip object
* \param pMaster : I2C Master
* \param pNBytes : Number of bytes
* \param pSCLDriveMode : SCL drive strength
*/
void ConfigureI2C(Ph2_HwDescription::Chip* pChip, uint8_t pMaster, uint8_t pFreq = 0, uint8_t pNBytes = 1, uint8_t pSCLDriveMode = 0);
/*!
* \brief I2C Write transaction using the lpGBT I2C Master
* \param pChip : pointer to Chip object
* \param pMaster : I2C Master
* \param pSlaveAddress : Slave address
* \param pData : Data
* \param pNBytes : Number of bytes
*/
bool WriteI2C(Ph2_HwDescription::Chip* pChip, uint8_t pMaster, uint8_t pSlaveAddress, uint32_t pData, uint8_t pNBytes = 1);
/*!
* \brief I2C Read transaction using the lpGBT I2C Master
* \param pChip : pointer to Chip object
* \param pMaster : I2C Master
* \param pSlaveAddress : Slave address
* \param pNBytes : Number of bytes
*/
uint32_t ReadI2C(Ph2_HwDescription::Chip* pChip, uint8_t pMaster, uint8_t pSlaveAddress, uint8_t pNBytes = 1);
/*!
* \brief Get lpGBT I2C Master status
* \param pChip : pointer to Chip object
* \param pMaster : I2C Master
*/
// Configure lpGBT I2C Master
void ConfigureI2C(Ph2_HwDescription::Chip* pChip, uint8_t pMaster, uint8_t pFreq, uint8_t pNBytes, uint8_t pSCLDriveMode);
// I2C Write transaction using the lpGBT I2C Master
bool WriteI2C(Ph2_HwDescription::Chip* pChip, uint8_t pMaster, uint8_t pSlaveAddress, uint32_t pData, uint8_t pNBytes);
// I2C Read transaction using the lpGBT I2C Master
uint32_t ReadI2C(Ph2_HwDescription::Chip* pChip, uint8_t pMaster, uint8_t pSlaveAddress, uint8_t pNBytes);
// Get lpGBT I2C Master status
uint8_t GetI2CStatus(Ph2_HwDescription::Chip* pChip, uint8_t pMaster);
// ###########################
// # LpGBT ADC-DAC functions #
// ###########################
/*!
* \brief Read lpGBT ADC
* \param pChip : pointer to Chip object
* \param pADCInput : ADC input
*/
// configure ADC
void ConfigureADC(Ph2_HwDescription::Chip* pChip, uint8_t pGainSelect, uint8_t pADCCoreDiffEnable);
// brief Read single ended lpGBT ADC
uint16_t ReadADC(Ph2_HwDescription::Chip* pChip, const std::string& pADCInput);
/*!
* \brief Read lpGBT differential ADC
* \param pChip : pointer to Chip object
* \param pADCInputP : ADC input positive
* \param pADCInputN : ADC input negative
*/
// Read lpGBT differential ADC
uint16_t ReadADCDiff(Ph2_HwDescription::Chip* pChip, const std::string& pADCInputP, const std::string& pADCInputN);
// ########################
// # LpGBT GPIO functions #
// ########################
void ConfigureGPIO(Ph2_HwDescription::Chip* pChip, const std::vector<uint8_t>& pGPIOs, uint8_t pInOut, uint8_t pHighLow, uint8_t pDriveStr, uint8_t pPullEn, uint8_t pPullUpDown);
// #####################
// # LpGBT BERT Tester #
// #####################
// configure BER tester
void ConfigureBERT(Ph2_HwDescription::Chip* pChip, uint8_t pCoarseSource, uint8_t pFineSource, uint8_t pMeasTime, uint8_t pSkipDisable, bool pStart);
// configure BER pattern
void ConfigureBERTPattern(Ph2_HwDescription::Chip* pChip, uint32_t pPattern);
// get BER status
uint8_t GetBERTStatus(Ph2_HwDescription::Chip* pChip);
// get BERT errors
uint64_t GetBERTErrors(Ph2_HwDescription::Chip* pChip);
// perform BER test
float PerformBERTest(Ph2_HwDescription::Chip* pChip, uint8_t pCoarseSource, uint8_t pFineSource, uint8_t pMeasTime, uint8_t pSkipDisable, uint32_t pPattern);
// ###################################
// # Outer Tracker specific funtions #
// ###################################
// configure PS-ROH
void ConfigurePSROH(Ph2_HwDescription::Chip* pChip, uint8_t pRate);
// cbc read/write
bool cbcWrite(Ph2_HwDescription::Chip* pChip, uint8_t pFeId, uint8_t pChipId, uint8_t pPage, uint8_t pRegistergAddress, uint8_t pRegisterValue, bool pReadBack = true, bool pSetPage = false)
{
return true;
}
uint32_t cbcRead(Ph2_HwDescription::Chip* pChip, uint8_t pFeId, uint8_t pChipId, uint8_t pPage, uint8_t pRegisterAddress) { return 0; }
uint8_t cbcSetPage(Ph2_HwDescription::Chip* pChip, uint8_t pFeId, uint8_t pChipId, uint8_t pPage) { return 0; }
uint8_t cbcGetPageRegister(Ph2_HwDescription::Chip* pChip, uint8_t pFeId, uint8_t cChipId) { return 0; }
// cic read/write
bool cicWrite(Ph2_HwDescription::Chip* pChip, uint8_t pFeId, uint16_t pRegisterAddress, uint8_t pRegisterValue, bool pRetry = false);
uint32_t cicRead(Ph2_HwDescription::Chip* pChip, uint8_t pFeId, uint16_t pRegisterAddress);
// ssa read/write
bool ssaWrite(Ph2_HwDescription::Chip* pChip, uint8_t pFeId, uint8_t pChipId, uint16_t pRegisterAddress, uint8_t pRegisterValue, bool pRetry = false);
uint32_t ssaRead(Ph2_HwDescription::Chip* pChip, uint8_t pFeId, uint8_t pChipId, uint16_t pRegisterAddress);
// mpa read/write
bool mpaWrite(Ph2_HwDescription::Chip* pChip, uint8_t pFeId, uint8_t pChipId, uint16_t pRegisterAddress, uint8_t pRegisterValue, bool pRetry = false);
uint32_t mpaRead(Ph2_HwDescription::Chip* pChip, uint8_t pFeId, uint8_t pChipId, uint16_t pRegisterAddress);
private:
std::map<std::string, uint8_t> fADCInputMap = {{"ADC0", 0},
{"ADC1", 1},
......
......@@ -44,12 +44,12 @@ uint16_t MPAInterface::ReadChipReg(Chip* pMPA, const std::string& pRegNode)
bool MPAInterface::WriteChipReg(Chip* pMPA, const std::string& pRegNode, uint16_t pValue, bool pVerifLoop)
{
setBoard(pMPA->getBeBoardId());
//need to or success
if (pRegNode=="ThDAC_ALL")
{
// need to or success
if(pRegNode == "ThDAC_ALL")
{
this->Set_threshold(pMPA, pValue);
return true;
}
}
ChipRegItem cRegItem = pMPA->getRegItem(pRegNode);
cRegItem.fValue = pValue & 0xFF;
std::vector<uint32_t> cVec;
......@@ -134,23 +134,19 @@ bool MPAInterface::WriteChipAllLocalReg(ReadoutChip* pMPA, const std::string& da
else
LOG(ERROR) << "Error, DAC " << dacName << " is not a Local DAC";
std::vector<std::pair<std::string, uint16_t>> cRegVec;
ChannelGroup<NMPACHANNELS, 1> channelToEnable;
std::vector<uint32_t> cVec;
ChannelGroup<NMPACHANNELS, 1> channelToEnable;
std::vector<uint32_t> cVec;
cVec.clear();
bool cSuccess = true;
for(uint16_t iChannel = 0; iChannel < pMPA->getNumberOfChannels(); ++iChannel)
{
char dacName1[20];
sprintf(dacName1, dacTemplate.c_str(), 1 + iChannel);
LOG(DEBUG) << BOLDBLUE << "Setting register " << dacName1 << " to " << (localRegValues.getChannel<uint16_t>(iChannel) & 0x1F) << RESET;
cSuccess = cSuccess && this->WriteChipReg(pMPA, dacName1, (localRegValues.getChannel<uint16_t>(iChannel) & 0x1F), pVerifLoop);