Separating the design hierarchy for multiple board support

This merge request introduces a preliminary work on support for ZCU102 board. It separates the design hierarchy into two parallel ones. This is due to the different physical interfaces of the boards. It shall allow a better readability of the structure and the code.

Main changes includes:

• Creation of different top modules for each board
• Creation of different system cores for each board
• Creation of different user cores for each board

The idea is that the top structure will be board dependent and the project implementation either board depend, or completely board agnostic with a generic architecture.

fw/prj/create_vivado_project.tcl

@@ -3,7 +3,7 @@
 #
 # create_vivado_project.tcl: Tcl script for re-creating project 'boreal_vivado'
 #
-# Generated by Vivado on Thu Mar 07 16:57:49 CET 2024
+# Generated by Vivado on Fri Mar 08 17:35:24 CET 2024
 # IP Build 3864474 on Sun May  7 20:36:21 MDT 2023
 #
 # This file contains the Vivado Tcl commands for re-creating the project to the state*
@@ -33,13 +33,17 @@
 #    "/work/caribou/boreal/fw/src/sys/axi4lite_slave_if/synth/axi4lite_slave_if.vhd"
 #    "/work/caribou/boreal/fw/src/sys/reg_if/synth/reg_if.vhd"
 #    "/work/caribou/boreal/fw/src/sys/reg_map_if/synth/reg_map_if.vhd"
+#    "/work/caribou/boreal/fw/src/sys/fw_id/synth/fw_id.vhd"
 #    "/work/caribou/boreal/fw/src/usr/blink_led/synth/blink_led.vhd"
 #    "/work/caribou/boreal/fw/src/bd/zc706_ps/hdl/zc706_ps_wrapper.vhd"
-#    "/work/caribou/boreal/fw/src/sys/fw_id/synth/fw_id.vhd"
-#    "/work/caribou/boreal/fw/src/sys/sys_core/synth/sys_core.vhd"
-#    "/work/caribou/boreal/fw/src/usr/usr_core/synth/usr_core.vhd"
-#    "/work/caribou/boreal/fw/src/top/synth/boreal_top.vhd"
+#    "/work/caribou/boreal/fw/src/sys/sys_core/synth/zc706_sys_core.vhd"
+#    "/work/caribou/boreal/fw/src/usr/usr_core/synth/zc706_usr_core.vhd"
+#    "/work/caribou/boreal/fw/src/top/synth/zc706_top.vhd"
+#    "/work/caribou/boreal/fw/src/usr/usr_core/synth/zcu102_usr_core.vhd"
+#    "/work/caribou/boreal/fw/src/sys/sys_core/synth/zcu102_sys_core.vhd"
+#    "/work/caribou/boreal/fw/src/top/synth/zcu102_top.vhd"
 #    "/work/caribou/boreal/fw/src/bd/zcu102_ps/zcu102_ps.bd"
+#    "/work/caribou/boreal/fw/src/bd/zcu102_ps/hdl/zcu102_ps_wrapper.vhd"
 #    "/work/caribou/boreal/fw/src/usr/blink_led/xdc/blink_led_phy.tcl"
 #    "/work/caribou/boreal/fw/src/usr/blink_led/xdc/blink_led_timing.tcl"
 #    "/work/caribou/boreal/fw/src/sys/fw_id/xdc/usr_access.xdc"
@@ -57,13 +61,17 @@ proc checkRequiredFiles { origin_dir} {
  "[file normalize "$origin_dir/../src/sys/axi4lite_slave_if/synth/axi4lite_slave_if.vhd"]"\
  "[file normalize "$origin_dir/../src/sys/reg_if/synth/reg_if.vhd"]"\
  "[file normalize "$origin_dir/../src/sys/reg_map_if/synth/reg_map_if.vhd"]"\
+ "[file normalize "$origin_dir/../src/sys/fw_id/synth/fw_id.vhd"]"\
  "[file normalize "$origin_dir/../src/usr/blink_led/synth/blink_led.vhd"]"\
  "[file normalize "$origin_dir/../src/bd/zc706_ps/hdl/zc706_ps_wrapper.vhd"]"\
- "[file normalize "$origin_dir/../src/sys/fw_id/synth/fw_id.vhd"]"\
- "[file normalize "$origin_dir/../src/sys/sys_core/synth/sys_core.vhd"]"\
- "[file normalize "$origin_dir/../src/usr/usr_core/synth/usr_core.vhd"]"\
- "[file normalize "$origin_dir/../src/top/synth/boreal_top.vhd"]"\
+ "[file normalize "$origin_dir/../src/sys/sys_core/synth/zc706_sys_core.vhd"]"\
+ "[file normalize "$origin_dir/../src/usr/usr_core/synth/zc706_usr_core.vhd"]"\
+ "[file normalize "$origin_dir/../src/top/synth/zc706_top.vhd"]"\
+ "[file normalize "$origin_dir/../src/usr/usr_core/synth/zcu102_usr_core.vhd"]"\
+ "[file normalize "$origin_dir/../src/sys/sys_core/synth/zcu102_sys_core.vhd"]"\
+ "[file normalize "$origin_dir/../src/top/synth/zcu102_top.vhd"]"\
  "[file normalize "$origin_dir/../src/bd/zcu102_ps/zcu102_ps.bd"]"\
+ "[file normalize "$origin_dir/../src/bd/zcu102_ps/hdl/zcu102_ps_wrapper.vhd"]"\
  "[file normalize "$origin_dir/../src/usr/blink_led/xdc/blink_led_phy.tcl"]"\
  "[file normalize "$origin_dir/../src/usr/blink_led/xdc/blink_led_timing.tcl"]"\
  "[file normalize "$origin_dir/../src/sys/fw_id/xdc/usr_access.xdc"]"\
@@ -271,13 +279,17 @@ set files [list \
  [file normalize "${origin_dir}/../src/sys/axi4lite_slave_if/synth/axi4lite_slave_if.vhd"] \
  [file normalize "${origin_dir}/../src/sys/reg_if/synth/reg_if.vhd"] \
  [file normalize "${origin_dir}/../src/sys/reg_map_if/synth/reg_map_if.vhd"] \
+ [file normalize "${origin_dir}/../src/sys/fw_id/synth/fw_id.vhd"] \
  [file normalize "${origin_dir}/../src/usr/blink_led/synth/blink_led.vhd"] \
  [file normalize "${origin_dir}/../src/bd/zc706_ps/hdl/zc706_ps_wrapper.vhd"] \
- [file normalize "${origin_dir}/../src/sys/fw_id/synth/fw_id.vhd"] \
- [file normalize "${origin_dir}/../src/sys/sys_core/synth/sys_core.vhd"] \
- [file normalize "${origin_dir}/../src/usr/usr_core/synth/usr_core.vhd"] \
- [file normalize "${origin_dir}/../src/top/synth/boreal_top.vhd"] \
+ [file normalize "${origin_dir}/../src/sys/sys_core/synth/zc706_sys_core.vhd"] \
+ [file normalize "${origin_dir}/../src/usr/usr_core/synth/zc706_usr_core.vhd"] \
+ [file normalize "${origin_dir}/../src/top/synth/zc706_top.vhd"] \
+ [file normalize "${origin_dir}/../src/usr/usr_core/synth/zcu102_usr_core.vhd"] \
+ [file normalize "${origin_dir}/../src/sys/sys_core/synth/zcu102_sys_core.vhd"] \
+ [file normalize "${origin_dir}/../src/top/synth/zcu102_top.vhd"] \
  [file normalize "${origin_dir}/../src/bd/zcu102_ps/zcu102_ps.bd"] \
+ [file normalize "${origin_dir}/../src/bd/zcu102_ps/hdl/zcu102_ps_wrapper.vhd"] \
 ]
 add_files -norecurse -fileset $obj $files
 
@@ -357,6 +369,18 @@ set_property -name "used_in" -value "synthesis simulation" -objects $file_obj
 set_property -name "used_in_simulation" -value "1" -objects $file_obj
 set_property -name "used_in_synthesis" -value "1" -objects $file_obj
 
+set file "$origin_dir/../src/sys/fw_id/synth/fw_id.vhd"
+set file [file normalize $file]
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "VHDL 2008" -objects $file_obj
+set_property -name "is_enabled" -value "1" -objects $file_obj
+set_property -name "is_global_include" -value "0" -objects $file_obj
+set_property -name "library" -value "xil_defaultlib" -objects $file_obj
+set_property -name "path_mode" -value "RelativeFirst" -objects $file_obj
+set_property -name "used_in" -value "synthesis simulation" -objects $file_obj
+set_property -name "used_in_simulation" -value "1" -objects $file_obj
+set_property -name "used_in_synthesis" -value "1" -objects $file_obj
+
 set file "$origin_dir/../src/usr/blink_led/synth/blink_led.vhd"
 set file [file normalize $file]
 set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
@@ -381,7 +405,7 @@ set_property -name "used_in" -value "synthesis simulation" -objects $file_obj
 set_property -name "used_in_simulation" -value "1" -objects $file_obj
 set_property -name "used_in_synthesis" -value "1" -objects $file_obj
 
-set file "$origin_dir/../src/sys/fw_id/synth/fw_id.vhd"
+set file "$origin_dir/../src/sys/sys_core/synth/zc706_sys_core.vhd"
 set file [file normalize $file]
 set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
 set_property -name "file_type" -value "VHDL 2008" -objects $file_obj
@@ -393,7 +417,7 @@ set_property -name "used_in" -value "synthesis simulation" -objects $file_obj
 set_property -name "used_in_simulation" -value "1" -objects $file_obj
 set_property -name "used_in_synthesis" -value "1" -objects $file_obj
 
-set file "$origin_dir/../src/sys/sys_core/synth/sys_core.vhd"
+set file "$origin_dir/../src/usr/usr_core/synth/zc706_usr_core.vhd"
 set file [file normalize $file]
 set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
 set_property -name "file_type" -value "VHDL 2008" -objects $file_obj
@@ -405,7 +429,7 @@ set_property -name "used_in" -value "synthesis simulation" -objects $file_obj
 set_property -name "used_in_simulation" -value "1" -objects $file_obj
 set_property -name "used_in_synthesis" -value "1" -objects $file_obj
 
-set file "$origin_dir/../src/usr/usr_core/synth/usr_core.vhd"
+set file "$origin_dir/../src/top/synth/zc706_top.vhd"
 set file [file normalize $file]
 set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
 set_property -name "file_type" -value "VHDL 2008" -objects $file_obj
@@ -417,10 +441,34 @@ set_property -name "used_in" -value "synthesis simulation" -objects $file_obj
 set_property -name "used_in_simulation" -value "1" -objects $file_obj
 set_property -name "used_in_synthesis" -value "1" -objects $file_obj
 
-set file "$origin_dir/../src/top/synth/boreal_top.vhd"
+set file "$origin_dir/../src/usr/usr_core/synth/zcu102_usr_core.vhd"
 set file [file normalize $file]
 set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
-set_property -name "file_type" -value "VHDL 2008" -objects $file_obj
+set_property -name "file_type" -value "VHDL" -objects $file_obj
+set_property -name "is_enabled" -value "1" -objects $file_obj
+set_property -name "is_global_include" -value "0" -objects $file_obj
+set_property -name "library" -value "xil_defaultlib" -objects $file_obj
+set_property -name "path_mode" -value "RelativeFirst" -objects $file_obj
+set_property -name "used_in" -value "synthesis simulation" -objects $file_obj
+set_property -name "used_in_simulation" -value "1" -objects $file_obj
+set_property -name "used_in_synthesis" -value "1" -objects $file_obj
+
+set file "$origin_dir/../src/sys/sys_core/synth/zcu102_sys_core.vhd"
+set file [file normalize $file]
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "VHDL" -objects $file_obj
+set_property -name "is_enabled" -value "1" -objects $file_obj
+set_property -name "is_global_include" -value "0" -objects $file_obj
+set_property -name "library" -value "xil_defaultlib" -objects $file_obj
+set_property -name "path_mode" -value "RelativeFirst" -objects $file_obj
+set_property -name "used_in" -value "synthesis simulation" -objects $file_obj
+set_property -name "used_in_simulation" -value "1" -objects $file_obj
+set_property -name "used_in_synthesis" -value "1" -objects $file_obj
+
+set file "$origin_dir/../src/top/synth/zcu102_top.vhd"
+set file [file normalize $file]
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "VHDL" -objects $file_obj
 set_property -name "is_enabled" -value "1" -objects $file_obj
 set_property -name "is_global_include" -value "0" -objects $file_obj
 set_property -name "library" -value "xil_defaultlib" -objects $file_obj
@@ -444,6 +492,18 @@ set_property -name "used_in_implementation" -value "1" -objects $file_obj
 set_property -name "used_in_simulation" -value "1" -objects $file_obj
 set_property -name "used_in_synthesis" -value "1" -objects $file_obj
 
+set file "$origin_dir/../src/bd/zcu102_ps/hdl/zcu102_ps_wrapper.vhd"
+set file [file normalize $file]
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "VHDL" -objects $file_obj
+set_property -name "is_enabled" -value "1" -objects $file_obj
+set_property -name "is_global_include" -value "0" -objects $file_obj
+set_property -name "library" -value "xil_defaultlib" -objects $file_obj
+set_property -name "path_mode" -value "RelativeFirst" -objects $file_obj
+set_property -name "used_in" -value "synthesis simulation" -objects $file_obj
+set_property -name "used_in_simulation" -value "1" -objects $file_obj
+set_property -name "used_in_synthesis" -value "1" -objects $file_obj
+
 
 # Set 'sources_1' fileset file properties for local files
 # None
@@ -460,8 +520,7 @@ set_property -name "include_dirs" -value "" -objects $obj
 set_property -name "lib_map_file" -value "" -objects $obj
 set_property -name "loop_count" -value "1000" -objects $obj
 set_property -name "name" -value "sources_1" -objects $obj
-set_property -name "top" -value "boreal_top" -objects $obj
-set_property -name "top_auto_set" -value "0" -objects $obj
+set_property -name "top" -value "zc706_top" -objects $obj
 set_property -name "verilog_define" -value "" -objects $obj
 set_property -name "verilog_uppercase" -value "0" -objects $obj
 set_property -name "verilog_version" -value "verilog_2001" -objects $obj
@@ -594,8 +653,7 @@ set_property -name "simmodel_value_check" -value "1" -objects $obj
 set_property -name "simulator_launch_mode" -value "off" -objects $obj
 set_property -name "source_set" -value "sources_1" -objects $obj
 set_property -name "systemc_include_dirs" -value "" -objects $obj
-set_property -name "top" -value "boreal_top" -objects $obj
-set_property -name "top_auto_set" -value "0" -objects $obj
+set_property -name "top" -value "zc706_top" -objects $obj
 set_property -name "top_lib" -value "xil_defaultlib" -objects $obj
 set_property -name "transport_int_delay" -value "0" -objects $obj
 set_property -name "transport_path_delay" -value "0" -objects $obj