Encapsulating AXI4Lite bus signals into a VHDL record type

This merge request improves the readability of the code by encapsulating the AXi4Lite bus interface into a single VHDL record type. The latter is defined as inout in the entity instantiation. This risk is taken as the interface is not to be changed and no ambiguity exists concerning the direction of every individual signal. In the worst case scenario, the direction can be identified either in the record definition via comments, or in the axi4lite_slave_if in the entity definition.