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Created date
Adapting top level interface according to board type
!29
· created
Dec 19, 2024
by
Younes Otarid
Format
Merged
updated
Dec 19, 2024
Reworking H2M integration for both ZC706 and ZCU102
!28
· created
Dec 19, 2024
by
Younes Otarid
Feature
Format
Merged
updated
Dec 19, 2024
Separating ZC706 and ZCU102 designs
!25
· created
Nov 26, 2024
by
Younes Otarid
Feature
Format
Merged
updated
Nov 26, 2024
Minor update to block designs
!21
· created
Nov 12, 2024
by
Younes Otarid
Format
Merged
updated
Nov 12, 2024
Integration of H2M device
!17
· created
Oct 29, 2024
by
Younes Otarid
Feature
Format
Merged
updated
Oct 29, 2024
Reworking boreal architecture
!15
· created
Aug 05, 2024
by
Younes Otarid
Feature
Format
Merged
updated
Aug 05, 2024
Refine boreal-manager
!14
· created
Jul 04, 2024
by
Younes Otarid
Documentation
Feature
Format
Merged
updated
Jul 04, 2024
factorised hierarchical structure for multi-board support
!10
· created
May 24, 2024
by
Younes Otarid
Feature
Format
Merged
updated
May 24, 2024
Extending support for ZCU102 board
!7
· created
Apr 03, 2024
by
Younes Otarid
Feature
Format
Simulation
Merged
updated
Apr 04, 2024
Encapsulating AXI4Lite bus signals into a VHDL record type
!6
· created
Mar 20, 2024
by
Younes Otarid
Format
Merged
updated
Mar 20, 2024
Separating the design hierarchy for multiple board support
!3
· created
Mar 10, 2024
by
Younes Otarid
Feature
Format
Merged
updated
Mar 10, 2024
Code tree restructuring
!2
· created
Mar 06, 2024
by
Younes Otarid
Format
Merged
updated
Mar 06, 2024
including all caribou i/o in the design + reworking constraints setting
!1
· created
Feb 19, 2024
by
Younes Otarid
Feature
Format
Merged
updated
Mar 06, 2024