Serial Memory Interface

This MR adds an interface that maps a few FPGA (or more precise: /dev/mem) registers, one for addresses and one for values. When setting a register, the register address is written to the address memory portion, the value to the second allocated memory space. The Firmware should then take care of transmitting these to wherever they need to go.

The interface has

• A memory map, and within that
• A write address register _register_address_write
• A write value register _register_value_write
• A read address register _register_address_read
• A read value register _register_value_read
• A status register _status

Transactions are triggered by setting the corresponding address register.

The procedure for writing is:

• Set _register_value_write = MYVAL
• Set _register_address_write = MYREG
• Wait for _status > 0
• Check for _status >> 1 == 0, if not throw CommunicationError
• Return

The procedure for reading is:

• Set _register_address_read = MYREG
• Wait for _status > 0
• Check for _status >> 1 == 0, if not throw CommunicationError
• Read MYVAL = _register_value_read
• Return MYVAL