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DESYER1
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Jona Dilg
requested to merge
jdilg/pearyfork:DESYER1
into
master
May 15, 2024
Overview
9
Commits
41
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14
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6
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added DESYER1 device skeleton
set up bias voltages and currents, tested on test board
added rough structure for slow-control (will be flashed out once the FPGAs have been programmed)
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