Fix metastable registers with ASYNC_REG attributes

Several metastable/intermediate registers in the slow-to-fast and fast-to- slow CDCs are optimised away by Vivado in the DTH back-end test design. This is presumably due to some clocking details in this design. The effect is that in the elaborated design the flip-flops are still present, but in the synthesised design they no longer are. This is especially clear because after that several constraints fail. I.e.,

[Vivado 12-4739] set_max_delay:No valid object(s) found for '-from [get_pins -hierarchical -filter {NAME =~ *cmp_cdc_fast_to_slow/slow_ready_reg_reg*/C}]'. ["/afs/cern.ch/work/j/jhegeman/cms_tcds2/uhal/dth_ipbb/src/tclink/firmware/constrs/core_lpgbt10G_timing.xdc":25]
[Vivado 12-4739] set_false_path:No valid object(s) found for '-from [get_pins -hierarchical -filter {NAME =~ *cmp_cdc_fast_to_slow/phase_o_reg*/C}]'. ["/afs/cern.ch/work/j/jhegeman/cms_tcds2/uhal/dth_ipbb/src/tclink/firmware/constrs/core_lpgbt10G_timing.xdc":26]
[Vivado 12-4739] set_false_path:No valid object(s) found for '-to [get_pins -hierarchical -filter {NAME =~ *cmp_cdc_fast_to_slow/phase_calib_r_reg*/D}]'. ["/afs/cern.ch/work/j/jhegeman/cms_tcds2/uhal/dth_ipbb/src/tclink/firmware/constrs/core_lpgbt10G_timing.xdc":27]
[Vivado 12-4739] set_false_path:No valid object(s) found for '-to [get_pins -hierarchical -filter {NAME =~ *cmp_cdc_fast_to_slow/phase_force_r_reg/D}]'. ["/afs/cern.ch/work/j/jhegeman/cms_tcds2/uhal/dth_ipbb/src/tclink/firmware/constrs/core_lpgbt10G_timing.xdc":28]
[Vivado 12-4739] set_false_path:No valid object(s) found for '-to [get_pins -hierarchical -filter {NAME =~ *cmp_cdc_slow_to_fast/xormeas_meta_reg/D}]'. ["/afs/cern.ch/work/j/jhegeman/cms_tcds2/uhal/dth_ipbb/src/tclink/firmware/constrs/core_lpgbt10G_timing.xdc":33]

This commit applies ASYNC_REG attributes to these registers, which prevents them from being optimised away.