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Created date
IP naming cleanup, and adding GTH cores equivalent to the master GTY cores.
!1
· created
Jul 30, 2020
by
Jeroen Hegeman
Merged
0
updated
Jul 31, 2020
Add constraints manipulations and message severity rules to allow multiple instantiations of the same transceiver IP
!2
· created
Aug 03, 2020
by
Jeroen Hegeman
Merged
1
updated
Aug 04, 2020
Adding .gitignore file to ignore some Xilinx- and Vivado-specific files
!3
· created
Aug 20, 2020
by
Jeroen Hegeman
Merged
0
updated
Aug 24, 2020
Additional records for cleaner interface
!4
· created
Aug 20, 2020
by
Jeroen Hegeman
Merged
0
updated
Aug 24, 2020
Fine tuning constraints etc
!5
· created
Aug 21, 2020
by
Jeroen Hegeman
Merged
0
updated
Aug 24, 2020
Fix metastable registers with ASYNC_REG attributes
!6
· created
Aug 22, 2020
by
Jeroen Hegeman
Merged
2
updated
Aug 24, 2020
Update all GTH IP cores
!7
· created
Aug 27, 2020
by
Jeroen Hegeman
Merged
0
updated
Aug 31, 2020
Name improvement for the MMCM IP
!8
· created
Sep 04, 2020
by
Jeroen Hegeman
Merged
0
updated
Sep 07, 2020
Improve constraints to avoid Vivado complaining about inefficient queries
!9
· created
Nov 05, 2020
by
Jeroen Hegeman
Merged
0
updated
Nov 05, 2020
MGT IP cleanup and improvement
!10
· created
Nov 20, 2020
by
Jeroen Hegeman
Merged
1
updated
Nov 27, 2020
Add __pycache__ directory to .gitignore
!12
· created
Nov 23, 2020
by
Jeroen Hegeman
Merged
0
updated
Nov 24, 2020
Some minor improvements to the modelling code
!13
· created
Nov 24, 2020
by
Jeroen Hegeman
Merged
1
updated
Nov 27, 2020
Add a tclink_channel_controller to help with initialisation, monitoring, and recovery of TCLink channels
!14
· created
Dec 15, 2020
by
Jeroen Hegeman
Merged
1
updated
Dec 16, 2020
Various small TCLink improvements
!15
· created
Jan 26, 2021
by
Jeroen Hegeman
Merged
0
updated
Jan 27, 2021
TLlink improvements 20210408
!16
· created
Apr 08, 2021
by
Jeroen Hegeman
Merged
0
updated
Apr 08, 2021
Robustify TCLink channel controller
!17
· created
Jun 28, 2021
by
Jeroen Hegeman
Merged
0
updated
Jun 29, 2021
Transform IP core info into Tcl scripts to satisfy Xilinx licensing terms
!18
· created
Jun 30, 2021
by
Jeroen Hegeman
Merged
0
updated
Jul 19, 2021
Implement a 'freeze controller phase error value for read-out' feature
!19
· created
Jul 08, 2021
by
Jeroen Hegeman
Merged
0
updated
Jul 08, 2021
Improve diagnostics for when closing the loop does not work, or for when the loop opens itself
!20
· created
Jul 13, 2021
by
Jeroen Hegeman
Merged
0
updated
Jul 14, 2021
Fix some sloppiness with signals in different clock domains
!21
· created
Jul 15, 2021
by
Jeroen Hegeman
Merged
0
updated
Jul 15, 2021
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