Add tight timing specifications to all Manifest files, plus Manifest file updating utility

Add tight timing specifications according to those provided on the hdlmake website to add -retiming to the synth_design. This is required for the 320MHz wishbone clock compilation process, and also generally a good way to improve FPGA timing i.e. in the case of ILAs.

This has been verified to compile automatically for the 320MHz upgrade, as well as standard firmware.