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Core1990_Interlaken
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status_signals
dcb9606f
·
Added missing IP to fileset and added latency count timeout reset
·
May 13, 2024
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FLX-2382_master
fde7de52
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Removed branch specific content for better compatibility with master
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Apr 23, 2024
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encoder_improvements
3ead8d56
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Commented debug signals
·
Apr 23, 2024
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master
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7fa7636f
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Merge branch 'IntelFPGA-2' into 'master'
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Apr 22, 2024
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FLX-2383_Core1990_lint
24ecbe8f
·
Import VHDL files as VHDL-2008 now
·
Apr 22, 2024
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Stale branches
InterlakenChannelBondingMux
e738439c
·
Changed data generator to Xilinx Interlaken core
·
Feb 23, 2021
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fbonini/IBUFDSGT
a3c2b138
·
remving retiming attributes
·
Jul 07, 2021
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BNL181_interlaken
d9514327
·
Support multiple reference clocks for Virtex Ultrascale+
·
Mar 02, 2022
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VersalVMK180_interlaken
cab14256
·
Update the location of bd .tcl files
·
Apr 20, 2022
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mergeVMKVCUtest
ee341676
·
Added more sources, ip-cores and made some improvements (reset)
·
Jun 28, 2022
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