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Core1990_Interlaken
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encoder_improvements
be955f69
·
Added correct block sync file to transceiver folder and also to fileset script
·
May 23, 2024
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master
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03934353
·
Merge branch 'FLX-2382_master' in 'master'
·
May 17, 2024
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status_signals
ad95afa9
·
Updated UVVM tb file (added initial values)
·
May 16, 2024
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FLX-2382_master
fde7de52
·
Removed branch specific content for better compatibility with master
·
Apr 23, 2024
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FLX-2383_Core1990_lint
24ecbe8f
·
Import VHDL files as VHDL-2008 now
·
Apr 22, 2024
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documentation
f5730628
·
Added initial documentation (early concept)
·
Apr 17, 2024
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mergeVMK180
b449e426
·
Updated GTM BD (connected more signals between base and bridge)
·
Apr 15, 2024
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IntelFPGA-2
226efbbb
·
Corrected path in generate implementation script and added datagen valid signal to STP
·
Mar 22, 2024
!30
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burst_format_fix
10ccf4ea
·
Fix for BurstMax length
·
Feb 26, 2024
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gitlab-ci-test
e98c9604
·
Added VSG tag
·
Jan 29, 2024
!27
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lti_receiver
faca01f9
·
Further improvements on providing each lane its own tx usr clk
·
Jun 09, 2023
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VCU108
95a4a133
·
Added constraints and script for VCU118
·
Mar 31, 2023
!18
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vcu_ibert
9f5150a6
·
Cleaned GTY file
·
Mar 27, 2023
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FLX-2046_Per_Channel_RXUSRCLK
caea05b2
·
Routed rx error signals to receiver_multichannel top
·
Feb 24, 2023
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VersalVMK180_global2felix
f7f9d84e
·
Update scrit to include source files for TTC
·
Aug 01, 2022
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IntelFPGA
ff810801
·
Added script to generate project and fixed some file references
·
Jun 30, 2022
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mergeVMKVCUtest
ee341676
·
Added more sources, ip-cores and made some improvements (reset)
·
Jun 28, 2022
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VersalVMK180_interlaken
cab14256
·
Update the location of bd .tcl files
·
Apr 20, 2022
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BNL181_interlaken
d9514327
·
Support multiple reference clocks for Virtex Ultrascale+
·
Mar 02, 2022
!7
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fbonini/IBUFDSGT
a3c2b138
·
remving retiming attributes
·
Jul 07, 2021
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