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Core1990_Interlaken
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InterlakenChannelBondingMux
e738439c
·
Changed data generator to Xilinx Interlaken core
·
Feb 23, 2021
fbonini/IBUFDSGT
a3c2b138
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remving retiming attributes
·
Jul 07, 2021
BNL181_interlaken
d9514327
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Support multiple reference clocks for Virtex Ultrascale+
·
Mar 02, 2022
!7
VersalVMK180_interlaken
cab14256
·
Update the location of bd .tcl files
·
Apr 20, 2022
mergeVMKVCUtest
ee341676
·
Added more sources, ip-cores and made some improvements (reset)
·
Jun 28, 2022
IntelFPGA
ff810801
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Added script to generate project and fixed some file references
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Jun 30, 2022
VersalVMK180_global2felix
f7f9d84e
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Update scrit to include source files for TTC
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Aug 01, 2022
FLX-2046_Per_Channel_RXUSRCLK
caea05b2
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Routed rx error signals to receiver_multichannel top
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Feb 24, 2023
vcu_ibert
9f5150a6
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Cleaned GTY file
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Mar 27, 2023
VCU108
95a4a133
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Added constraints and script for VCU118
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Mar 31, 2023
!18
lti_receiver
faca01f9
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Further improvements on providing each lane its own tx usr clk
·
Jun 09, 2023
gitlab-ci-test
e98c9604
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Added VSG tag
·
Jan 29, 2024
!27
burst_format_fix
10ccf4ea
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Fix for BurstMax length
·
Feb 26, 2024