Resolve FLX-1886 "Phase2/ flx182 virtual network" (!499) · Merge requests · atlas-tdaq-felix / firmware · GitLab

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Merged Frans Schreuder requested to merge phase2/FLX-1886_FLX182_virtual_network into phase2/master 1 year ago

Dec 02, 2024
- Fixed felig_top_bnl712 · 095024dd
  Frans Schreuder authored 3 months ago
  
  095024dd
- Merge remote-tracking branch 'origin/phase2/master' into phase2/FLX-1886 _FLX182_virtual_network · 529c6cbe
  Frans Schreuder authored 3 months ago
  
  529c6cbe
Oct 25, 2024
- fixed testbench · 4ce8d882
  Laura Marilena Rientsma authored 4 months ago
  
  4ce8d882
- Merge branch 'phase2/FLX-1886 _FLX182_virtual_network' of... · 26d448dd
  Laura Marilena Rientsma authored 4 months ago
  
  Merge branch 'phase2/FLX-1886_FLX182_virtual_network' of ssh://gitlab.cern.ch:7999/atlas-tdaq-felix/firmware into phase2/FLX-1886_FLX182_virtual_network
  26d448dd
- cleaned up code · 8ee95ca8
  Laura Marilena Rientsma authored 4 months ago
  
  8ee95ca8
- added initial testbench · c5db5df2
  Laura Marilena Rientsma authored 4 months ago
  
  c5db5df2
Oct 21, 2024
- Removed duplicate driver on fromhost axis clock for Interlaken · 2575145d
  Laura Marilena Rientsma authored 4 months ago
  
  2575145d
- Merge remote-tracking branch 'origin/phase2/master' into phase2/FLX-1886 _FLX182_virtual_network · a140b8b4
  Laura Marilena Rientsma authored 4 months ago
  
  a140b8b4
- changed fromHost_prog_empty to toHost and removed ILAs · 817044e9
  Laura Marilena Rientsma authored 4 months ago
  
  817044e9
Oct 10, 2024
- changed fifo in versal network device to axis packet fifos · 9582f5b7
  Laura Marilena Rientsma authored 5 months ago
  
  9582f5b7
- vsg fix · 70b1604a
  Laura Marilena Rientsma authored 5 months ago
  
  70b1604a
- Merge remote-tracking branch 'origin/phase2/master' into phase2/FLX-1886 _FLX182_virtual_network · d586bbcc
  Laura Marilena Rientsma authored 5 months ago
  
  d586bbcc
Sep 24, 2024
- inverted fifo status signals · 90440de1
  Laura Marilena Rientsma authored 5 months ago
  
  90440de1
- expanded port width after ip upgrade to Vivado 2024.1 · 4f021616
  Laura Marilena Rientsma authored 5 months ago
  
  4f021616
Sep 02, 2024
- Updated IP cores to 2024.1 · 788f8818
  Laura Marilena Rientsma authored 6 months ago
  
  788f8818
May 24, 2024
- Do a single read (edge detect) and write for Versal virtual network on BAR3, also check full/empty · 77ec6bde
  Frans Schreuder authored 9 months ago
  
  77ec6bde
- Update ip catalog after adding local ip repo · fc3546d1
  Frans Schreuder authored 9 months ago
  
  fc3546d1
- Fixed reset signals in dma_control · efafabfc
  Frans Schreuder authored 9 months ago
  
  efafabfc
- Merge remote-tracking branch 'origin/phase2/master' into phase2/FLX-1886 _FLX182_virtual_network · 490524ce
  Frans Schreuder authored 9 months ago
  
  490524ce
Jan 12, 2024
- Merge remote-tracking branch 'origin/phase2/master' into phase2/FLX-1886 _FLX182_virtual_network · 005a3636
  Frans Schreuder authored 1 year ago
  
  005a3636
Aug 10, 2023
- regenerated cips bd BNL182 · b17f96da
  Frans Schreuder authored 1 year ago
  
  b17f96da
Aug 09, 2023
- Added versal virtual network device to FLX182 cips block design · 2c37147d
  Frans Schreuder authored 1 year ago
  
  2c37147d
- Added IP core for versal virtual network device for FLX182 · b025fe4d
  Frans Schreuder authored 1 year ago
  
  b025fe4d
- Validated .bd files · b9103bdf
  Frans Schreuder authored 1 year ago
  
  b9103bdf
- Changed memory for virtual network to BRAM to cross clock domains between PCIe and PS · 7313b31d
  Frans Schreuder authored 1 year ago
  
  7313b31d
- Added BAR3 to Versal PCIe endpoint 0 ( FLX182) and added block ram to CIPS · 25d26fd5
  Frans Schreuder authored 1 year ago
  
  25d26fd5
- Implemented virtual network device between Wupper endpoint 0 and Versal Processing system · 82c6ab78
  Frans Schreuder authored 1 year ago
  
  82c6ab78