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Updated date
Replaced \= in comment by /= to aviod unknown escape character in c...
!434
· created
Feb 17, 2023
by
Frans Schreuder
Merged
0
updated
Feb 18, 2023
Combined registers from phase2/master_FLX-2106_64b66bsimu and...
!432
· created
Feb 15, 2023
by
Frans Schreuder
Merged
2
updated
Feb 17, 2023
pixel decoding aclk at 160 MHz to avoid data losses
!431
· created
Feb 14, 2023
by
Marco Trovato
Merged
0
updated
Feb 15, 2023
renaming LTITTC R/W colliding registers
!429
· created
Feb 08, 2023
by
Marco Trovato
Merged
0
updated
Feb 15, 2023
FLX-2115 BUFG
!430
· created
Feb 10, 2023
by
Ricardo Luz
Merged
0
updated
Feb 11, 2023
LTITTC Link Wrapper moved from link wrapper to LTITTC Wrapper. Same MGT bank...
!420
· created
Jan 19, 2023
by
Frans Schreuder
Merged
10
updated
Feb 06, 2023
Use Vivado 2021.2 for VCU128 ci script
!426
· created
Jan 30, 2023
by
Frans Schreuder
Merged
0
updated
Feb 01, 2023
Initial implementation of discarding Tohost data on lower priority DMA channels, see FLX-2082
!415
· created
Dec 19, 2022
by
Frans Schreuder
Merged
0
updated
Jan 31, 2023
Upgraded VMK180 block designs to Vivado 2022.2 (non engineering sample)
!425
· created
Jan 27, 2023
by
Frans Schreuder
Merged
0
updated
Jan 31, 2023
Set default NUMBER_OF_DESCRIPTORS to 6 (5 tohost + 1 fromhost), see FLX-2098
!422
· created
Jan 19, 2023
by
Frans Schreuder
Merged
0
updated
Jan 27, 2023
Resolve FLX-2087 "FELIG L1A reset"
!424
· created
Jan 26, 2023
by
Ricardo Luz
master
Merged
0
updated
Jan 27, 2023
Added an initial .bd file for BNL182 CPM, and inputs/outputs for Wupper.
!412
· created
Dec 06, 2022
by
Frans Schreuder
Merged
0
updated
Jan 20, 2023
Implemented RC/RQ Frame Straddle for PCIe Gen3 and Gen4
!408
· created
Nov 15, 2022
by
Frans Schreuder
Merged
0
updated
Jan 20, 2023
Deinit submodules after simulation and publish script
!421
· created
Jan 19, 2023
by
Frans Schreuder
Merged
0
updated
Jan 20, 2023
Resolve FLX-2072 "Emptysuppress"
!416
· created
Dec 21, 2022
by
Frans Schreuder
master
Merged
0
updated
Jan 19, 2023
phase2/strips_FLX-2054
!413
· created
Dec 06, 2022
by
Elena Zhivun
Merged
0
updated
Dec 19, 2022
Fix truncation mechanism in ByteToAxiStream (FLX-1979), and a small fix...
!414
· created
Dec 14, 2022
by
Frans Schreuder
Merged
0
updated
Dec 19, 2022
FLX-2069: Added L0A bit in TTC_out_type, for Phase I a delayed version of L1A
!410
· created
Nov 29, 2022
by
Frans Schreuder
Merged
0
updated
Dec 06, 2022
release 4.12 to master
!411
· created
Nov 30, 2022
by
Frans Schreuder
master
Merged
0
updated
Dec 06, 2022
FLX-2069: Added TTC_L0A_DELAY register, implemented L1A delay (0-63 BC cycles)...
!409
· created
Nov 29, 2022
by
Frans Schreuder
master
Merged
0
updated
Dec 06, 2022
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