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Created date
Deinit submodules after simulation and publish script
!421
· created
Jan 19, 2023
by
Frans Schreuder
Merged
0
updated
Jan 20, 2023
LTITTC Link Wrapper moved from link wrapper to LTITTC Wrapper. Same MGT bank...
!420
· created
Jan 19, 2023
by
Frans Schreuder
Merged
10
updated
Feb 06, 2023
Draft: New tx phase alignment feature added ;
!419
· created
Jan 19, 2023
by
Frans Schreuder
Closed
0
updated
Feb 22, 2023
Updated core1990 to master
!418
· created
Jan 17, 2023
by
Frans Schreuder
Closed
0
updated
Jan 17, 2023
Changed git submodules to not follow the modules master, but rather stay as committed in firmware
!417
· created
Jan 16, 2023
by
Frans Schreuder
phase2/FLX-1936_FLX182_Support
Closed
0
updated
Jan 17, 2023
Resolve FLX-2072 "Emptysuppress"
!416
· created
Dec 21, 2022
by
Frans Schreuder
master
Merged
0
updated
Jan 19, 2023
Initial implementation of discarding Tohost data on lower priority DMA channels, see FLX-2082
!415
· created
Dec 19, 2022
by
Frans Schreuder
Merged
0
updated
Jan 31, 2023
Fix truncation mechanism in ByteToAxiStream (FLX-1979), and a small fix...
!414
· created
Dec 14, 2022
by
Frans Schreuder
Merged
0
updated
Dec 19, 2022
phase2/strips_FLX-2054
!413
· created
Dec 06, 2022
by
Elena Zhivun
Merged
0
updated
Dec 19, 2022
Added an initial .bd file for BNL182 CPM, and inputs/outputs for Wupper.
!412
· created
Dec 06, 2022
by
Frans Schreuder
Merged
0
updated
Jan 20, 2023
release 4.12 to master
!411
· created
Nov 30, 2022
by
Frans Schreuder
master
Merged
0
updated
Dec 06, 2022
FLX-2069: Added L0A bit in TTC_out_type, for Phase I a delayed version of L1A
!410
· created
Nov 29, 2022
by
Frans Schreuder
Merged
0
updated
Dec 06, 2022
FLX-2069: Added TTC_L0A_DELAY register, implemented L1A delay (0-63 BC cycles)...
!409
· created
Nov 29, 2022
by
Frans Schreuder
master
Merged
0
updated
Dec 06, 2022
Implemented RC/RQ Frame Straddle for PCIe Gen3 and Gen4
!408
· created
Nov 15, 2022
by
Frans Schreuder
Merged
0
updated
Jan 20, 2023
Draft: BCMPrime (BCM') intilisation to felix FW
!407
· created
Nov 04, 2022
by
Ismet Siral
Closed
1
updated
Jan 20, 2023
Fix LPGBT alignment for FEC12
!406
· created
Nov 01, 2022
by
Marco Trovato
Merged
1
updated
Nov 04, 2022
Implement VHDL Style Guide (FLX-1587)
!405
· created
Oct 25, 2022
by
Frans Schreuder
Merged
0
updated
Nov 14, 2022
Fixed undriven sta_headerFlag_out in lpgbtfpga_uplink, which prevents FEC12...
!404
· created
Oct 24, 2022
by
Frans Schreuder
Merged
0
updated
Oct 26, 2022
Close FLX-2019: Include scripts and instructions for simulation with modelsim
!403
· created
Oct 07, 2022
by
Marco Trovato
Merged
0
updated
Oct 08, 2022
Draft: phase2/FLX-1776_HGTD_Decoding_plus_FLX-1979
!402
· created
Sep 29, 2022
by
Frans Schreuder
Closed
1
updated
Apr 26, 2023
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