New BMBO DCT data format

A new data format is proposed for data to be transmitted both from BMBO-DCT and from BI-DCT to SL to reduce BMBO-DCT FPGA and SL FPGA resource occupancy. For the BI-DCT the Artix-7 FPGA has been replaced with a Kintex-7 to accomodate the logic to reorder the BI hit data for few BCs and perform the virtual phi computation.

The new BMBO-DCT data format is the following:
1 bit eta or phi strip ('0'-> is eta strip; '1'-> is phi strip) + 7 bit strip index (0-63 for eta, 0-79 for phi strips) + 10 bit BCID + 5 bit rising time layer 0 + 5 bit rising time layer 1
The falling time is not transmitted anymore. If needed it can be transmitted to SL readout with low priority.

The new BI-DCT data format is made of two consecutive 28-bit words representing the same hit as follows:

• 1st word: 2 bit word ID ("01") + 8 bit BCID + 8 bit strip ID + 8 bit virtual phi + 2 bit right falling time (MSB)
• 2nd word: 2 bit word ID ("10") + 8 bit left rising time + 6 bit left falling time (MSB) + 8 bit right rising time + 4 bit right falling time

BMBO DCT firmware:

• Added logic to read and write configuration registers
• Adapt firmware to new data format. With new data format, BMBO DCT FPGA occupancy almost halved

BI DCT firmware:

• Move to 288 front-end signals
• Replace Artix-7 FPGA with Kintex-7
• Added logic to read and write configuration registers
• Added logic to reorder BI data for few (4) BCs
• Added logic to perform the virtual phi computation (subtraction of left and right time measurements)
• Adapt firmware to new data format.

SL firmware:

• Adapt BMBO data handler (SLR1 and SLR2) to new BMBO DCT data format (almost no improvement in SL FPGA occupancy)
• Adapt BI data handler (SLR0) to new BI DCT data format (BI virtual phi computation removed, great improvement in SLR0 occupancy)
• Fix all critical warnings pointed out by synthesis and implementation