Merge branch 'IDTIDE_outputs' into 'main'

Move list of IDTIDE excluded auxdata in IDTIDE config

See merge request !68340

InnerDetector/InDetConfig/python/ITkTrackOutputConfig.py

-# Copyright (C) 2002-2023 CERN for the benefit of the ATLAS collaboration
+# Copyright (C) 2002-2024 CERN for the benefit of the ATLAS collaboration
 
 from AthenaConfiguration.ComponentAccumulator import ComponentAccumulator
 from InDetConfig.InDetTrackOutputConfig import FTAG_AUXDATA
@@ -20,9 +20,10 @@ def ITkTrackRecoOutputCfg(flags, extensions_list=None):
     # exclude TTVA decorations
     excludedAuxData += '.-TTVA_AMVFVertices.-TTVA_AMVFWeights'
 
-    # exclude IDTIDE/IDTRKVALID decorations
-    excludedAuxData += ('.-TrkBLX.-TrkBLY.-TrkBLZ.-TrkIBLX.-TrkIBLY.-TrkIBLZ'
-                        '.-TrkL1X.-TrkL1Y.-TrkL1Z.-TrkL2X.-TrkL2Y.-TrkL2Z')
+    # exclude IDTIDE decorations
+    from DerivationFrameworkInDet.IDTIDE import IDTIDE_AOD_EXCLUDED_AUXDATA
+    excludedAuxData += '.-'.join([''] + IDTIDE_AOD_EXCLUDED_AUXDATA)
+
     if not flags.Tracking.writeExtendedSi_PRDInfo:
         excludedAuxData += '.-msosLink'
 

InnerDetector/InDetConfig/python/InDetTrackOutputConfig.py

-# Copyright (C) 2002-2023 CERN for the benefit of the ATLAS collaboration
+# Copyright (C) 2002-2024 CERN for the benefit of the ATLAS collaboration
 
 from AthenaConfiguration.ComponentAccumulator import ComponentAccumulator
 
@@ -41,26 +41,14 @@ def InDetTrackRecoOutputCfg(flags, extensions_list=None):
     # exclude TTVA decorations
     excludedAuxData += '.-TTVA_AMVFVertices.-TTVA_AMVFWeights'
 
-    # exclude IDTIDE/IDTRKVALID decorations
-    excludedAuxData += ('.-TrkBLX.-TrkBLY.-TrkBLZ.-TrkIBLX.-TrkIBLY.-TrkIBLZ'
-                        '.-TrkL1X.-TrkL1Y.-TrkL1Z.-TrkL2X.-TrkL2Y.-TrkL2Z')
+    # exclude IDTIDE decorations
+    from DerivationFrameworkInDet.IDTIDE import IDTIDE_AOD_EXCLUDED_AUXDATA
+    excludedAuxData += '.-'.join([''] + IDTIDE_AOD_EXCLUDED_AUXDATA)
+
     if not (flags.Tracking.writeExtendedSi_PRDInfo or
             flags.Tracking.writeExtendedTRT_PRDInfo):
         excludedAuxData += '.-msosLink'
 
-    # exclude IDTIDE decorations
-    excludedAuxData += (
-        '.-IDTIDE1_biased_PVd0Sigma.-IDTIDE1_biased_PVz0Sigma'
-        '.-IDTIDE1_biased_PVz0SigmaSinTheta.-IDTIDE1_biased_d0'
-        '.-IDTIDE1_biased_d0Sigma'
-        '.-IDTIDE1_biased_z0.-IDTIDE1_biased_z0Sigma'
-        '.-IDTIDE1_biased_z0SigmaSinTheta.-IDTIDE1_biased_z0SinTheta'
-        '.-IDTIDE1_unbiased_PVd0Sigma.-IDTIDE1_unbiased_PVz0Sigma'
-        '.-IDTIDE1_unbiased_PVz0SigmaSinTheta'
-        '.-IDTIDE1_unbiased_d0.-IDTIDE1_unbiased_d0Sigma'
-        '.-IDTIDE1_unbiased_z0.-IDTIDE1_unbiased_z0Sigma'
-        '.-IDTIDE1_unbiased_z0SigmaSinTheta.-IDTIDE1_unbiased_z0SinTheta')
-
     ##### ESD #####
     # Save full and zero-suppressed BCM rdos
     # (the latter is needed to allow writting to AOD and the former will hopefully be removed in future):

PhysicsAnalysis/DerivationFramework/DerivationFrameworkInDet/python/IDTIDE.py

-# Copyright (C) 2002-2023 CERN for the benefit of the ATLAS collaboration
+# Copyright (C) 2002-2024 CERN for the benefit of the ATLAS collaboration
 #!/usr/bin/env python
 # ====================================================================
 # IDTIDE.py
@@ -17,6 +17,23 @@ from AthenaConfiguration.Enums import MetadataCategory
 from AthenaCommon.CFElements import seqAND,_append
 from AthenaCommon.Constants import INFO
 
+# IDTIDE Variables to be excluded from AOD
+IDTIDE_AOD_EXCLUDED_AUXDATA = [
+    'TrkBLX', 'TrkBLY', 'TrkBLZ', 'TrkIBLX', 'TrkIBLY', 'TrkIBLZ',
+    'TrkL1X', 'TrkL1Y', 'TrkL1Z', 'TrkL2X', 'TrkL2Y', 'TrkL2Z',
+    'IDTIDE_biased_PVd0Sigma', 'IDTIDE_biased_PVz0Sigma',
+    'IDTIDE_biased_PVz0SigmaSinTheta',
+    'IDTIDE_biased_d0', 'IDTIDE_biased_d0Sigma',
+    'IDTIDE_biased_z0', 'IDTIDE_biased_z0Sigma',
+    'IDTIDE_biased_z0SigmaSinTheta', 'IDTIDE_biased_z0SinTheta',
+    'IDTIDE_unbiased_PVd0Sigma', 'IDTIDE_unbiased_PVz0Sigma',
+    'IDTIDE_unbiased_PVz0SigmaSinTheta',
+    'IDTIDE_unbiased_d0', 'IDTIDE_unbiased_d0Sigma',
+    'IDTIDE_unbiased_z0', 'IDTIDE_unbiased_z0Sigma',
+    'IDTIDE_unbiased_z0SigmaSinTheta', 'IDTIDE_unbiased_z0SinTheta'
+    ]
+
+
 # Main algorithm config
 def parSeq(name, subs=[]):
     """ parallel sequencer """