diff --git a/Event/xAOD/xAODTrigger/Root/MuonRoI_v1.cxx b/Event/xAOD/xAODTrigger/Root/MuonRoI_v1.cxx index 42885c09d3506e609348e5614f55179d58ff0e58..650bb8495bc58cf1c154aa9eff5bca5f2b577250 100644 --- a/Event/xAOD/xAODTrigger/Root/MuonRoI_v1.cxx +++ b/Event/xAOD/xAODTrigger/Root/MuonRoI_v1.cxx @@ -229,7 +229,7 @@ namespace xAOD{ /// bool MuonRoI_v1::getPhiOverlap() const { if (isRun3()) { - if (getSource() == Barrel) return (roiWord() >> RUN3_BARREL_OL_SHIFT) & RUN3_BARREL_OL_MASK; + if (getSource() == Barrel) return (roiWord() >> RUN3_CAND_WORD_CANDFLAGS_BA_PHIOVERLAP_SHIFT) & RUN3_CAND_WORD_CANDFLAGS_BA_PHIOVERLAP_MASK; else return false; } else { if (getSource() == Barrel) return (roiWord() >> BARREL_OL_SHIFT) & BARREL_PHI_OL_MASK; diff --git a/Trigger/TrigT1/TrigT1MuctpiBits/TrigT1MuctpiBits/MuCTPI_Bits.h b/Trigger/TrigT1/TrigT1MuctpiBits/TrigT1MuctpiBits/MuCTPI_Bits.h index 5b4315900b5a8d831e4cb9546d832c63d71d2e1a..3b1878ff61454d73b29b39584f40d2d339b83947 100755 --- a/Trigger/TrigT1/TrigT1MuctpiBits/TrigT1MuctpiBits/MuCTPI_Bits.h +++ b/Trigger/TrigT1/TrigT1MuctpiBits/TrigT1MuctpiBits/MuCTPI_Bits.h @@ -47,12 +47,10 @@ namespace LVL1::MuCTPIBits { //===== Need to double check that the run3 positions are correct for the OL flags===== /// Mask for extracting the overlap bits for barrel candidates from the data words - static constexpr uint32_t RUN3_BARREL_OL_MASK = 0x1; // only the phi ovl is used in the run3 format static constexpr uint32_t BARREL_OL_MASK = 0x3; static constexpr uint32_t BARREL_PHI_OL_MASK = 0x1; static constexpr uint32_t BARREL_ETA_OL_MASK = 0x2; /// Position of the overlap bits in barrel data words - static constexpr uint32_t RUN3_BARREL_OL_SHIFT = 12; // this is now part of the 4 "candidate flags" bits static constexpr uint32_t BARREL_OL_SHIFT = 9; /// Mask for extracting the overlap bits for endcap candidates from the data words static constexpr uint32_t ENDCAP_OL_MASK = 0x1; diff --git a/Trigger/TrigT1/TrigT1MuctpiPhase1/src/TriggerProcessor.cxx b/Trigger/TrigT1/TrigT1MuctpiPhase1/src/TriggerProcessor.cxx index 86c5c020b67483d4d74cc5e78b78d0e1ddbad432..57c73f4735e2886c3105eb6738b153937aa35fee 100644 --- a/Trigger/TrigT1/TrigT1MuctpiPhase1/src/TriggerProcessor.cxx +++ b/Trigger/TrigT1/TrigT1MuctpiPhase1/src/TriggerProcessor.cxx @@ -107,7 +107,7 @@ namespace LVL1MUCTPIPHASE1 { //CANDIDIATE FLAGS if (isys == 0) { - daq_word |= (sectorData->ovl(icand) & LVL1::MuCTPIBits::RUN3_BARREL_OL_MASK) << LVL1::MuCTPIBits::RUN3_BARREL_OL_SHIFT; + daq_word |= (sectorData->ovl(icand) & LVL1::MuCTPIBits::RUN3_CAND_WORD_CANDFLAGS_BA_PHIOVERLAP_MASK) << LVL1::MuCTPIBits::RUN3_CAND_WORD_CANDFLAGS_BA_PHIOVERLAP_SHIFT; daq_word |= (sectorData->is2candidates(icand) & LVL1::MuCTPIBits::ROI_OVERFLOW_MASK) << LVL1::MuCTPIBits::RUN3_ROI_OVERFLOW_SHIFT; } else diff --git a/Trigger/TrigValidation/TrigAnalysisTest/share/ref_RDOtoRDOTrig_v1Dev_build.ref b/Trigger/TrigValidation/TrigAnalysisTest/share/ref_RDOtoRDOTrig_v1Dev_build.ref index 47f246c465bc2d27286b4e6698e19c69817de0bf..79779c6518e9fc50f8ddaa7de277e3b6b299d927 100644 --- a/Trigger/TrigValidation/TrigAnalysisTest/share/ref_RDOtoRDOTrig_v1Dev_build.ref +++ b/Trigger/TrigValidation/TrigAnalysisTest/share/ref_RDOtoRDOTrig_v1Dev_build.ref @@ -12920,26 +12920,23 @@ HLT_mu10_l2mt_L1MU10BO: HLT_mu10_l2mt_L1MU10BOM: eventCount: 1 stepCounts: - 0: 2 + 0: 1 1: 1 2: 1 3: 1 stepFeatures: - 0: 3 + 0: 1 1: 1 2: 1 3: 1 HLT_mu10_l2mt_mu4_l2mt_bJpsimumu_L1MU10BOM: eventCount: 0 - stepCounts: - 0: 1 stepFeatures: - 0: 6 - 1: 2 + 0: 2 HLT_mu10_l2mt_mu4_l2mt_bJpsimumu_L1MU12BOM: eventCount: 0 stepFeatures: - 0: 4 + 0: 2 HLT_mu10_mu6_probe_PhysicsTLA_L1MU8F: eventCount: 3 stepCounts: @@ -14127,7 +14124,7 @@ HLT_mu24_ivarmedium_j20_pf_ftf_L1MU18VFCH: 5: 4 6: 29 HLT_mu24_ivarmedium_mu10_ivarmedium_probe_L1MU14FCH: - eventCount: 0 + eventCount: 1 stepCounts: 0: 5 1: 5 @@ -14138,6 +14135,7 @@ HLT_mu24_ivarmedium_mu10_ivarmedium_probe_L1MU14FCH: 6: 1 7: 1 8: 1 + 9: 1 stepFeatures: 0: 6 1: 5 @@ -15090,7 +15088,7 @@ HLT_mu26_ivarmedium_j20_pf_ftf_L1MU18VFCH: 5: 4 6: 29 HLT_mu26_ivarmedium_mu10_ivarmedium_probe_L1MU14FCH: - eventCount: 0 + eventCount: 1 stepCounts: 0: 6 1: 5 @@ -15101,6 +15099,7 @@ HLT_mu26_ivarmedium_mu10_ivarmedium_probe_L1MU14FCH: 6: 1 7: 1 8: 1 + 9: 1 stepFeatures: 0: 7 1: 5 @@ -15113,7 +15112,7 @@ HLT_mu26_ivarmedium_mu10_ivarmedium_probe_L1MU14FCH: 8: 2 9: 1 HLT_mu26_ivarmedium_mu10_ivarmedium_probe_L1MU18VFCH: - eventCount: 0 + eventCount: 1 stepCounts: 0: 6 1: 5 @@ -15124,6 +15123,7 @@ HLT_mu26_ivarmedium_mu10_ivarmedium_probe_L1MU18VFCH: 6: 1 7: 1 8: 1 + 9: 1 stepFeatures: 0: 7 1: 5