diff --git a/Trigger/TrigT1/L1CaloFEX/L1CaloFEXSim/share/L1CaloFEXSimCfg_R2data.ref b/Trigger/TrigT1/L1CaloFEX/L1CaloFEXSim/share/L1CaloFEXSimCfg_R2data.ref
index d2abcddba8d0c7a502f88b442c6af3dd55df4d07..c6f71ea8f239acb000e9ab63eb255e841dfce889 100644
--- a/Trigger/TrigT1/L1CaloFEX/L1CaloFEXSim/share/L1CaloFEXSimCfg_R2data.ref
+++ b/Trigger/TrigT1/L1CaloFEX/L1CaloFEXSim/share/L1CaloFEXSimCfg_R2data.ref
@@ -44,6 +44,7 @@ ApplicationMgr                                               0 SUCCESS
 ApplicationMgr                                               0 SUCCESS                     CaloBCIDLumiCondAlg/CaloBCIDLumiCondAlg
 ApplicationMgr                                               0 SUCCESS                     CaloNoiseCondAlg/Calo_electronicNoiseAlg
 ApplicationMgr                                               0 SUCCESS                     CaloNoiseSigmaDiffCondAlg/CaloNoiseSigmaDiffCondAlg
+ApplicationMgr                                               0 SUCCESS                     CaloSuperCellAlignCondAlg/CaloSuperCellAlignCondAlg
 ApplicationMgr                                               0 SUCCESS           AthSequencer/AthEndSeq
 ApplicationMgr                                               0 SUCCESS                AthIncFirerAlg/EndIncFiringAlg
 ApplicationMgr                                               0 SUCCESS                IncidentProcAlg/IncidentProcAlg2
diff --git a/Trigger/TrigT1/TrigT1CaloFexPerf/python/EmulationConfig.py b/Trigger/TrigT1/TrigT1CaloFexPerf/python/EmulationConfig.py
index b768905deea7d29da4e75e1a56dffb558a066a85..c45f6fa05d7633ebeb0645d5dbfef581284a5c79 100644
--- a/Trigger/TrigT1/TrigT1CaloFexPerf/python/EmulationConfig.py
+++ b/Trigger/TrigT1/TrigT1CaloFexPerf/python/EmulationConfig.py
@@ -84,4 +84,7 @@ def emulateSC_Cfg(flags, CellsIn="SeedLessFS", SCOut="EmulatedSCell"):
     #The default input to LARSuperCellBCIDEmAlg (which applies the BCID correction) is the same: SCellContainer
         acc.merge(LArSuperCellBCIDEmAlgCfg(flags, **larSCargs))
 
+    # Given this function emulates supercells, we should also configure the supercell alignment Cond alg
+    acc.addCondAlgo(CompFactory.CaloSuperCellAlignCondAlg())
+
     return acc