Detected bugs in a pulser group (WREN gateware)
It was noticed that when a pulse period is equal to 32 and a pulse width is between 24 and 32 (clock frequency was 1GHz), a wrong number of pulses is generated with wrong pulse period and width. For example, for this pulser configuration the number of generated pulses is two instead of three, pulse period is 64 instead of 32, and pulse width is 28 instead of 29.
- repeat mode: 0
- start input: 31
- stop input: 31
- clock input: 31
- pulser output: 6
- initial delay [clk cycl]: 0
- pulse width [ns]: 29
- pulse period [clk cycl]: 32
- number of pulses: 3
- time [s]: 293
- time [ns]: 4094
Instructions for running the testbench are in README.md.
UPDATE: The same configurations are repeated on the real board. The screenshots from a scope are added for each configuration. Some configurations work correctly, while for others the same bug as in the simulation is confirmed.
The screenshot for the configuration above and the command used in the wrenrx-get program to program a pulser:
pulser-program 1 -start no -stop no -clock no -width 29 -period 32 -idelay 0 -n 3 -r 0 -sec 1 -ns 0