Question : Use of record types for VHDL side code generation
Would it be possible / interesting to set an option to use vhdl records type for the bus in / bus out signals ? I have been using the t_axi4_lite_master_out_32 and t_axi4_lite_master_in_32 for the axi4lite buses, from the axi4_pkg by CO.
Things could be more complicated for the cern-be-vme-(err)-16/32 buses because the creation of a generic record is not possible before VHDL 2008 and theses buses are mostly used in legacy designs where the tools do not fully comply with VHDL2008, but creating a package with the type definition in a separate VHDL file could solve the problem.