From 533be98034df43508177a25d375b5ea193dd993c Mon Sep 17 00:00:00 2001
From: Karol Krizka <kkrizka@gmail.com>
Date: Tue, 26 Apr 2022 15:28:32 -0700
Subject: [PATCH 01/16] Add amacv2_scope for monitoring AMAC output for
 changes.

---
 .gitlab-ci.yml                                |   7 +-
 README.md                                     |   1 +
 Top/amacv2_scope_ip/hog.conf                  |  17 +
 Top/amacv2_scope_ip/list/amacv2_scope.src     |   1 +
 Top/amacv2_scope_ip/post-creation.tcl         |   2 +
 firmware/bd/ActiveBoard.tcl                   |  25 +-
 .../amacv2_scope/hdl/amacv2_scope_top.vhd     | 368 +++++++++++++
 .../hdl/generic_read_registers_axi.vhd        | 516 ++++++++++++++++++
 .../ip_repo/amacv2_scope/hdl/simplescope.vhd  |  51 ++
 .../amacv2_scope/list/amacv2_scope.src        |   4 +
 .../device-tree/files/system-user.dtsi        |   3 +
 11 files changed, 993 insertions(+), 2 deletions(-)
 create mode 100644 Top/amacv2_scope_ip/hog.conf
 create mode 100644 Top/amacv2_scope_ip/list/amacv2_scope.src
 create mode 100644 Top/amacv2_scope_ip/post-creation.tcl
 create mode 100644 firmware/ip_repo/amacv2_scope/hdl/amacv2_scope_top.vhd
 create mode 100644 firmware/ip_repo/amacv2_scope/hdl/generic_read_registers_axi.vhd
 create mode 100644 firmware/ip_repo/amacv2_scope/hdl/simplescope.vhd
 create mode 100644 firmware/ip_repo/amacv2_scope/list/amacv2_scope.src

diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml
index 15ec58f1..739d3505 100644
--- a/.gitlab-ci.yml
+++ b/.gitlab-ci.yml
@@ -47,6 +47,11 @@ package_ip:amacv2_digital_io_ip:
   variables:
     PACKAGE_NAME: amacv2_digital_io_ip
 
+package_ip:amacv2_scope_ip:
+  extends: .base:package_ip
+  variables:
+    PACKAGE_NAME: amacv2_scope_ip
+
 package_ip:freqmeas_ip:
   extends: .base:package_ip
   variables:
@@ -58,7 +63,7 @@ generate_project:microzed_7020:
   variables:
     extends: .vars
     PROJECT_NAME: microzed_7020
-  needs: ["package_ip:endeavour_ip", "package_ip:amacv2_digital_io_ip", "package_ip:freqmeas_ip"]
+  needs: ["package_ip:endeavour_ip", "package_ip:amacv2_digital_io_ip", "package_ip:amacv2_scope_ip", "package_ip:freqmeas_ip"]
 
 .base:petalinux:
   <<: *only-default
diff --git a/README.md b/README.md
index 52d59a9e..8d3f6342 100644
--- a/README.md
+++ b/README.md
@@ -39,6 +39,7 @@ The following commands will package our custom IP blocks.
 ```shell
 ./Hog/CreateProject.sh endeavour_ip
 ./Hog/CreateProject.sh amacv2_digital_io_ip
+./Hog/CreateProject.sh amacv2_scope_ip
 ./Hog/CreateProject.sh freqmeas_ip
 ```
 
diff --git a/Top/amacv2_scope_ip/hog.conf b/Top/amacv2_scope_ip/hog.conf
new file mode 100644
index 00000000..5b615aaf
--- /dev/null
+++ b/Top/amacv2_scope_ip/hog.conf
@@ -0,0 +1,17 @@
+#vivado
+[main]
+PART = xc7z020clg400-1
+BOARD_PART = avnet.com:microzed_7020:part0:1.3
+
+[synth_1]
+STRATEGY = "Vivado Synthesis Defaults"
+FLOW = "Vivado Synthesis 2021"
+
+[impl_1]
+STRATEGY = "Vivado Implementation Defaults"
+FLOW = "Vivado Implementation 2021"
+
+[hog]
+ALLOW_FAIL_ON_GIT = False
+ALLOW_FAIL_ON_LIST = False
+ALLOW_FAIL_ON_CONF = False
diff --git a/Top/amacv2_scope_ip/list/amacv2_scope.src b/Top/amacv2_scope_ip/list/amacv2_scope.src
new file mode 100644
index 00000000..5898ebea
--- /dev/null
+++ b/Top/amacv2_scope_ip/list/amacv2_scope.src
@@ -0,0 +1 @@
+firmware/ip_repo/amacv2_scope/list/amacv2_scope.src
\ No newline at end of file
diff --git a/Top/amacv2_scope_ip/post-creation.tcl b/Top/amacv2_scope_ip/post-creation.tcl
new file mode 100644
index 00000000..df833893
--- /dev/null
+++ b/Top/amacv2_scope_ip/post-creation.tcl
@@ -0,0 +1,2 @@
+source ${repo_path}/firmware/tcl/build_ip.tcl
+build_zynq_ip amacv2_scope "AMAC Testbench scoping of AMAC outputs" "Scope AMAC outputs"
diff --git a/firmware/bd/ActiveBoard.tcl b/firmware/bd/ActiveBoard.tcl
index 726a7bd3..1216247b 100644
--- a/firmware/bd/ActiveBoard.tcl
+++ b/firmware/bd/ActiveBoard.tcl
@@ -65,7 +65,7 @@ proc create_root_design { parentCell } {
     # AXI
     set axi_interconnect_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_interconnect_0 ]
     set_property -dict [ list \
-    			     CONFIG.NUM_MI 4 \
+    			     CONFIG.NUM_MI 5 \
     			    ] $axi_interconnect_0
 
     connect_bd_intf_net [get_bd_intf_pins processing_system7_0/M_AXI_GP0] -boundary_type upper [get_bd_intf_pins axi_interconnect_0/S00_AXI]
@@ -199,6 +199,29 @@ proc create_root_design { parentCell } {
 
     assign_bd_address -offset 0x41C20000 -range 0x00010000 -target_address_space [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs ${axi_freqmeas_0}/s00_axi/reg0] -force
 
+    #
+    # AMACv2 Output Scope
+
+    # IP
+    set axi_amacv2_scope_0 [create_bd_cell -type ip -vlnv lbl.gov:pbv3:amacv2_scope:1.0 axi_amacv2_scope_0]
+
+    # Ports
+    set amac_outputs [list LDx0en LDx1en LDx2en LDy0en LDy1en LDy2en HrstBx HrstBy LAM GPO DCDCadj DCDCen OFout RO_PG_O]
+
+    foreach amac_output ${amac_outputs} {
+	# create_bd_port -dir I ${amac_output} # Already done as part of the IO controller
+	connect_bd_net [get_bd_ports ${amac_output}] [get_bd_pins ${axi_amacv2_scope_0}/${amac_output}]
+    }
+
+    # AXI
+    connect_bd_intf_net [get_bd_intf_pins ${axi_amacv2_scope_0}/s00_axi] [get_bd_intf_pins axi_interconnect_0/M04_AXI]
+
+    apply_bd_automation -rule xilinx.com:bd_rule:clkrst \
+        -config { Clk {/processing_system7_0/FCLK_CLK0 (100 MHz)} Freq {100} Ref_Clk0 {} Ref_Clk1 {} Ref_Clk2 {}} \
+        [get_bd_pins axi_interconnect_0/M04_ACLK]
+
+    assign_bd_address -offset 0x41C30000 -range 0x00010000 -target_address_space [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs ${axi_amacv2_scope_0}/s00_axi/reg0] -force
+
     #
     # Cleanup
 
diff --git a/firmware/ip_repo/amacv2_scope/hdl/amacv2_scope_top.vhd b/firmware/ip_repo/amacv2_scope/hdl/amacv2_scope_top.vhd
new file mode 100644
index 00000000..2cc34938
--- /dev/null
+++ b/firmware/ip_repo/amacv2_scope/hdl/amacv2_scope_top.vhd
@@ -0,0 +1,368 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity amacv2_scope is
+  generic (
+    -- Users to add parameters here
+
+    -- User parameters ends
+    -- Do not modify the parameters beyond this line
+
+    -- Parameters of Axi Slave Bus Interface S00_AXI
+    C_S00_AXI_DATA_WIDTH	: integer	:= 32;
+    C_S00_AXI_ADDR_WIDTH	: integer	:= 7
+    );
+  port (
+    -- Users to add ports here
+
+    -- AMAC outputs
+    LDx0en  : in std_logic;
+    LDy0en  : in std_logic;
+    LDx1en  : in std_logic;
+    LDy1en  : in std_logic;
+    LDx2en  : in std_logic;
+    LDy2en  : in std_logic;
+    HrstBx  : in std_logic;
+    HrstBy  : in std_logic;
+    LAM     : in std_logic;
+    GPO     : in std_logic;
+    DCDCadj : in std_logic;
+    DCDCEn  : in std_logic;
+    Ofout   : in std_logic;
+    RO_PG_O : in std_logic;
+
+    -- Do not modify the ports beyond this line
+
+
+    -- Ports of Axi Slave Bus Interface S00_AXI
+    s00_axi_aclk	: in std_logic;
+    s00_axi_aresetn	: in std_logic;
+    s00_axi_awaddr	: in std_logic_vector(C_S00_AXI_ADDR_WIDTH-1 downto 0);
+    s00_axi_awprot	: in std_logic_vector(2 downto 0);
+    s00_axi_awvalid	: in std_logic;
+    s00_axi_awready	: out std_logic;
+    s00_axi_wdata	: in std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0);
+    s00_axi_wstrb	: in std_logic_vector((C_S00_AXI_DATA_WIDTH/8)-1 downto 0);
+    s00_axi_wvalid	: in std_logic;
+    s00_axi_wready	: out std_logic;
+    s00_axi_bresp	: out std_logic_vector(1 downto 0);
+    s00_axi_bvalid	: out std_logic;
+    s00_axi_bready	: in std_logic;
+    s00_axi_araddr	: in std_logic_vector(C_S00_AXI_ADDR_WIDTH-1 downto 0);
+    s00_axi_arprot	: in std_logic_vector(2 downto 0);
+    s00_axi_arvalid	: in std_logic;
+    s00_axi_arready	: out std_logic;
+    s00_axi_rdata	: out std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0);
+    s00_axi_rresp	: out std_logic_vector(1 downto 0);
+    s00_axi_rvalid	: out std_logic;
+    s00_axi_rready	: in std_logic
+    );
+end amacv2_scope;
+
+architecture arch_imp of amacv2_scope is
+
+  -- component declaration
+  component generic_read_registers_AXI is
+    generic (
+      C_S_AXI_DATA_WIDTH	: integer	:= 32;
+      C_S_AXI_ADDR_WIDTH	: integer	:= 7
+      );
+    port (
+      reset             : out std_logic_vector(31 downto 0);
+      control           : out std_logic_vector(31 downto 0);
+      reg2              : in  std_logic_vector(31 downto 0);
+      reg3              : in  std_logic_vector(31 downto 0);
+      reg4              : in  std_logic_vector(31 downto 0);
+      reg5              : in  std_logic_vector(31 downto 0);
+      reg6              : in  std_logic_vector(31 downto 0);
+      reg7              : in  std_logic_vector(31 downto 0);
+      reg8              : in  std_logic_vector(31 downto 0);
+      reg9              : in  std_logic_vector(31 downto 0);
+      reg10             : in  std_logic_vector(31 downto 0);
+      reg11             : in  std_logic_vector(31 downto 0);
+      reg12             : in  std_logic_vector(31 downto 0);
+      reg13             : in  std_logic_vector(31 downto 0);
+      reg14             : in  std_logic_vector(31 downto 0);
+      reg15             : in  std_logic_vector(31 downto 0);
+      reg16             : in  std_logic_vector(31 downto 0);
+      reg17             : in  std_logic_vector(31 downto 0);
+      reg18             : in  std_logic_vector(31 downto 0);
+      reg19             : in  std_logic_vector(31 downto 0);
+      reg20             : in  std_logic_vector(31 downto 0);
+      reg21             : in  std_logic_vector(31 downto 0);
+      reg22             : in  std_logic_vector(31 downto 0);
+      reg23             : in  std_logic_vector(31 downto 0);
+      reg24             : in  std_logic_vector(31 downto 0);
+      reg25             : in  std_logic_vector(31 downto 0);
+      reg26             : in  std_logic_vector(31 downto 0);
+      reg27             : in  std_logic_vector(31 downto 0);
+      reg28             : in  std_logic_vector(31 downto 0);
+      reg29             : in  std_logic_vector(31 downto 0);
+      reg30             : in  std_logic_vector(31 downto 0);
+      reg31             : in  std_logic_vector(31 downto 0);
+      S_AXI_ACLK	: in  std_logic;
+      S_AXI_ARESETN	: in  std_logic;
+      S_AXI_AWADDR	: in  std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
+      S_AXI_AWPROT	: in  std_logic_vector(2 downto 0);
+      S_AXI_AWVALID	: in  std_logic;
+      S_AXI_AWREADY	: out std_logic;
+      S_AXI_WDATA	: in  std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
+      S_AXI_WSTRB	: in  std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
+      S_AXI_WVALID	: in  std_logic;
+      S_AXI_WREADY	: out std_logic;
+      S_AXI_BRESP	: out std_logic_vector(1 downto 0);
+      S_AXI_BVALID	: out std_logic;
+      S_AXI_BREADY	: in  std_logic;
+      S_AXI_ARADDR	: in  std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
+      S_AXI_ARPROT	: in  std_logic_vector(2 downto 0);
+      S_AXI_ARVALID	: in  std_logic;
+      S_AXI_ARREADY	: out std_logic;
+      S_AXI_RDATA	: out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
+      S_AXI_RRESP	: out std_logic_vector(1 downto 0);
+      S_AXI_RVALID	: out std_logic;
+      S_AXI_RREADY	: in  std_logic
+      );
+  end component amacv2_scope_AXI;
+
+  component simplescope is
+  port (
+    reset       : in  std_logic;
+    clock       : in  std_logic;
+    input       : in  std_logic;
+    counter     : out unsigned(31 downto 0); 
+    trace       : out std_logic_vector(31 downto 0)
+  );
+  end component simplescope;
+
+  --
+  -- Signals
+  signal reset_full     : std_logic_vector(31 downto 0);
+  signal scope_reset    : std_logic;
+  
+
+  signal counter_LDx0en : unsigned(31 downto 0);
+  signal trace_LDx0en   : std_logic_vector(31 downto 0);
+  signal counter_LDy0en : unsigned(31 downto 0);        
+  signal trace_LDy0en   : std_logic_vector(31 downto 0);
+  signal counter_LDx1en : unsigned(31 downto 0);        
+  signal trace_LDx1en   : std_logic_vector(31 downto 0);
+  signal counter_LDy1en : unsigned(31 downto 0);        
+  signal trace_LDy1en   : std_logic_vector(31 downto 0);
+  signal counter_LDx2en : unsigned(31 downto 0);        
+  signal trace_LDx2en   : std_logic_vector(31 downto 0);
+  signal counter_LDy2en : unsigned(31 downto 0);        
+  signal trace_LDy2en   : std_logic_vector(31 downto 0);
+  signal counter_HrstBx : unsigned(31 downto 0);        
+  signal trace_HrstBx   : std_logic_vector(31 downto 0);
+  signal counter_HrstBy : unsigned(31 downto 0);        
+  signal trace_HrstBy   : std_logic_vector(31 downto 0);
+  signal counter_LAM    : unsigned(31 downto 0);        
+  signal trace_LAM      : std_logic_vector(31 downto 0);
+  signal counter_GPO    : unsigned(31 downto 0);        
+  signal trace_GPO      : std_logic_vector(31 downto 0);
+  signal counter_DCDCadj: unsigned(31 downto 0);        
+  signal trace_DCDCadj  : std_logic_vector(31 downto 0);
+  signal counter_DCDCEn : unsigned(31 downto 0);        
+  signal trace_DCDCEn   : std_logic_vector(31 downto 0);
+  signal counter_Ofout  : unsigned(31 downto 0);        
+  signal trace_Ofout    : std_logic_vector(31 downto 0);
+  signal counter_RO_PG_O: unsigned(31 downto 0);        
+  signal trace_RO_PG_O  : std_logic_vector(31 downto 0);
+  
+begin
+  --
+  -- AMAC output scopes
+  scope_LDx0en_inst : simplescope
+    port map (
+      clock     => s00_axi_aclk,
+      reset     => scope_reset,
+      input     => LDx0en,
+      counter   => counter_LDx0en,
+      trace     => trace_LDx0en
+      );
+
+  scope_LDy0en_inst : simplescope
+    port map (
+      clock     => s00_axi_aclk,
+      reset     => scope_reset,
+      input     => LDy0en,
+      counter   => counter_LDy0en,
+      trace     => trace_LDy0en
+      );
+
+  scope_LDx1en_inst : simplescope
+    port map (
+      clock     => s00_axi_aclk,
+      reset     => scope_reset,
+      input     => LDx1en,
+      counter   => counter_LDx1en,
+      trace     => trace_LDx1en
+      );
+
+  scope_LDy1en_inst : simplescope
+    port map (
+      clock     => s00_axi_aclk,
+      reset     => scope_reset,
+      input     => LDy1en,
+      counter   => counter_LDy1en,
+      trace     => trace_LDy1en
+      );
+
+  scope_LDx2en_inst : simplescope
+    port map (
+      clock     => s00_axi_aclk,
+      reset     => scope_reset,
+      input     => LDx2en,
+      counter   => counter_LDx2en,
+      trace     => trace_LDx2en
+      );
+
+  scope_LDy2en_inst : simplescope
+    port map (
+      clock     => s00_axi_aclk,
+      reset     => scope_reset,
+      input     => LDy2en,
+      counter   => counter_LDy2en,
+      trace     => trace_LDy2en
+      );
+
+  scope_HrstBx_inst : simplescope
+    port map (
+      clock     => s00_axi_aclk,
+      reset     => scope_reset,
+      input     => HrstBx,
+      counter   => counter_HrstBx,
+      trace     => trace_HrstBx
+      );
+
+  scope_HrstBy_inst : simplescope
+    port map (
+      clock     => s00_axi_aclk,
+      reset     => scope_reset,
+      input     => HrstBy,
+      counter   => counter_HrstBy,
+      trace     => trace_HrstBy
+      );
+
+  scope_LAM_inst : simplescope
+    port map (
+      clock     => s00_axi_aclk,
+      reset     => scope_reset,
+      input     => LAM,
+      counter   => counter_LAM,
+      trace     => trace_LAM
+      );
+
+  scope_GPO_inst : simplescope
+    port map (
+      clock     => s00_axi_aclk,
+      reset     => scope_reset,
+      input     => GPO,
+      counter   => counter_GPO,
+      trace     => trace_GPO
+      );
+
+  scope_DCDCadj_inst : simplescope
+    port map (
+      clock     => s00_axi_aclk,
+      reset     => scope_reset,
+      input     => DCDCadj,
+      counter   => counter_DCDCadj,
+      trace     => trace_DCDCadj
+      );
+
+  scope_DCDCEn_inst : simplescope
+    port map (
+      clock     => s00_axi_aclk,
+      reset     => scope_reset,
+      input     => DCDCEn,
+      counter   => counter_DCDCEn,
+      trace     => trace_DCDCEn
+      );
+
+  scope_Ofout_inst : simplescope
+    port map (
+      clock     => s00_axi_aclk,
+      reset     => scope_reset,
+      input     => Ofout,
+      counter   => counter_Ofout,
+      trace     => trace_Ofout
+      );
+
+  scope_RO_PG_O_inst : simplescope
+    port map (
+      clock     => s00_axi_aclk,
+      reset     => scope_reset,
+      input     => RO_PG_O,
+      counter   => counter_RO_PG_O,
+      trace     => trace_RO_PG_O
+      );
+
+  --
+  -- Instantiation of Axi Bus Interface AXI
+  generic_read_registers_AXI_inst : generic_read_registers_AXI
+    generic map (
+      C_S_AXI_DATA_WIDTH=> C_S00_AXI_DATA_WIDTH,
+      C_S_AXI_ADDR_WIDTH=> C_S00_AXI_ADDR_WIDTH
+      )
+    port map (
+      reset             => reset_full,
+      reg2              => std_logic_vector(counter_LDx0en),
+      reg3              => trace_LDx0en,
+      reg4              => std_logic_vector(counter_LDy0en),
+      reg5              => trace_LDy0en,
+      reg6              => std_logic_vector(counter_LDx1en),
+      reg7              => trace_LDx1en,
+      reg8              => std_logic_vector(counter_LDy1en),
+      reg9              => trace_LDy1en,
+      reg10             => std_logic_vector(counter_LDx2en),
+      reg11             => trace_LDx2en,
+      reg12             => std_logic_vector(counter_LDy2en),
+      reg13             => trace_LDy2en,
+      reg14             => std_logic_vector(counter_HrstBx),
+      reg15             => trace_HrstBx,
+      reg16             => std_logic_vector(counter_HrstBy),
+      reg17             => trace_HrstBy,
+      reg18             => std_logic_vector(counter_LAM),
+      reg19             => trace_LAM,
+      reg20             => std_logic_vector(counter_GPO),
+      reg21             => trace_GPO,
+      reg22             => std_logic_vector(counter_DCDCadj),
+      reg23             => trace_DCDCadj,
+      reg24             => std_logic_vector(counter_DCDCEn),
+      reg25             => trace_DCDCEn,
+      reg26             => std_logic_vector(counter_Ofout),
+      reg27             => trace_Ofout,
+      reg28             => std_logic_vector(counter_RO_PG_O),
+      reg29             => trace_RO_PG_O,
+      reg30             => (others => '0'),
+      reg31             => (others => '0'),
+      S_AXI_ACLK	=> s00_axi_aclk,
+      S_AXI_ARESETN	=> s00_axi_aresetn,
+      S_AXI_AWADDR	=> s00_axi_awaddr,
+      S_AXI_AWPROT	=> s00_axi_awprot,
+      S_AXI_AWVALID	=> s00_axi_awvalid,
+      S_AXI_AWREADY	=> s00_axi_awready,
+      S_AXI_WDATA	=> s00_axi_wdata,
+      S_AXI_WSTRB	=> s00_axi_wstrb,
+      S_AXI_WVALID	=> s00_axi_wvalid,
+      S_AXI_WREADY	=> s00_axi_wready,
+      S_AXI_BRESP	=> s00_axi_bresp,
+      S_AXI_BVALID	=> s00_axi_bvalid,
+      S_AXI_BREADY	=> s00_axi_bready,
+      S_AXI_ARADDR	=> s00_axi_araddr,
+      S_AXI_ARPROT	=> s00_axi_arprot,
+      S_AXI_ARVALID	=> s00_axi_arvalid,
+      S_AXI_ARREADY	=> s00_axi_arready,
+      S_AXI_RDATA	=> s00_axi_rdata,
+      S_AXI_RRESP	=> s00_axi_rresp,
+      S_AXI_RVALID	=> s00_axi_rvalid,
+      S_AXI_RREADY	=> s00_axi_rready
+      );
+
+  -- Add user logic here
+  scope_reset   <= reset_full(0);
+  -- User logic ends
+
+end arch_imp;
diff --git a/firmware/ip_repo/amacv2_scope/hdl/generic_read_registers_axi.vhd b/firmware/ip_repo/amacv2_scope/hdl/generic_read_registers_axi.vhd
new file mode 100644
index 00000000..f654d4a7
--- /dev/null
+++ b/firmware/ip_repo/amacv2_scope/hdl/generic_read_registers_axi.vhd
@@ -0,0 +1,516 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity generic_read_registers_AXI is
+  generic (
+    -- Users to add parameters here
+
+    -- User parameters ends
+    -- Do not modify the parameters beyond this line
+
+    -- Width of S_AXI data bus
+    C_S_AXI_DATA_WIDTH	: integer	:= 32;
+    -- Width of S_AXI address bus
+    C_S_AXI_ADDR_WIDTH	: integer	:= 7
+    );
+  port (
+    -- Users to add ports here
+    -- control signals
+    reset       : out std_logic_vector(31 downto 0);
+    control     : out std_logic_vector(31 downto 0);
+
+    -- outputs
+    reg2        : in  std_logic_vector(31 downto 0);
+    reg3        : in  std_logic_vector(31 downto 0);
+    reg4        : in  std_logic_vector(31 downto 0);
+    reg5        : in  std_logic_vector(31 downto 0);
+    reg6        : in  std_logic_vector(31 downto 0);
+    reg7        : in  std_logic_vector(31 downto 0);
+    reg8        : in  std_logic_vector(31 downto 0);
+    reg9        : in  std_logic_vector(31 downto 0);
+    reg10       : in  std_logic_vector(31 downto 0);
+    reg11       : in  std_logic_vector(31 downto 0);
+    reg12       : in  std_logic_vector(31 downto 0);
+    reg13       : in  std_logic_vector(31 downto 0);
+    reg14       : in  std_logic_vector(31 downto 0);
+    reg15       : in  std_logic_vector(31 downto 0);
+    reg16       : in  std_logic_vector(31 downto 0);
+    reg17       : in  std_logic_vector(31 downto 0);
+    reg18       : in  std_logic_vector(31 downto 0);
+    reg19       : in  std_logic_vector(31 downto 0);
+    reg20       : in  std_logic_vector(31 downto 0);
+    reg21       : in  std_logic_vector(31 downto 0);
+    reg22       : in  std_logic_vector(31 downto 0);
+    reg23       : in  std_logic_vector(31 downto 0);
+    reg24       : in  std_logic_vector(31 downto 0);
+    reg25       : in  std_logic_vector(31 downto 0);
+    reg26       : in  std_logic_vector(31 downto 0);
+    reg27       : in  std_logic_vector(31 downto 0);
+    reg28       : in  std_logic_vector(31 downto 0);
+    reg29       : in  std_logic_vector(31 downto 0);
+    reg30       : in  std_logic_vector(31 downto 0);
+    reg31       : in  std_logic_vector(31 downto 0);
+
+    -- User ports ends
+    -- Do not modify the ports beyond this line
+
+    -- Global Clock Signal
+    S_AXI_ACLK	: in std_logic;
+    -- Global Reset Signal. This Signal is Active LOW
+    S_AXI_ARESETN	: in std_logic;
+    -- Write address (issued by master, acceped by Slave)
+    S_AXI_AWADDR	: in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
+    -- Write channel Protection type. This signal indicates the
+    -- privilege and security level of the transaction, and whether
+    -- the transaction is a data access or an instruction access.
+    S_AXI_AWPROT	: in std_logic_vector(2 downto 0);
+    -- Write address valid. This signal indicates that the master signaling
+    -- valid write address and control information.
+    S_AXI_AWVALID	: in std_logic;
+    -- Write address ready. This signal indicates that the slave is ready
+    -- to accept an address and associated control signals.
+    S_AXI_AWREADY	: out std_logic;
+    -- Write data (issued by master, acceped by Slave) 
+    S_AXI_WDATA	: in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
+    -- Write strobes. This signal indicates which byte lanes hold
+    -- valid data. There is one write strobe bit for each eight
+    -- bits of the write data bus.    
+    S_AXI_WSTRB	: in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
+    -- Write valid. This signal indicates that valid write
+    -- data and strobes are available.
+    S_AXI_WVALID	: in std_logic;
+    -- Write ready. This signal indicates that the slave
+    -- can accept the write data.
+    S_AXI_WREADY	: out std_logic;
+    -- Write response. This signal indicates the status
+    -- of the write transaction.
+    S_AXI_BRESP	: out std_logic_vector(1 downto 0);
+    -- Write response valid. This signal indicates that the channel
+    -- is signaling a valid write response.
+    S_AXI_BVALID	: out std_logic;
+    -- Response ready. This signal indicates that the master
+    -- can accept a write response.
+    S_AXI_BREADY	: in std_logic;
+    -- Read address (issued by master, acceped by Slave)
+    S_AXI_ARADDR	: in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
+    -- Protection type. This signal indicates the privilege
+    -- and security level of the transaction, and whether the
+    -- transaction is a data access or an instruction access.
+    S_AXI_ARPROT	: in std_logic_vector(2 downto 0);
+    -- Read address valid. This signal indicates that the channel
+    -- is signaling valid read address and control information.
+    S_AXI_ARVALID	: in std_logic;
+    -- Read address ready. This signal indicates that the slave is
+    -- ready to accept an address and associated control signals.
+    S_AXI_ARREADY	: out std_logic;
+    -- Read data (issued by slave)
+    S_AXI_RDATA	: out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
+    -- Read response. This signal indicates the status of the
+    -- read transfer.
+    S_AXI_RRESP	: out std_logic_vector(1 downto 0);
+    -- Read valid. This signal indicates that the channel is
+    -- signaling the required read data.
+    S_AXI_RVALID	: out std_logic;
+    -- Read ready. This signal indicates that the master can
+    -- accept the read data and response information.
+    S_AXI_RREADY	: in std_logic
+    );
+end generic_read_registers_AXI;
+
+architecture arch_imp of generic_read_registers_AXI is
+
+  -- AXI4LITE signals
+  signal axi_awaddr	: std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
+  signal axi_awready	: std_logic;
+  signal axi_wready	: std_logic;
+  signal axi_bresp	: std_logic_vector(1 downto 0);
+  signal axi_bvalid	: std_logic;
+  signal axi_araddr	: std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
+  signal axi_arready	: std_logic;
+  signal axi_rdata	: std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
+  signal axi_rresp	: std_logic_vector(1 downto 0);
+  signal axi_rvalid	: std_logic;
+
+  -- Example-specific design signals
+  -- local parameter for addressing 32 bit / 64 bit C_S_AXI_DATA_WIDTH
+  -- ADDR_LSB is used for addressing 32/64 bit registers/memories
+  -- ADDR_LSB = 2 for 32 bits (n downto 2)
+  -- ADDR_LSB = 3 for 64 bits (n downto 3)
+  constant ADDR_LSB  : integer := (C_S_AXI_DATA_WIDTH/32)+ 1;
+  constant OPT_MEM_ADDR_BITS : integer := 4;
+  ------------------------------------------------
+  ---- Signals for user logic register space example
+  --------------------------------------------------
+  ---- Number of Slave Registers 4
+  signal slv_reg0	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
+  signal slv_reg1	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
+  signal slv_reg2	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
+  signal slv_reg3	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
+  signal slv_reg4	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
+  signal slv_reg5	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
+  signal slv_reg6	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
+  signal slv_reg7	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
+  signal slv_reg8	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
+  signal slv_reg9	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
+  signal slv_reg10	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
+  signal slv_reg11	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
+  signal slv_reg12	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
+  signal slv_reg13	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
+  signal slv_reg14	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
+  signal slv_reg15	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
+  signal slv_reg16	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
+  signal slv_reg17	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
+  signal slv_reg18	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
+  signal slv_reg19	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
+  signal slv_reg20	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
+  signal slv_reg21	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
+  signal slv_reg22	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
+  signal slv_reg23	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
+  signal slv_reg24	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
+  signal slv_reg25	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
+  signal slv_reg26	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
+  signal slv_reg27	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
+  signal slv_reg28	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
+  signal slv_reg29	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
+  signal slv_reg30	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
+  signal slv_reg31	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
+  signal slv_reg_rden	: std_logic;
+  signal slv_reg_wren	: std_logic;
+  signal reg_data_out	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
+  signal byte_index	: integer;
+  signal aw_en	: std_logic;
+
+begin
+  -- I/O Connections assignments
+
+  S_AXI_AWREADY	<= axi_awready;
+  S_AXI_WREADY	<= axi_wready;
+  S_AXI_BRESP	<= axi_bresp;
+  S_AXI_BVALID	<= axi_bvalid;
+  S_AXI_ARREADY	<= axi_arready;
+  S_AXI_RDATA	<= axi_rdata;
+  S_AXI_RRESP	<= axi_rresp;
+  S_AXI_RVALID	<= axi_rvalid;
+  -- Implement axi_awready generation
+  -- axi_awready is asserted for one S_AXI_ACLK clock cycle when both
+  -- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_awready is
+  -- de-asserted when reset is low.
+
+  process (S_AXI_ACLK)
+  begin
+    if rising_edge(S_AXI_ACLK) then 
+      if S_AXI_ARESETN = '0' then
+        axi_awready <= '0';
+        aw_en <= '1';
+      else
+        if (axi_awready = '0' and S_AXI_AWVALID = '1' and S_AXI_WVALID = '1' and aw_en = '1') then
+          -- slave is ready to accept write address when
+          -- there is a valid write address and write data
+          -- on the write address and data bus. This design 
+          -- expects no outstanding transactions. 
+          axi_awready <= '1';
+        elsif (S_AXI_BREADY = '1' and axi_bvalid = '1') then
+          aw_en <= '1';
+          axi_awready <= '0';
+        else
+          axi_awready <= '0';
+        end if;
+      end if;
+    end if;
+  end process;
+
+  -- Implement axi_awaddr latching
+  -- This process is used to latch the address when both 
+  -- S_AXI_AWVALID and S_AXI_WVALID are valid. 
+
+  process (S_AXI_ACLK)
+  begin
+    if rising_edge(S_AXI_ACLK) then 
+      if S_AXI_ARESETN = '0' then
+        axi_awaddr <= (others => '0');
+      else
+        if (axi_awready = '0' and S_AXI_AWVALID = '1' and S_AXI_WVALID = '1' and aw_en = '1') then
+          -- Write Address latching
+          axi_awaddr <= S_AXI_AWADDR;
+        end if;
+      end if;
+    end if;                   
+  end process; 
+
+  -- Implement axi_wready generation
+  -- axi_wready is asserted for one S_AXI_ACLK clock cycle when both
+  -- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_wready is 
+  -- de-asserted when reset is low. 
+
+  process (S_AXI_ACLK)
+  begin
+    if rising_edge(S_AXI_ACLK) then 
+      if S_AXI_ARESETN = '0' then
+        axi_wready <= '0';
+      else
+        if (axi_wready = '0' and S_AXI_WVALID = '1' and S_AXI_AWVALID = '1' and aw_en = '1') then
+          -- slave is ready to accept write data when 
+          -- there is a valid write address and write data
+          -- on the write address and data bus. This design 
+          -- expects no outstanding transactions.           
+          axi_wready <= '1';
+        else
+          axi_wready <= '0';
+        end if;
+      end if;
+    end if;
+  end process; 
+
+  -- Implement memory mapped register select and write logic generation
+  -- The write data is accepted and written to memory mapped registers when
+  -- axi_awready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. Write strobes are used to
+  -- select byte enables of slave registers while writing.
+  -- These registers are cleared when reset (active low) is applied.
+  -- Slave register write enable is asserted when valid address and data are available
+  -- and the slave is ready to accept the write address and write data.
+  slv_reg_wren <= axi_wready and S_AXI_WVALID and axi_awready and S_AXI_AWVALID ;
+
+  process (S_AXI_ACLK)
+    variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0); 
+  begin
+    if rising_edge(S_AXI_ACLK) then 
+      if S_AXI_ARESETN = '0' then
+        slv_reg0 <= (others => '0');
+      else
+        loc_addr := axi_awaddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB);
+        if (slv_reg_wren = '1') then
+          case loc_addr is
+            when b"00000" =>
+              for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
+                if ( S_AXI_WSTRB(byte_index) = '1' ) then
+                  -- Respective byte enables are asserted as per write strobes                   
+                  -- slave registor 0
+                  slv_reg0(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
+                end if;
+              end loop;
+            when others =>
+              slv_reg0  <= slv_reg0;
+          end case;
+        else -- reset registers after write (pulse writes)
+          slv_reg0      <= (others => '0');
+        end if;
+      end if;
+    end if;                   
+  end process; 
+
+  -- Implement write response logic generation
+  -- The write response and response valid signals are asserted by the slave 
+  -- when axi_wready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted.  
+  -- This marks the acceptance of address and indicates the status of 
+  -- write transaction.
+
+  process (S_AXI_ACLK)
+  begin
+    if rising_edge(S_AXI_ACLK) then 
+      if S_AXI_ARESETN = '0' then
+        axi_bvalid  <= '0';
+        axi_bresp   <= "00"; --need to work more on the responses
+      else
+        if (axi_awready = '1' and S_AXI_AWVALID = '1' and axi_wready = '1' and S_AXI_WVALID = '1' and axi_bvalid = '0'  ) then
+          axi_bvalid <= '1';
+          axi_bresp  <= "00"; 
+        elsif (S_AXI_BREADY = '1' and axi_bvalid = '1') then   --check if bready is asserted while bvalid is high)
+          axi_bvalid <= '0';                                 -- (there is a possibility that bready is always asserted high)
+        end if;
+      end if;
+    end if;                   
+  end process; 
+
+  -- Implement axi_arready generation
+  -- axi_arready is asserted for one S_AXI_ACLK clock cycle when
+  -- S_AXI_ARVALID is asserted. axi_awready is 
+  -- de-asserted when reset (active low) is asserted. 
+  -- The read address is also latched when S_AXI_ARVALID is 
+  -- asserted. axi_araddr is reset to zero on reset assertion.
+
+  process (S_AXI_ACLK)
+  begin
+    if rising_edge(S_AXI_ACLK) then 
+      if S_AXI_ARESETN = '0' then
+        axi_arready <= '0';
+        axi_araddr  <= (others => '1');
+      else
+        if (axi_arready = '0' and S_AXI_ARVALID = '1') then
+          -- indicates that the slave has acceped the valid read address
+          axi_arready <= '1';
+          -- Read Address latching 
+          axi_araddr  <= S_AXI_ARADDR;           
+        else
+          axi_arready <= '0';
+        end if;
+      end if;
+    end if;                   
+  end process; 
+
+  -- Implement axi_arvalid generation
+  -- axi_rvalid is asserted for one S_AXI_ACLK clock cycle when both 
+  -- S_AXI_ARVALID and axi_arready are asserted. The slave registers 
+  -- data are available on the axi_rdata bus at this instance. The 
+  -- assertion of axi_rvalid marks the validity of read data on the 
+  -- bus and axi_rresp indicates the status of read transaction.axi_rvalid 
+  -- is deasserted on reset (active low). axi_rresp and axi_rdata are 
+  -- cleared to zero on reset (active low).  
+  process (S_AXI_ACLK)
+  begin
+    if rising_edge(S_AXI_ACLK) then
+      if S_AXI_ARESETN = '0' then
+        axi_rvalid <= '0';
+        axi_rresp  <= "00";
+      else
+        if (axi_arready = '1' and S_AXI_ARVALID = '1' and axi_rvalid = '0') then
+          -- Valid read data is available at the read data bus
+          axi_rvalid <= '1';
+          axi_rresp  <= "00"; -- 'OKAY' response
+        elsif (axi_rvalid = '1' and S_AXI_RREADY = '1') then
+          -- Read data is accepted by the master
+          axi_rvalid <= '0';
+        end if;            
+      end if;
+    end if;
+  end process;
+
+  -- Implement memory mapped register select and read logic generation
+  -- Slave register read enable is asserted when valid address is available
+  -- and the slave is ready to accept the read address.
+  slv_reg_rden <= axi_arready and S_AXI_ARVALID and (not axi_rvalid) ;
+
+  process (slv_reg0 , slv_reg1 , slv_reg2 , slv_reg3 , slv_reg4 , slv_reg5 , slv_reg6 , slv_reg7 ,
+           slv_reg8 , slv_reg9 , slv_reg10, slv_reg11, slv_reg12, slv_reg13, slv_reg14, slv_reg15,
+           slv_reg16, slv_reg17, slv_reg18, slv_reg19, slv_reg20, slv_reg21, slv_reg22, slv_reg23,
+           slv_reg24, slv_reg25, slv_reg26, slv_reg27, slv_reg28, slv_reg29, slv_reg30, slv_reg31,
+           axi_araddr, S_AXI_ARESETN, slv_reg_rden)
+    variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0);
+  begin
+    -- Address decoding for reading registers
+    loc_addr := axi_araddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB);
+    case loc_addr is
+      when b"00000" =>
+        reg_data_out <= slv_reg0;
+      when b"00001" =>
+        reg_data_out <= slv_reg1;
+      when b"00010" =>
+        reg_data_out <= slv_reg2;
+      when b"00011" =>
+        reg_data_out <= slv_reg3;
+      when b"00100" =>
+        reg_data_out <= slv_reg4;
+      when b"00101" =>
+        reg_data_out <= slv_reg5;
+      when b"00110" =>
+        reg_data_out <= slv_reg6;
+      when b"00111" =>
+        reg_data_out <= slv_reg7;
+      when b"01000" =>
+        reg_data_out <= slv_reg8;
+      when b"01001" =>
+        reg_data_out <= slv_reg9;
+      when b"01010" =>
+        reg_data_out <= slv_reg10;
+      when b"01011" =>
+        reg_data_out <= slv_reg11;
+      when b"01100" =>
+        reg_data_out <= slv_reg12;
+      when b"01101" =>
+        reg_data_out <= slv_reg13;
+      when b"01110" =>
+        reg_data_out <= slv_reg14;
+      when b"01111" =>
+        reg_data_out <= slv_reg15;
+      when b"10000" =>
+        reg_data_out <= slv_reg16;
+      when b"10001" =>
+        reg_data_out <= slv_reg17;
+      when b"10010" =>
+        reg_data_out <= slv_reg18;
+      when b"10011" =>
+        reg_data_out <= slv_reg19;
+      when b"10100" =>
+        reg_data_out <= slv_reg20;
+      when b"10101" =>
+        reg_data_out <= slv_reg21;
+      when b"10110" =>
+        reg_data_out <= slv_reg22;
+      when b"10111" =>
+        reg_data_out <= slv_reg23;
+      when b"11000" =>
+        reg_data_out <= slv_reg24;
+      when b"11001" =>
+        reg_data_out <= slv_reg25;
+      when b"11010" =>
+        reg_data_out <= slv_reg26;
+      when b"11011" =>
+        reg_data_out <= slv_reg27;
+      when b"11100" =>
+        reg_data_out <= slv_reg28;
+      when b"11101" =>
+        reg_data_out <= slv_reg29;
+      when b"11110" =>
+        reg_data_out <= slv_reg30;
+      when b"11111" =>
+        reg_data_out <= slv_reg31;
+      when others =>
+        reg_data_out  <= (others => '0');
+    end case;
+  end process; 
+
+  -- Output register or memory read data
+  process( S_AXI_ACLK ) is
+  begin
+    if (rising_edge (S_AXI_ACLK)) then
+      if ( S_AXI_ARESETN = '0' ) then
+        axi_rdata  <= (others => '0');
+      else
+        if (slv_reg_rden = '1') then
+          -- When there is a valid read address (S_AXI_ARVALID) with 
+          -- acceptance of read address by the slave (axi_arready), 
+          -- output the read dada 
+          -- Read address mux
+          axi_rdata <= reg_data_out;     -- register read data
+        end if;   
+      end if;
+    end if;
+  end process;
+
+  -- Add user logic here
+  reset         <= slv_reg0;
+  control       <= slv_reg1;
+
+  slv_reg2      <= reg2;
+  slv_reg3      <= reg3;
+  slv_reg4      <= reg4;
+  slv_reg5      <= reg5;
+  slv_reg6      <= reg6;
+  slv_reg7      <= reg7;
+  slv_reg8      <= reg8;
+  slv_reg9      <= reg9;
+  slv_reg10     <= reg10;
+  slv_reg11     <= reg11;
+  slv_reg12     <= reg12;
+  slv_reg13     <= reg13;
+  slv_reg14     <= reg14;
+  slv_reg15     <= reg15;
+  slv_reg16     <= reg16;
+  slv_reg17     <= reg17;
+  slv_reg18     <= reg18;
+  slv_reg19     <= reg19;
+  slv_reg20     <= reg20;
+  slv_reg21     <= reg21;
+  slv_reg22     <= reg22;
+  slv_reg23     <= reg23;
+  slv_reg24     <= reg24;
+  slv_reg25     <= reg25;
+  slv_reg26     <= reg26;
+  slv_reg27     <= reg27;
+  slv_reg28     <= reg28;
+  slv_reg29     <= reg29;
+  slv_reg30     <= reg30;
+  slv_reg31     <= reg31;
+  -- User logic ends
+
+end arch_imp;
diff --git a/firmware/ip_repo/amacv2_scope/hdl/simplescope.vhd b/firmware/ip_repo/amacv2_scope/hdl/simplescope.vhd
new file mode 100644
index 00000000..8c1f9c90
--- /dev/null
+++ b/firmware/ip_repo/amacv2_scope/hdl/simplescope.vhd
@@ -0,0 +1,51 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity simplescope is
+  port (
+    reset       : in  std_logic;
+    clock       : in  std_logic;
+    input       : in  std_logic;
+
+    counter     : out unsigned(31 downto 0); 
+    trace       : out std_logic_vector(31 downto 0)
+  );
+end simplescope;
+
+architecture arch_imp of simplescope is
+  signal reg_input0     : std_logic;
+  signal reg_input      : std_logic;
+  
+  signal reg_counter    : unsigned(31 downto 0);
+  signal reg_trace      : std_logic_vector(31 downto 0);
+  signal reg_fr_trace   : std_logic_vector(31 downto 0);
+
+begin
+  proc_input_reg: process (reset, clock)
+  begin
+    if reset = '1' then
+      reg_input0        <= '0';
+      reg_input         <= '0';
+    elsif rising_edge(clock) then
+      reg_input0        <= input;
+      reg_input         <= reg_input0;
+    end if;
+  end process;
+
+  proc_scope    : process (reset, clock)
+  begin
+    if reset = '1' then
+      reg_counter               <= to_unsigned(0, 32);
+      reg_trace                 <= (others => '0');
+      reg_fr_trace              <= (others => '0');
+    elsif rising_edge(clock) then
+      reg_trace(31 downto 1)    <= reg_trace(30 downto 0);
+      reg_trace(0)              <= reg_input;
+      if reg_trace(15) /= reg_trace(16) then
+        reg_counter             <= reg_counter + 1;
+        reg_fr_trace            <= reg_trace;
+      end if;
+    end if;
+  end process;
+end arch_imp;
diff --git a/firmware/ip_repo/amacv2_scope/list/amacv2_scope.src b/firmware/ip_repo/amacv2_scope/list/amacv2_scope.src
new file mode 100644
index 00000000..95232983
--- /dev/null
+++ b/firmware/ip_repo/amacv2_scope/list/amacv2_scope.src
@@ -0,0 +1,4 @@
+firmware/ip_repo/amacv2_scope/hdl/amacv2_scope_top.vhd 93
+firmware/ip_repo/amacv2_scope/hdl/simplescope.vhd
+firmware/ip_repo/amacv2_scope/hdl/generic_read_registers_axi.vhd
+
diff --git a/petalinux/project-spec/meta-user/recipes-bsp/device-tree/files/system-user.dtsi b/petalinux/project-spec/meta-user/recipes-bsp/device-tree/files/system-user.dtsi
index 72d7a6b4..09eddace 100644
--- a/petalinux/project-spec/meta-user/recipes-bsp/device-tree/files/system-user.dtsi
+++ b/petalinux/project-spec/meta-user/recipes-bsp/device-tree/files/system-user.dtsi
@@ -14,6 +14,9 @@
         compatible = "generic-uio";
 };
 
+&axi_amacv2_scope_0 {
+        compatible = "generic-uio";
+};
 
 &axi_quad_spi_0 {
         spidev@0 {
-- 
GitLab


From b41b7368c806067aa09f9cfcc967d68975c4e4b4 Mon Sep 17 00:00:00 2001
From: Karol Krizka <kkrizka@gmail.com>
Date: Tue, 3 May 2022 18:09:07 -0700
Subject: [PATCH 02/16] Fixes

---
 Top/microzed_7020/list/microzed_7020.con      |  1 +
 firmware/bd/ActiveBoard.tcl                   |  5 +-
 .../amacv2_scope/hdl/amacv2_scope_top.vhd     |  3 +-
 .../hdl/generic_read_registers_axi.vhd        | 51 +++++++++++++++++--
 .../ip_repo/amacv2_scope/hdl/simplescope.vhd  |  9 ++++
 5 files changed, 60 insertions(+), 9 deletions(-)

diff --git a/Top/microzed_7020/list/microzed_7020.con b/Top/microzed_7020/list/microzed_7020.con
index e7ae10c5..38152af2 100644
--- a/Top/microzed_7020/list/microzed_7020.con
+++ b/Top/microzed_7020/list/microzed_7020.con
@@ -1,2 +1,3 @@
 Top/microzed_7020/pinmap.xdc
 Top/microzed_7020/standards.xdc
+Top/microzed_7020/debug.xdc
diff --git a/firmware/bd/ActiveBoard.tcl b/firmware/bd/ActiveBoard.tcl
index 1216247b..84ad510d 100644
--- a/firmware/bd/ActiveBoard.tcl
+++ b/firmware/bd/ActiveBoard.tcl
@@ -203,14 +203,15 @@ proc create_root_design { parentCell } {
     # AMACv2 Output Scope
 
     # IP
+    #set axi_amacv2_scope_0 [create_bd_cell -type ip -vlnv lbl.gov:pbv3:freqmeas:1.0 axi_amacv2_scope_0]
     set axi_amacv2_scope_0 [create_bd_cell -type ip -vlnv lbl.gov:pbv3:amacv2_scope:1.0 axi_amacv2_scope_0]
 
     # Ports
     set amac_outputs [list LDx0en LDx1en LDx2en LDy0en LDy1en LDy2en HrstBx HrstBy LAM GPO DCDCadj DCDCen OFout RO_PG_O]
 
     foreach amac_output ${amac_outputs} {
-	# create_bd_port -dir I ${amac_output} # Already done as part of the IO controller
-	connect_bd_net [get_bd_ports ${amac_output}] [get_bd_pins ${axi_amacv2_scope_0}/${amac_output}]
+    	# create_bd_port -dir I ${amac_output} # Already done as part of the IO controller
+    	connect_bd_net [get_bd_ports ${amac_output}] [get_bd_pins ${axi_amacv2_scope_0}/${amac_output}]
     }
 
     # AXI
diff --git a/firmware/ip_repo/amacv2_scope/hdl/amacv2_scope_top.vhd b/firmware/ip_repo/amacv2_scope/hdl/amacv2_scope_top.vhd
index 2cc34938..db894f06 100644
--- a/firmware/ip_repo/amacv2_scope/hdl/amacv2_scope_top.vhd
+++ b/firmware/ip_repo/amacv2_scope/hdl/amacv2_scope_top.vhd
@@ -123,7 +123,7 @@ architecture arch_imp of amacv2_scope is
       S_AXI_RVALID	: out std_logic;
       S_AXI_RREADY	: in  std_logic
       );
-  end component amacv2_scope_AXI;
+  end component generic_read_registers_AXI;
 
   component simplescope is
   port (
@@ -169,7 +169,6 @@ architecture arch_imp of amacv2_scope is
   signal trace_Ofout    : std_logic_vector(31 downto 0);
   signal counter_RO_PG_O: unsigned(31 downto 0);        
   signal trace_RO_PG_O  : std_logic_vector(31 downto 0);
-  
 begin
   --
   -- AMAC output scopes
diff --git a/firmware/ip_repo/amacv2_scope/hdl/generic_read_registers_axi.vhd b/firmware/ip_repo/amacv2_scope/hdl/generic_read_registers_axi.vhd
index f654d4a7..ceff8d84 100644
--- a/firmware/ip_repo/amacv2_scope/hdl/generic_read_registers_axi.vhd
+++ b/firmware/ip_repo/amacv2_scope/hdl/generic_read_registers_axi.vhd
@@ -142,7 +142,7 @@ architecture arch_imp of generic_read_registers_AXI is
   ------------------------------------------------
   ---- Signals for user logic register space example
   --------------------------------------------------
-  ---- Number of Slave Registers 4
+  ---- Number of Slave Registers 32
   signal slv_reg0	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
   signal slv_reg1	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
   signal slv_reg2	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
@@ -181,6 +181,46 @@ architecture arch_imp of generic_read_registers_AXI is
   signal byte_index	: integer;
   signal aw_en	: std_logic;
 
+  attribute MARK_DEBUG : string;
+  attribute MARK_DEBUG of slv_reg0 : signal is "TRUE";
+  attribute MARK_DEBUG of slv_reg1 : signal is "TRUE";
+  attribute MARK_DEBUG of slv_reg2 : signal is "TRUE";
+  attribute MARK_DEBUG of slv_reg3 : signal is "TRUE";
+  attribute MARK_DEBUG of slv_reg4 : signal is "TRUE";
+  attribute MARK_DEBUG of slv_reg5 : signal is "TRUE";
+  attribute MARK_DEBUG of slv_reg6 : signal is "TRUE";
+  attribute MARK_DEBUG of slv_reg7 : signal is "TRUE";
+  attribute MARK_DEBUG of slv_reg8 : signal is "TRUE";
+  attribute MARK_DEBUG of slv_reg9 : signal is "TRUE";
+  attribute MARK_DEBUG of slv_reg10 : signal is "TRUE";
+  attribute MARK_DEBUG of slv_reg11 : signal is "TRUE";
+  attribute MARK_DEBUG of slv_reg12 : signal is "TRUE";
+  attribute MARK_DEBUG of slv_reg13 : signal is "TRUE";
+  attribute MARK_DEBUG of slv_reg14 : signal is "TRUE";
+  attribute MARK_DEBUG of slv_reg15 : signal is "TRUE";
+  attribute MARK_DEBUG of slv_reg16 : signal is "TRUE";
+  attribute MARK_DEBUG of slv_reg17 : signal is "TRUE";
+  attribute MARK_DEBUG of slv_reg18 : signal is "TRUE";
+  attribute MARK_DEBUG of slv_reg19 : signal is "TRUE";
+  attribute MARK_DEBUG of slv_reg20 : signal is "TRUE";
+  attribute MARK_DEBUG of slv_reg21 : signal is "TRUE";
+  attribute MARK_DEBUG of slv_reg22 : signal is "TRUE";
+  attribute MARK_DEBUG of slv_reg23 : signal is "TRUE";
+  attribute MARK_DEBUG of slv_reg24 : signal is "TRUE";
+  attribute MARK_DEBUG of slv_reg25 : signal is "TRUE";
+  attribute MARK_DEBUG of slv_reg26 : signal is "TRUE";
+  attribute MARK_DEBUG of slv_reg27 : signal is "TRUE";
+  attribute MARK_DEBUG of slv_reg28 : signal is "TRUE";
+  attribute MARK_DEBUG of slv_reg29 : signal is "TRUE";
+  attribute MARK_DEBUG of slv_reg30 : signal is "TRUE";
+  attribute MARK_DEBUG of slv_reg31 : signal is "TRUE";
+  attribute MARK_DEBUG of axi_araddr : signal is "TRUE";
+  attribute MARK_DEBUG of S_AXI_ARESETN : signal is "TRUE";
+  attribute MARK_DEBUG of slv_reg_rden : signal is "TRUE";
+  attribute MARK_DEBUG of reg_data_out : signal is "TRUE";
+  attribute MARK_DEBUG of axi_rdata : signal is "TRUE";
+  attribute MARK_DEBUG of axi_rvalid : signal is "TRUE";
+
 begin
   -- I/O Connections assignments
 
@@ -467,16 +507,17 @@ begin
         axi_rdata  <= (others => '0');
       else
         if (slv_reg_rden = '1') then
-          -- When there is a valid read address (S_AXI_ARVALID) with 
-          -- acceptance of read address by the slave (axi_arready), 
-          -- output the read dada 
+          -- When there is a valid read address (S_AXI_ARVALID) with
+          -- acceptance of read address by the slave (axi_arready),
+          -- output the read dada
           -- Read address mux
           axi_rdata <= reg_data_out;     -- register read data
-        end if;   
+        end if;
       end if;
     end if;
   end process;
 
+
   -- Add user logic here
   reset         <= slv_reg0;
   control       <= slv_reg1;
diff --git a/firmware/ip_repo/amacv2_scope/hdl/simplescope.vhd b/firmware/ip_repo/amacv2_scope/hdl/simplescope.vhd
index 8c1f9c90..79722022 100644
--- a/firmware/ip_repo/amacv2_scope/hdl/simplescope.vhd
+++ b/firmware/ip_repo/amacv2_scope/hdl/simplescope.vhd
@@ -21,7 +21,16 @@ architecture arch_imp of simplescope is
   signal reg_trace      : std_logic_vector(31 downto 0);
   signal reg_fr_trace   : std_logic_vector(31 downto 0);
 
+  attribute MARK_DEBUG : string;
+  attribute MARK_DEBUG of reg_input0 : signal is "TRUE";
+  attribute MARK_DEBUG of reg_input : signal is "TRUE";
+  attribute MARK_DEBUG of reg_counter : signal is "TRUE";
+  attribute MARK_DEBUG of reg_trace : signal is "TRUE";
+  attribute MARK_DEBUG of reg_fr_trace : signal is "TRUE";
 begin
+  counter       <= reg_counter;
+  trace         <= reg_fr_trace;
+
   proc_input_reg: process (reset, clock)
   begin
     if reset = '1' then
-- 
GitLab


From 6f738fa165472aad3da7883a71bb59dde6dd0538 Mon Sep 17 00:00:00 2001
From: Karol Krizka <kkrizka@gmail.com>
Date: Tue, 3 May 2022 22:00:28 -0700
Subject: [PATCH 03/16] Add debug file with cores.

---
 Top/microzed_7020/debug.xdc | 118 ++++++++++++++++++++++++++++++++++++
 1 file changed, 118 insertions(+)
 create mode 100644 Top/microzed_7020/debug.xdc

diff --git a/Top/microzed_7020/debug.xdc b/Top/microzed_7020/debug.xdc
new file mode 100644
index 00000000..eecf80a5
--- /dev/null
+++ b/Top/microzed_7020/debug.xdc
@@ -0,0 +1,118 @@
+create_debug_core u_ila_0 ila
+set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0]
+set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_0]
+set_property C_ADV_TRIGGER false [get_debug_cores u_ila_0]
+set_property C_DATA_DEPTH 1024 [get_debug_cores u_ila_0]
+set_property C_EN_STRG_QUAL false [get_debug_cores u_ila_0]
+set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_0]
+set_property C_TRIGIN_EN false [get_debug_cores u_ila_0]
+set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0]
+
+# Clocks
+set_property port_width 1 [get_debug_ports u_ila_0/clk]
+connect_debug_port u_ila_0/clk [get_nets [list ActiveBoard_i/processing_system7_0/inst/FCLK_CLK0]]
+
+
+##
+# AXI Stuff
+
+set probe "u_ila_0/probe0"
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports ${probe}]
+set_property port_width 32 [get_debug_ports ${probe}]
+connect_debug_port ${probe} [get_nets [list {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg0[0]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg0[1]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg0[2]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg0[3]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg0[4]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg0[5]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg0[6]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg0[7]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg0[8]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg0[9]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg0[10]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg0[11]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg0[12]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg0[13]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg0[14]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg0[15]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg0[16]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg0[17]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg0[18]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg0[19]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg0[20]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg0[21]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg0[22]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg0[23]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg0[24]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg0[25]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg0[26]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg0[27]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg0[28]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg0[29]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg0[30]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg0[31]}]]
+
+set probe [create_debug_port u_ila_0 probe]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports ${probe}]
+set_property port_width 32 [get_debug_ports ${probe}]
+connect_debug_port ${probe} [get_nets [list {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg1[0]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg1[1]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg1[2]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg1[3]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg1[4]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg1[5]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg1[6]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg1[7]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg1[8]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg1[9]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg1[10]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg1[11]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg1[12]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg1[13]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg1[14]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg1[15]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg1[16]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg1[17]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg1[18]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg1[19]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg1[20]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg1[21]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg1[22]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg1[23]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg1[24]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg1[25]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg1[26]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg1[27]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg1[28]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg1[29]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg1[30]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg1[31]}]]
+
+set probe [create_debug_port u_ila_0 probe]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports ${probe}]
+set_property port_width 32 [get_debug_ports ${probe}]
+connect_debug_port ${probe} [get_nets [list {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg2[0]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg2[1]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg2[2]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg2[3]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg2[4]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg2[5]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg2[6]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg2[7]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg2[8]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg2[9]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg2[10]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg2[11]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg2[12]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg2[13]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg2[14]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg2[15]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg2[16]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg2[17]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg2[18]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg2[19]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg2[20]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg2[21]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg2[22]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg2[23]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg2[24]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg2[25]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg2[26]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg2[27]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg2[28]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg2[29]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg2[30]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg2[31]}]]
+
+set probe [create_debug_port u_ila_0 probe]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports ${probe}]
+set_property port_width 32 [get_debug_ports ${probe}]
+connect_debug_port ${probe} [get_nets [list {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg3[0]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg3[1]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg3[2]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg3[3]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg3[4]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg3[5]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg3[6]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg3[7]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg3[8]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg3[9]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg3[10]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg3[11]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg3[12]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg3[13]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg3[14]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg3[15]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg3[16]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg3[17]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg3[18]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg3[19]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg3[20]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg3[21]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg3[22]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg3[23]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg3[24]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg3[25]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg3[26]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg3[27]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg3[28]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg3[29]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg3[30]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg3[31]}]]
+
+set probe [create_debug_port u_ila_0 probe]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports ${probe}]
+set_property port_width 32 [get_debug_ports ${probe}]
+connect_debug_port ${probe} [get_nets [list {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg24[0]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg24[1]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg24[2]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg24[3]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg24[4]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg24[5]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg24[6]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg24[7]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg24[8]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg24[9]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg24[10]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg24[11]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg24[12]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg24[13]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg24[14]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg24[15]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg24[16]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg24[17]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg24[18]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg24[19]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg24[20]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg24[21]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg24[22]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg24[23]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg24[24]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg24[25]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg24[26]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg24[27]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg24[28]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg24[29]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg24[30]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg24[31]}]]
+
+set probe [create_debug_port u_ila_0 probe]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports ${probe}]
+set_property port_width 32 [get_debug_ports ${probe}]
+connect_debug_port ${probe} [get_nets [list {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg25[0]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg25[1]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg25[2]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg25[3]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg25[4]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg25[5]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg25[6]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg25[7]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg25[8]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg25[9]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg25[10]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg25[11]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg25[12]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg25[13]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg25[14]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg25[15]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg25[16]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg25[17]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg25[18]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg25[19]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg25[20]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg25[21]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg25[22]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg25[23]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg25[24]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg25[25]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg25[26]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg25[27]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg25[28]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg25[29]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg25[30]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg25[31]}]]
+
+set probe [create_debug_port u_ila_0 probe]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports ${probe}]
+set_property port_width 32 [get_debug_ports ${probe}]
+connect_debug_port ${probe} [get_nets [list {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/reg_data_out[0]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/reg_data_out[1]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/reg_data_out[2]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/reg_data_out[3]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/reg_data_out[4]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/reg_data_out[5]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/reg_data_out[6]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/reg_data_out[7]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/reg_data_out[8]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/reg_data_out[9]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/reg_data_out[10]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/reg_data_out[11]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/reg_data_out[12]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/reg_data_out[13]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/reg_data_out[14]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/reg_data_out[15]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/reg_data_out[16]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/reg_data_out[17]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/reg_data_out[18]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/reg_data_out[19]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/reg_data_out[20]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/reg_data_out[21]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/reg_data_out[22]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/reg_data_out[23]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/reg_data_out[24]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/reg_data_out[25]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/reg_data_out[26]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/reg_data_out[27]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/reg_data_out[28]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/reg_data_out[29]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/reg_data_out[30]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/reg_data_out[31]}]]
+
+set probe [create_debug_port u_ila_0 probe]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports ${probe}]
+set_property port_width 32 [get_debug_ports ${probe}]
+connect_debug_port ${probe} [get_nets [list {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/axi_rdata[0]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/axi_rdata[1]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/axi_rdata[2]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/axi_rdata[3]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/axi_rdata[4]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/axi_rdata[5]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/axi_rdata[6]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/axi_rdata[7]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/axi_rdata[8]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/axi_rdata[9]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/axi_rdata[10]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/axi_rdata[11]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/axi_rdata[12]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/axi_rdata[13]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/axi_rdata[14]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/axi_rdata[15]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/axi_rdata[16]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/axi_rdata[17]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/axi_rdata[18]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/axi_rdata[19]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/axi_rdata[20]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/axi_rdata[21]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/axi_rdata[22]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/axi_rdata[23]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/axi_rdata[24]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/axi_rdata[25]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/axi_rdata[26]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/axi_rdata[27]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/axi_rdata[28]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/axi_rdata[29]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/axi_rdata[30]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/axi_rdata[31]}]]
+
+set probe [create_debug_port u_ila_0 probe]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports ${probe}]
+set_property port_width 7 [get_debug_ports ${probe}]
+connect_debug_port ${probe} [get_nets [list {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/axi_araddr[0]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/axi_araddr[1]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/axi_araddr[2]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/axi_araddr[3]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/axi_araddr[4]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/axi_araddr[5]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/axi_araddr[6]}]]
+
+set probe [create_debug_port u_ila_0 probe]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports ${probe}]
+set_property port_width 1 [get_debug_ports ${probe}]
+connect_debug_port ${probe} [get_nets {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/axi_rvalid}]
+
+set probe [create_debug_port u_ila_0 probe]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports ${probe}]
+set_property port_width 1 [get_debug_ports ${probe}]
+connect_debug_port ${probe} [get_nets {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg_rden}]
+
+##
+# Scope
+proc probe_scope {name} {
+    set prefix "ActiveBoard_i/axi_amacv2_scope_0/U0/scope_${name}_inst/reg_fr_trace"
+
+    set probe [create_debug_port u_ila_0 probe]
+    set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports ${probe}]
+    set_property port_width 32 [get_debug_ports ${probe}]
+    connect_debug_port ${probe} [get_nets [list "${prefix}/reg_fr_trace[0]" "${prefix}/reg_fr_trace[1]" "${prefix}/reg_fr_trace[2]" "${prefix}/reg_fr_trace[3]" "${prefix}/reg_fr_trace[4]" "${prefix}/reg_fr_trace[5]" "${prefix}/reg_fr_trace[6]" "${prefix}/reg_fr_trace[7]" "${prefix}/reg_fr_trace[8]" "${prefix}/reg_fr_trace[9]" "${prefix}/reg_fr_trace[10]" "${prefix}/reg_fr_trace[11]" "${prefix}/reg_fr_trace[12]" "${prefix}/reg_fr_trace[13]" "${prefix}/reg_fr_trace[14]" "${prefix}/reg_fr_trace[15]" "${prefix}/reg_fr_trace[16]" "${prefix}/reg_fr_trace[17]" "${prefix}/reg_fr_trace[18]" "${prefix}/reg_fr_trace[19]" "${prefix}/reg_fr_trace[20]" "${prefix}/reg_fr_trace[21]" "${prefix}/reg_fr_trace[22]" "${prefix}/reg_fr_trace[23]" "${prefix}/reg_fr_trace[24]" "${prefix}/reg_fr_trace[25]" "${prefix}/reg_fr_trace[26]" "${prefix}/reg_fr_trace[27]" "${prefix}/reg_fr_trace[28]" "${prefix}/reg_fr_trace[29]" "${prefix}/reg_fr_trace[30]" "${prefix}/reg_fr_trace[31]"]]
+
+    set probe [create_debug_port u_ila_0 probe]
+    set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports ${probe}]
+    set_property port_width 32 [get_debug_ports ${probe}]
+    connect_debug_port ${probe} [get_nets [list "${prefix}/reg_counter[0]" "${prefix}/reg_counter[1]" "${prefix}/reg_counter[2]" "${prefix}/reg_counter[3]" "${prefix}/reg_counter[4]" "${prefix}/reg_counter[5]" "${prefix}/reg_counter[6]" "${prefix}/reg_counter[7]" "${prefix}/reg_counter[8]" "${prefix}/reg_counter[9]" "${prefix}/reg_counter[10]" "${prefix}/reg_counter[11]" "${prefix}/reg_counter[12]" "${prefix}/reg_counter[13]" "${prefix}/reg_counter[14]" "${prefix}/reg_counter[15]" "${prefix}/reg_counter[16]" "${prefix}/reg_counter[17]" "${prefix}/reg_counter[18]" "${prefix}/reg_counter[19]" "${prefix}/reg_counter[20]" "${prefix}/reg_counter[21]" "${prefix}/reg_counter[22]" "${prefix}/reg_counter[23]" "${prefix}/reg_counter[24]" "${prefix}/reg_counter[25]" "${prefix}/reg_counter[26]" "${prefix}/reg_counter[27]" "${prefix}/reg_counter[28]" "${prefix}/reg_counter[29]" "${prefix}/reg_counter[30]" "${prefix}/reg_counter[31]"]]
+
+    set probe [create_debug_port u_ila_0 probe]
+    set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports ${probe}]
+    set_property port_width 32 [get_debug_ports ${probe}]
+    connect_debug_port ${probe} [get_nets [list "${prefix}/reg_trace[0]" "${prefix}/reg_trace[1]" "${prefix}/reg_trace[2]" "${prefix}/reg_trace[3]" "${prefix}/reg_trace[4]" "${prefix}/reg_trace[5]" "${prefix}/reg_trace[6]" "${prefix}/reg_trace[7]" "${prefix}/reg_trace[8]" "${prefix}/reg_trace[9]" "${prefix}/reg_trace[10]" "${prefix}/reg_trace[11]" "${prefix}/reg_trace[12]" "${prefix}/reg_trace[13]" "${prefix}/reg_trace[14]" "${prefix}/reg_trace[15]" "${prefix}/reg_trace[16]" "${prefix}/reg_trace[17]" "${prefix}/reg_trace[18]" "${prefix}/reg_trace[19]" "${prefix}/reg_trace[20]" "${prefix}/reg_trace[21]" "${prefix}/reg_trace[22]" "${prefix}/reg_trace[23]" "${prefix}/reg_trace[24]" "${prefix}/reg_trace[25]" "${prefix}/reg_trace[26]" "${prefix}/reg_trace[27]" "${prefix}/reg_trace[28]" "${prefix}/reg_trace[29]" "${prefix}/reg_trace[30]" "${prefix}/reg_trace[31]"]]
+
+    set probe [create_debug_port u_ila_0 probe]
+    set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports ${probe}]
+    set_property port_width 1 [get_debug_ports ${probe}]
+    connect_debug_port ${probe} [get_nets [list ${prefix}/reg_input]]
+
+    set probe [create_debug_port u_ila_0 probe]
+    set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports ${probe}]
+    set_property port_width 1 [get_debug_ports ${probe}]
+    connect_debug_port ${probe} [get_nets [list ${prefix}/reg_input0]]
+
+    set probe [create_debug_port u_ila_0 probe]
+    set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports ${probe}]
+    set_property port_width 1 [get_debug_ports ${probe}]
+    connect_debug_port ${probe} [get_nets [list ${prefix}/reset]]
+}
+
+probe_scope LDx0en
+probe_scope DCDCen
+
+##
+# Clock stuff
+set_property C_CLK_INPUT_FREQ_HZ 300000000 [get_debug_cores dbg_hub]
+set_property C_ENABLE_CLK_DIVIDER false [get_debug_cores dbg_hub]
+set_property C_USER_SCAN_CHAIN 1 [get_debug_cores dbg_hub]
+connect_debug_port dbg_hub/clk [get_nets u_ila_0_FCLK_CLK0]
-- 
GitLab


From 5229976d94b9fd3903eea4de5c26591984acf37c Mon Sep 17 00:00:00 2001
From: Karol Krizka <karol.krizka@cern.ch>
Date: Wed, 4 May 2022 17:48:04 +0200
Subject: [PATCH 04/16] Update .gitlab-ci.yml file

---
 .gitlab-ci.yml | 21 +++++++++++++++++++++
 1 file changed, 21 insertions(+)

diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml
index 739d3505..fe4e44a2 100644
--- a/.gitlab-ci.yml
+++ b/.gitlab-ci.yml
@@ -1,3 +1,24 @@
+test:
+  rules:
+  - if: "$CI_COMMIT_REF_NAME =~ /^test\\/.*$/i"
+    when: never
+  - if: "$CI_COMMIT_MESSAGE =~ /DOXYGEN_ONLY/"
+    when: never
+  - if: "$CI_MERGE_REQUEST_TITLE =~ /^Draft:.*$/ && $CI_COMMIT_MESSAGE !~ /^RESOLVE_WIP:/"
+    when: never
+  - if: "$CI_MERGE_REQUEST_TARGET_BRANCH_NAME =~ /^master.*$/ && $HOG_TARGET_BRANCH
+      == null"
+    when: on_success
+  - if: "$CI_MERGE_REQUEST_TARGET_BRANCH_NAME == $HOG_TARGET_BRANCH && $HOG_TARGET_BRANCH
+      != null"
+    when: on_success
+  - if: "$CI_MERGE_REQUEST_TARGET_BRANCH_NAME == $HOG_INTERMEDIATE_BRANCH && $HOG_INTERMEDIATE_BRANCH
+      != null"
+    when: on_success
+  stage: merge
+  script:
+    - echo "Hello World!"
+
 include:
     - project: 'hog/Hog'
       file: '/hog.yml'
-- 
GitLab


From a8ac88b8e02eb0e74fb36e3b8aa7cb3c13dc09a6 Mon Sep 17 00:00:00 2001
From: Karol Krizka <karol.krizka@cern.ch>
Date: Wed, 4 May 2022 17:48:32 +0200
Subject: [PATCH 05/16] Update .gitlab-ci.yml file

---
 .gitlab-ci.yml | 21 ---------------------
 1 file changed, 21 deletions(-)

diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml
index fe4e44a2..739d3505 100644
--- a/.gitlab-ci.yml
+++ b/.gitlab-ci.yml
@@ -1,24 +1,3 @@
-test:
-  rules:
-  - if: "$CI_COMMIT_REF_NAME =~ /^test\\/.*$/i"
-    when: never
-  - if: "$CI_COMMIT_MESSAGE =~ /DOXYGEN_ONLY/"
-    when: never
-  - if: "$CI_MERGE_REQUEST_TITLE =~ /^Draft:.*$/ && $CI_COMMIT_MESSAGE !~ /^RESOLVE_WIP:/"
-    when: never
-  - if: "$CI_MERGE_REQUEST_TARGET_BRANCH_NAME =~ /^master.*$/ && $HOG_TARGET_BRANCH
-      == null"
-    when: on_success
-  - if: "$CI_MERGE_REQUEST_TARGET_BRANCH_NAME == $HOG_TARGET_BRANCH && $HOG_TARGET_BRANCH
-      != null"
-    when: on_success
-  - if: "$CI_MERGE_REQUEST_TARGET_BRANCH_NAME == $HOG_INTERMEDIATE_BRANCH && $HOG_INTERMEDIATE_BRANCH
-      != null"
-    when: on_success
-  stage: merge
-  script:
-    - echo "Hello World!"
-
 include:
     - project: 'hog/Hog'
       file: '/hog.yml'
-- 
GitLab


From 83be7c28af98bf22c484f238b9ffae52ef0f65c9 Mon Sep 17 00:00:00 2001
From: Karol Krizka <kkrizka@gmail.com>
Date: Wed, 4 May 2022 09:25:09 -0700
Subject: [PATCH 06/16] Add documentation to amacv2_scope_ip entities.

---
 .../amacv2_scope/hdl/amacv2_scope_top.vhd     | 29 +++++++++++++++++++
 .../hdl/generic_read_registers_axi.vhd        | 12 ++++++++
 .../ip_repo/amacv2_scope/hdl/simplescope.vhd  | 11 +++++++
 3 files changed, 52 insertions(+)

diff --git a/firmware/ip_repo/amacv2_scope/hdl/amacv2_scope_top.vhd b/firmware/ip_repo/amacv2_scope/hdl/amacv2_scope_top.vhd
index db894f06..d41449d3 100644
--- a/firmware/ip_repo/amacv2_scope/hdl/amacv2_scope_top.vhd
+++ b/firmware/ip_repo/amacv2_scope/hdl/amacv2_scope_top.vhd
@@ -2,6 +2,35 @@ library ieee;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;
 
+----
+-- Entity: amacv2_scope
+-- Author: Karol Krizka <kkrizka@gmail.com>
+--
+-- Top-level entity for an AXI-enabled block for scoping the digital output signals
+-- of the AMAC.
+--
+-- The following AXI registers are available:
+--  0x00        : reset all scopes by writing to bit 1
+--  0x02+2*ch   : counter from scope at channel ch
+--  0x02+2*ch+1 : last trace from channel ch, frozen with transition at center
+--
+-- The following signals are monitored:
+--  ch : signal
+--   0 : LDx0en
+--   1 : LDy0en
+--   2 : LDx1en
+--   3 : LDy1en
+--   4 : LDx2en
+--   5 : LDy2en
+--   6 : HrstBx
+--   7 : HrstBy
+--   8 : LAM
+--   9 : GPO
+--  10 : DCDCadj
+--  11 : DCDCEn
+--  12 : Ofout
+--  13 : RO_PG_O
+----
 entity amacv2_scope is
   generic (
     -- Users to add parameters here
diff --git a/firmware/ip_repo/amacv2_scope/hdl/generic_read_registers_axi.vhd b/firmware/ip_repo/amacv2_scope/hdl/generic_read_registers_axi.vhd
index ceff8d84..cfb6a984 100644
--- a/firmware/ip_repo/amacv2_scope/hdl/generic_read_registers_axi.vhd
+++ b/firmware/ip_repo/amacv2_scope/hdl/generic_read_registers_axi.vhd
@@ -2,6 +2,18 @@ library ieee;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;
 
+----
+-- Entity: generic_read_registers_AXI
+-- Author: Karol Krizka <kkrizka@gmail.com>
+--
+-- A set of 30 AXI read-only registers with 2 control register for generic applications
+-- that require monitoring.
+--
+-- The following AXI register types are available at the given addresses
+--  0x00       : strobe/reset register (write to set high for one clock cycle)
+--  0x01       : read/write register (ie: settings)
+--  0x02..0x1F : read-only registers that output value of the regADDR port
+----
 entity generic_read_registers_AXI is
   generic (
     -- Users to add parameters here
diff --git a/firmware/ip_repo/amacv2_scope/hdl/simplescope.vhd b/firmware/ip_repo/amacv2_scope/hdl/simplescope.vhd
index 79722022..b759eebb 100644
--- a/firmware/ip_repo/amacv2_scope/hdl/simplescope.vhd
+++ b/firmware/ip_repo/amacv2_scope/hdl/simplescope.vhd
@@ -2,6 +2,17 @@ library ieee;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;
 
+----
+-- Entity: simplescope
+-- Author: Karol Krizka <kkrizka@gmail.com>
+--
+-- A simple oscillioscope for monitoring the status of the `input` logic
+-- port. It counts the number of transitions (0->1 or 1->0) and stores
+-- the last +/- 16 samplings around a transition.
+--
+-- The block can be reset using the `reset` signal. The input is sampled
+-- using `clock`.
+----
 entity simplescope is
   port (
     reset       : in  std_logic;
-- 
GitLab


From daf0019c54274e9289a4cfae2048a374c4d6d2d7 Mon Sep 17 00:00:00 2001
From: Karol Krizka <kkrizka@gmail.com>
Date: Wed, 4 May 2022 10:03:33 -0700
Subject: [PATCH 07/16] Update uio device map in software.

---
 software/src/amac/AMACTB.h | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/software/src/amac/AMACTB.h b/software/src/amac/AMACTB.h
index eb03b63c..0a76e595 100644
--- a/software/src/amac/AMACTB.h
+++ b/software/src/amac/AMACTB.h
@@ -58,7 +58,7 @@ enum class HVref_t{HVref, HGND};
 class AMACTB {
 public:
   AMACTB(	std::shared_ptr<DeviceCom> dio	= std::make_shared<UIOCom>("/dev/uio0", 0x10000),
-		std::shared_ptr<DeviceCom> end	= std::make_shared<UIOCom>("/dev/uio1", 0x10000),
+		std::shared_ptr<DeviceCom> end	= std::make_shared<UIOCom>("/dev/uio2", 0x10000),
 		std::shared_ptr<DeviceCom> dac0	= std::make_shared<SPICom>("/dev/spidev1.3"),
 		std::shared_ptr<DeviceCom> dac1	= std::make_shared<SPICom>("/dev/spidev1.4"),
 		std::shared_ptr<DeviceCom> adc0	= std::make_shared<SPICom>("/dev/spidev1.5"),
@@ -67,7 +67,7 @@ public:
 		std::shared_ptr<DeviceCom> pot0	= std::make_shared<SPICom>("/dev/spidev1.0"),
 		std::shared_ptr<DeviceCom> pot1	= std::make_shared<SPICom>("/dev/spidev1.1"),
 		std::shared_ptr<DeviceCom> pot2	= std::make_shared<SPICom>("/dev/spidev1.2"),
-		std::shared_ptr<DeviceCom> frq	= std::make_shared<UIOCom>("/dev/uio2", 0x10000));
+		std::shared_ptr<DeviceCom> frq	= std::make_shared<UIOCom>("/dev/uio3", 0x10000));
   ~AMACTB();
 
   /* ======================================
-- 
GitLab


From d747ab8eae4eeb2a8b64b337453676afe2afe72d Mon Sep 17 00:00:00 2001
From: Karol Krizka <kkrizka@gmail.com>
Date: Wed, 4 May 2022 10:10:02 -0700
Subject: [PATCH 08/16] Update README.

---
 README.md | 29 +++++++++++++++++++++++++++--
 1 file changed, 27 insertions(+), 2 deletions(-)

diff --git a/README.md b/README.md
index 8d3f6342..435c4c5c 100644
--- a/README.md
+++ b/README.md
@@ -89,9 +89,34 @@ The digital IO IP block simply maps AXI registers to the simple (needing no proc
 | byte 1     | `HVSW_MUX_EN` | `MPM_MUX_EN`  | `LVL_TRANS_EN` | `Hvret_SW`  | `LD_EN_VDCDC` | `MUX_SEL2` | `MUX_SEL1`    | `MUX_SEL0`    |
 | byte 2   | -        | -        | -         | -        | -        | -         | `HVref_HGND_SW`        | `FPGA_EFUSE_PULSE`   |
 | byte 3   | -        | -        | -         | -        | -        | -         | -        | -        |
-## Endeavour (0x43C10000 - 0x43C1FFFF `/dev/uio1`)
 
-## Frequency Measurement (0x43C20000 - 0x43C2FFFF `/dev/uio2`)
+## Digital Output Scope (0x43C30000 - 0x43C3FFFF `/dev/uio1`)  
+The digital output oscilloscope IP block counts the number of transitions in the AMAC digital output. The +/- 16 bits around the last transition are also saved. The results are available for readout via AXI.
+
+### Register map
+- `0x00`   : reset all scopes by writing to bit 1  
+- `0x02+2*ch` : counter from scope at channel ch  
+- `0x02+2*ch+1` : last trace from channel ch, frozen with transition at center  
+
+### Channel definitions
+- 0 : LDx0en  
+- 1 : LDy0en  
+- 2 : LDx1en  
+- 3 : LDy1en  
+- 4 : LDx2en  
+- 5 : LDy2en  
+- 6 : HrstBx  
+- 7 : HrstBy  
+- 8 : LAM  
+- 9 : GPO  
+- 10 : DCDCadj  
+- 11 : DCDCEn  
+- 12 : Ofout  
+- 13 : RO_PG_O
+
+## Endeavour (0x43C10000 - 0x43C1FFFF `/dev/uio2`)
+
+## Frequency Measurement (0x43C20000 - 0x43C2FFFF `/dev/uio3`)
 The frequency measurement bloc is a simple synchronous (to *clk_i*) counter, which reacts on edges (if the signal is slow enough to be detected), with outputs *hi_n_o* and *lo_n_o* counting rising respectively falling edges and also measures the duty cycle of the input signal *frq_i*, with *hi_t_o* incrementing everytime *frq_i* is high and *clk_i* rises. The different *\*_flg_o* outputs monitor the registers, and are active high if an overflow is detected. On the input side, *ts_cnt_i* sets the number of clock cycles during which the measurement is done. *freeze_i*, active high, freezes the ouput registers (the measurement continues in the background) and *nrst_i*, active low, resets the bloc.
 
 For the AMACv2, there are 5 frequencies to be measured : *HVOSC0*->*HVOSC3* and *CLKOUT*, needing each one an instance of the frequency measurement bloc (without the AXI system) these 5 blocs are then mapped to AXI registers following this scheme:
-- 
GitLab


From f81c2d2c215d4155d476dc3c47dcc2450783b621 Mon Sep 17 00:00:00 2001
From: Karol Krizka <kkrizka@gmail.com>
Date: Wed, 4 May 2022 11:35:52 -0700
Subject: [PATCH 09/16] Remove debug cores. All seems to work.

---
 Top/microzed_7020/debug.xdc                   | 118 ------------------
 Top/microzed_7020/list/microzed_7020.con      |   1 -
 firmware/bd/ActiveBoard.tcl                   |   1 -
 .../hdl/generic_read_registers_axi.vhd        |  40 ------
 .../ip_repo/amacv2_scope/hdl/simplescope.vhd  |   7 --
 5 files changed, 167 deletions(-)
 delete mode 100644 Top/microzed_7020/debug.xdc

diff --git a/Top/microzed_7020/debug.xdc b/Top/microzed_7020/debug.xdc
deleted file mode 100644
index eecf80a5..00000000
--- a/Top/microzed_7020/debug.xdc
+++ /dev/null
@@ -1,118 +0,0 @@
-create_debug_core u_ila_0 ila
-set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0]
-set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_0]
-set_property C_ADV_TRIGGER false [get_debug_cores u_ila_0]
-set_property C_DATA_DEPTH 1024 [get_debug_cores u_ila_0]
-set_property C_EN_STRG_QUAL false [get_debug_cores u_ila_0]
-set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_0]
-set_property C_TRIGIN_EN false [get_debug_cores u_ila_0]
-set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0]
-
-# Clocks
-set_property port_width 1 [get_debug_ports u_ila_0/clk]
-connect_debug_port u_ila_0/clk [get_nets [list ActiveBoard_i/processing_system7_0/inst/FCLK_CLK0]]
-
-
-##
-# AXI Stuff
-
-set probe "u_ila_0/probe0"
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports ${probe}]
-set_property port_width 32 [get_debug_ports ${probe}]
-connect_debug_port ${probe} [get_nets [list {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg0[0]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg0[1]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg0[2]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg0[3]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg0[4]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg0[5]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg0[6]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg0[7]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg0[8]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg0[9]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg0[10]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg0[11]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg0[12]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg0[13]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg0[14]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg0[15]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg0[16]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg0[17]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg0[18]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg0[19]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg0[20]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg0[21]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg0[22]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg0[23]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg0[24]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg0[25]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg0[26]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg0[27]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg0[28]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg0[29]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg0[30]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg0[31]}]]
-
-set probe [create_debug_port u_ila_0 probe]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports ${probe}]
-set_property port_width 32 [get_debug_ports ${probe}]
-connect_debug_port ${probe} [get_nets [list {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg1[0]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg1[1]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg1[2]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg1[3]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg1[4]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg1[5]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg1[6]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg1[7]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg1[8]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg1[9]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg1[10]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg1[11]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg1[12]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg1[13]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg1[14]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg1[15]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg1[16]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg1[17]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg1[18]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg1[19]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg1[20]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg1[21]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg1[22]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg1[23]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg1[24]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg1[25]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg1[26]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg1[27]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg1[28]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg1[29]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg1[30]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg1[31]}]]
-
-set probe [create_debug_port u_ila_0 probe]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports ${probe}]
-set_property port_width 32 [get_debug_ports ${probe}]
-connect_debug_port ${probe} [get_nets [list {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg2[0]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg2[1]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg2[2]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg2[3]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg2[4]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg2[5]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg2[6]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg2[7]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg2[8]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg2[9]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg2[10]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg2[11]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg2[12]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg2[13]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg2[14]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg2[15]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg2[16]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg2[17]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg2[18]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg2[19]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg2[20]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg2[21]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg2[22]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg2[23]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg2[24]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg2[25]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg2[26]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg2[27]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg2[28]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg2[29]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg2[30]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg2[31]}]]
-
-set probe [create_debug_port u_ila_0 probe]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports ${probe}]
-set_property port_width 32 [get_debug_ports ${probe}]
-connect_debug_port ${probe} [get_nets [list {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg3[0]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg3[1]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg3[2]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg3[3]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg3[4]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg3[5]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg3[6]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg3[7]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg3[8]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg3[9]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg3[10]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg3[11]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg3[12]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg3[13]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg3[14]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg3[15]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg3[16]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg3[17]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg3[18]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg3[19]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg3[20]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg3[21]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg3[22]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg3[23]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg3[24]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg3[25]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg3[26]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg3[27]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg3[28]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg3[29]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg3[30]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg3[31]}]]
-
-set probe [create_debug_port u_ila_0 probe]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports ${probe}]
-set_property port_width 32 [get_debug_ports ${probe}]
-connect_debug_port ${probe} [get_nets [list {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg24[0]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg24[1]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg24[2]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg24[3]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg24[4]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg24[5]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg24[6]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg24[7]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg24[8]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg24[9]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg24[10]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg24[11]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg24[12]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg24[13]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg24[14]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg24[15]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg24[16]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg24[17]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg24[18]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg24[19]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg24[20]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg24[21]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg24[22]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg24[23]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg24[24]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg24[25]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg24[26]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg24[27]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg24[28]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg24[29]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg24[30]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg24[31]}]]
-
-set probe [create_debug_port u_ila_0 probe]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports ${probe}]
-set_property port_width 32 [get_debug_ports ${probe}]
-connect_debug_port ${probe} [get_nets [list {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg25[0]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg25[1]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg25[2]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg25[3]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg25[4]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg25[5]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg25[6]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg25[7]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg25[8]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg25[9]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg25[10]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg25[11]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg25[12]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg25[13]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg25[14]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg25[15]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg25[16]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg25[17]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg25[18]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg25[19]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg25[20]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg25[21]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg25[22]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg25[23]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg25[24]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg25[25]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg25[26]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg25[27]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg25[28]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg25[29]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg25[30]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg25[31]}]]
-
-set probe [create_debug_port u_ila_0 probe]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports ${probe}]
-set_property port_width 32 [get_debug_ports ${probe}]
-connect_debug_port ${probe} [get_nets [list {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/reg_data_out[0]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/reg_data_out[1]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/reg_data_out[2]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/reg_data_out[3]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/reg_data_out[4]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/reg_data_out[5]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/reg_data_out[6]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/reg_data_out[7]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/reg_data_out[8]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/reg_data_out[9]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/reg_data_out[10]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/reg_data_out[11]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/reg_data_out[12]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/reg_data_out[13]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/reg_data_out[14]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/reg_data_out[15]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/reg_data_out[16]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/reg_data_out[17]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/reg_data_out[18]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/reg_data_out[19]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/reg_data_out[20]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/reg_data_out[21]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/reg_data_out[22]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/reg_data_out[23]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/reg_data_out[24]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/reg_data_out[25]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/reg_data_out[26]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/reg_data_out[27]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/reg_data_out[28]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/reg_data_out[29]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/reg_data_out[30]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/reg_data_out[31]}]]
-
-set probe [create_debug_port u_ila_0 probe]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports ${probe}]
-set_property port_width 32 [get_debug_ports ${probe}]
-connect_debug_port ${probe} [get_nets [list {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/axi_rdata[0]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/axi_rdata[1]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/axi_rdata[2]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/axi_rdata[3]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/axi_rdata[4]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/axi_rdata[5]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/axi_rdata[6]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/axi_rdata[7]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/axi_rdata[8]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/axi_rdata[9]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/axi_rdata[10]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/axi_rdata[11]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/axi_rdata[12]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/axi_rdata[13]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/axi_rdata[14]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/axi_rdata[15]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/axi_rdata[16]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/axi_rdata[17]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/axi_rdata[18]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/axi_rdata[19]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/axi_rdata[20]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/axi_rdata[21]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/axi_rdata[22]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/axi_rdata[23]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/axi_rdata[24]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/axi_rdata[25]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/axi_rdata[26]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/axi_rdata[27]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/axi_rdata[28]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/axi_rdata[29]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/axi_rdata[30]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/axi_rdata[31]}]]
-
-set probe [create_debug_port u_ila_0 probe]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports ${probe}]
-set_property port_width 7 [get_debug_ports ${probe}]
-connect_debug_port ${probe} [get_nets [list {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/axi_araddr[0]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/axi_araddr[1]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/axi_araddr[2]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/axi_araddr[3]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/axi_araddr[4]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/axi_araddr[5]} {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/axi_araddr[6]}]]
-
-set probe [create_debug_port u_ila_0 probe]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports ${probe}]
-set_property port_width 1 [get_debug_ports ${probe}]
-connect_debug_port ${probe} [get_nets {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/axi_rvalid}]
-
-set probe [create_debug_port u_ila_0 probe]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports ${probe}]
-set_property port_width 1 [get_debug_ports ${probe}]
-connect_debug_port ${probe} [get_nets {ActiveBoard_i/axi_amacv2_scope_0/U0/generic_read_registers_AXI_inst/slv_reg_rden}]
-
-##
-# Scope
-proc probe_scope {name} {
-    set prefix "ActiveBoard_i/axi_amacv2_scope_0/U0/scope_${name}_inst/reg_fr_trace"
-
-    set probe [create_debug_port u_ila_0 probe]
-    set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports ${probe}]
-    set_property port_width 32 [get_debug_ports ${probe}]
-    connect_debug_port ${probe} [get_nets [list "${prefix}/reg_fr_trace[0]" "${prefix}/reg_fr_trace[1]" "${prefix}/reg_fr_trace[2]" "${prefix}/reg_fr_trace[3]" "${prefix}/reg_fr_trace[4]" "${prefix}/reg_fr_trace[5]" "${prefix}/reg_fr_trace[6]" "${prefix}/reg_fr_trace[7]" "${prefix}/reg_fr_trace[8]" "${prefix}/reg_fr_trace[9]" "${prefix}/reg_fr_trace[10]" "${prefix}/reg_fr_trace[11]" "${prefix}/reg_fr_trace[12]" "${prefix}/reg_fr_trace[13]" "${prefix}/reg_fr_trace[14]" "${prefix}/reg_fr_trace[15]" "${prefix}/reg_fr_trace[16]" "${prefix}/reg_fr_trace[17]" "${prefix}/reg_fr_trace[18]" "${prefix}/reg_fr_trace[19]" "${prefix}/reg_fr_trace[20]" "${prefix}/reg_fr_trace[21]" "${prefix}/reg_fr_trace[22]" "${prefix}/reg_fr_trace[23]" "${prefix}/reg_fr_trace[24]" "${prefix}/reg_fr_trace[25]" "${prefix}/reg_fr_trace[26]" "${prefix}/reg_fr_trace[27]" "${prefix}/reg_fr_trace[28]" "${prefix}/reg_fr_trace[29]" "${prefix}/reg_fr_trace[30]" "${prefix}/reg_fr_trace[31]"]]
-
-    set probe [create_debug_port u_ila_0 probe]
-    set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports ${probe}]
-    set_property port_width 32 [get_debug_ports ${probe}]
-    connect_debug_port ${probe} [get_nets [list "${prefix}/reg_counter[0]" "${prefix}/reg_counter[1]" "${prefix}/reg_counter[2]" "${prefix}/reg_counter[3]" "${prefix}/reg_counter[4]" "${prefix}/reg_counter[5]" "${prefix}/reg_counter[6]" "${prefix}/reg_counter[7]" "${prefix}/reg_counter[8]" "${prefix}/reg_counter[9]" "${prefix}/reg_counter[10]" "${prefix}/reg_counter[11]" "${prefix}/reg_counter[12]" "${prefix}/reg_counter[13]" "${prefix}/reg_counter[14]" "${prefix}/reg_counter[15]" "${prefix}/reg_counter[16]" "${prefix}/reg_counter[17]" "${prefix}/reg_counter[18]" "${prefix}/reg_counter[19]" "${prefix}/reg_counter[20]" "${prefix}/reg_counter[21]" "${prefix}/reg_counter[22]" "${prefix}/reg_counter[23]" "${prefix}/reg_counter[24]" "${prefix}/reg_counter[25]" "${prefix}/reg_counter[26]" "${prefix}/reg_counter[27]" "${prefix}/reg_counter[28]" "${prefix}/reg_counter[29]" "${prefix}/reg_counter[30]" "${prefix}/reg_counter[31]"]]
-
-    set probe [create_debug_port u_ila_0 probe]
-    set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports ${probe}]
-    set_property port_width 32 [get_debug_ports ${probe}]
-    connect_debug_port ${probe} [get_nets [list "${prefix}/reg_trace[0]" "${prefix}/reg_trace[1]" "${prefix}/reg_trace[2]" "${prefix}/reg_trace[3]" "${prefix}/reg_trace[4]" "${prefix}/reg_trace[5]" "${prefix}/reg_trace[6]" "${prefix}/reg_trace[7]" "${prefix}/reg_trace[8]" "${prefix}/reg_trace[9]" "${prefix}/reg_trace[10]" "${prefix}/reg_trace[11]" "${prefix}/reg_trace[12]" "${prefix}/reg_trace[13]" "${prefix}/reg_trace[14]" "${prefix}/reg_trace[15]" "${prefix}/reg_trace[16]" "${prefix}/reg_trace[17]" "${prefix}/reg_trace[18]" "${prefix}/reg_trace[19]" "${prefix}/reg_trace[20]" "${prefix}/reg_trace[21]" "${prefix}/reg_trace[22]" "${prefix}/reg_trace[23]" "${prefix}/reg_trace[24]" "${prefix}/reg_trace[25]" "${prefix}/reg_trace[26]" "${prefix}/reg_trace[27]" "${prefix}/reg_trace[28]" "${prefix}/reg_trace[29]" "${prefix}/reg_trace[30]" "${prefix}/reg_trace[31]"]]
-
-    set probe [create_debug_port u_ila_0 probe]
-    set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports ${probe}]
-    set_property port_width 1 [get_debug_ports ${probe}]
-    connect_debug_port ${probe} [get_nets [list ${prefix}/reg_input]]
-
-    set probe [create_debug_port u_ila_0 probe]
-    set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports ${probe}]
-    set_property port_width 1 [get_debug_ports ${probe}]
-    connect_debug_port ${probe} [get_nets [list ${prefix}/reg_input0]]
-
-    set probe [create_debug_port u_ila_0 probe]
-    set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports ${probe}]
-    set_property port_width 1 [get_debug_ports ${probe}]
-    connect_debug_port ${probe} [get_nets [list ${prefix}/reset]]
-}
-
-probe_scope LDx0en
-probe_scope DCDCen
-
-##
-# Clock stuff
-set_property C_CLK_INPUT_FREQ_HZ 300000000 [get_debug_cores dbg_hub]
-set_property C_ENABLE_CLK_DIVIDER false [get_debug_cores dbg_hub]
-set_property C_USER_SCAN_CHAIN 1 [get_debug_cores dbg_hub]
-connect_debug_port dbg_hub/clk [get_nets u_ila_0_FCLK_CLK0]
diff --git a/Top/microzed_7020/list/microzed_7020.con b/Top/microzed_7020/list/microzed_7020.con
index 38152af2..e7ae10c5 100644
--- a/Top/microzed_7020/list/microzed_7020.con
+++ b/Top/microzed_7020/list/microzed_7020.con
@@ -1,3 +1,2 @@
 Top/microzed_7020/pinmap.xdc
 Top/microzed_7020/standards.xdc
-Top/microzed_7020/debug.xdc
diff --git a/firmware/bd/ActiveBoard.tcl b/firmware/bd/ActiveBoard.tcl
index 84ad510d..38d078c4 100644
--- a/firmware/bd/ActiveBoard.tcl
+++ b/firmware/bd/ActiveBoard.tcl
@@ -203,7 +203,6 @@ proc create_root_design { parentCell } {
     # AMACv2 Output Scope
 
     # IP
-    #set axi_amacv2_scope_0 [create_bd_cell -type ip -vlnv lbl.gov:pbv3:freqmeas:1.0 axi_amacv2_scope_0]
     set axi_amacv2_scope_0 [create_bd_cell -type ip -vlnv lbl.gov:pbv3:amacv2_scope:1.0 axi_amacv2_scope_0]
 
     # Ports
diff --git a/firmware/ip_repo/amacv2_scope/hdl/generic_read_registers_axi.vhd b/firmware/ip_repo/amacv2_scope/hdl/generic_read_registers_axi.vhd
index cfb6a984..30213401 100644
--- a/firmware/ip_repo/amacv2_scope/hdl/generic_read_registers_axi.vhd
+++ b/firmware/ip_repo/amacv2_scope/hdl/generic_read_registers_axi.vhd
@@ -193,46 +193,6 @@ architecture arch_imp of generic_read_registers_AXI is
   signal byte_index	: integer;
   signal aw_en	: std_logic;
 
-  attribute MARK_DEBUG : string;
-  attribute MARK_DEBUG of slv_reg0 : signal is "TRUE";
-  attribute MARK_DEBUG of slv_reg1 : signal is "TRUE";
-  attribute MARK_DEBUG of slv_reg2 : signal is "TRUE";
-  attribute MARK_DEBUG of slv_reg3 : signal is "TRUE";
-  attribute MARK_DEBUG of slv_reg4 : signal is "TRUE";
-  attribute MARK_DEBUG of slv_reg5 : signal is "TRUE";
-  attribute MARK_DEBUG of slv_reg6 : signal is "TRUE";
-  attribute MARK_DEBUG of slv_reg7 : signal is "TRUE";
-  attribute MARK_DEBUG of slv_reg8 : signal is "TRUE";
-  attribute MARK_DEBUG of slv_reg9 : signal is "TRUE";
-  attribute MARK_DEBUG of slv_reg10 : signal is "TRUE";
-  attribute MARK_DEBUG of slv_reg11 : signal is "TRUE";
-  attribute MARK_DEBUG of slv_reg12 : signal is "TRUE";
-  attribute MARK_DEBUG of slv_reg13 : signal is "TRUE";
-  attribute MARK_DEBUG of slv_reg14 : signal is "TRUE";
-  attribute MARK_DEBUG of slv_reg15 : signal is "TRUE";
-  attribute MARK_DEBUG of slv_reg16 : signal is "TRUE";
-  attribute MARK_DEBUG of slv_reg17 : signal is "TRUE";
-  attribute MARK_DEBUG of slv_reg18 : signal is "TRUE";
-  attribute MARK_DEBUG of slv_reg19 : signal is "TRUE";
-  attribute MARK_DEBUG of slv_reg20 : signal is "TRUE";
-  attribute MARK_DEBUG of slv_reg21 : signal is "TRUE";
-  attribute MARK_DEBUG of slv_reg22 : signal is "TRUE";
-  attribute MARK_DEBUG of slv_reg23 : signal is "TRUE";
-  attribute MARK_DEBUG of slv_reg24 : signal is "TRUE";
-  attribute MARK_DEBUG of slv_reg25 : signal is "TRUE";
-  attribute MARK_DEBUG of slv_reg26 : signal is "TRUE";
-  attribute MARK_DEBUG of slv_reg27 : signal is "TRUE";
-  attribute MARK_DEBUG of slv_reg28 : signal is "TRUE";
-  attribute MARK_DEBUG of slv_reg29 : signal is "TRUE";
-  attribute MARK_DEBUG of slv_reg30 : signal is "TRUE";
-  attribute MARK_DEBUG of slv_reg31 : signal is "TRUE";
-  attribute MARK_DEBUG of axi_araddr : signal is "TRUE";
-  attribute MARK_DEBUG of S_AXI_ARESETN : signal is "TRUE";
-  attribute MARK_DEBUG of slv_reg_rden : signal is "TRUE";
-  attribute MARK_DEBUG of reg_data_out : signal is "TRUE";
-  attribute MARK_DEBUG of axi_rdata : signal is "TRUE";
-  attribute MARK_DEBUG of axi_rvalid : signal is "TRUE";
-
 begin
   -- I/O Connections assignments
 
diff --git a/firmware/ip_repo/amacv2_scope/hdl/simplescope.vhd b/firmware/ip_repo/amacv2_scope/hdl/simplescope.vhd
index b759eebb..b2946553 100644
--- a/firmware/ip_repo/amacv2_scope/hdl/simplescope.vhd
+++ b/firmware/ip_repo/amacv2_scope/hdl/simplescope.vhd
@@ -31,13 +31,6 @@ architecture arch_imp of simplescope is
   signal reg_counter    : unsigned(31 downto 0);
   signal reg_trace      : std_logic_vector(31 downto 0);
   signal reg_fr_trace   : std_logic_vector(31 downto 0);
-
-  attribute MARK_DEBUG : string;
-  attribute MARK_DEBUG of reg_input0 : signal is "TRUE";
-  attribute MARK_DEBUG of reg_input : signal is "TRUE";
-  attribute MARK_DEBUG of reg_counter : signal is "TRUE";
-  attribute MARK_DEBUG of reg_trace : signal is "TRUE";
-  attribute MARK_DEBUG of reg_fr_trace : signal is "TRUE";
 begin
   counter       <= reg_counter;
   trace         <= reg_fr_trace;
-- 
GitLab


From 7d52519c3238cbb6966cd1ba4a53645cdedb71c9 Mon Sep 17 00:00:00 2001
From: Karol Krizka <kkrizka@gmail.com>
Date: Wed, 4 May 2022 11:36:29 -0700
Subject: [PATCH 10/16] simplescope: fix false transition when initial state of
 input is not 0 after reset.

---
 .../ip_repo/amacv2_scope/hdl/simplescope.vhd  | 29 +++++++++----------
 1 file changed, 14 insertions(+), 15 deletions(-)

diff --git a/firmware/ip_repo/amacv2_scope/hdl/simplescope.vhd b/firmware/ip_repo/amacv2_scope/hdl/simplescope.vhd
index b2946553..a54036c4 100644
--- a/firmware/ip_repo/amacv2_scope/hdl/simplescope.vhd
+++ b/firmware/ip_repo/amacv2_scope/hdl/simplescope.vhd
@@ -35,12 +35,9 @@ begin
   counter       <= reg_counter;
   trace         <= reg_fr_trace;
 
-  proc_input_reg: process (reset, clock)
+  proc_input_reg: process (clock)
   begin
-    if reset = '1' then
-      reg_input0        <= '0';
-      reg_input         <= '0';
-    elsif rising_edge(clock) then
+    if rising_edge(clock) then
       reg_input0        <= input;
       reg_input         <= reg_input0;
     end if;
@@ -48,16 +45,18 @@ begin
 
   proc_scope    : process (reset, clock)
   begin
-    if reset = '1' then
-      reg_counter               <= to_unsigned(0, 32);
-      reg_trace                 <= (others => '0');
-      reg_fr_trace              <= (others => '0');
-    elsif rising_edge(clock) then
-      reg_trace(31 downto 1)    <= reg_trace(30 downto 0);
-      reg_trace(0)              <= reg_input;
-      if reg_trace(15) /= reg_trace(16) then
-        reg_counter             <= reg_counter + 1;
-        reg_fr_trace            <= reg_trace;
+    if rising_edge(clock) then
+      if reset = '1' then
+        reg_counter             <= to_unsigned(0, 32);
+        reg_trace               <= (others => reg_input);
+        reg_fr_trace            <= (others => '0');
+      else
+        reg_trace(31 downto 1)    <= reg_trace(30 downto 0);
+        reg_trace(0)              <= reg_input;
+        if reg_trace(15) /= reg_trace(16) then
+          reg_counter             <= reg_counter + 1;
+          reg_fr_trace            <= reg_trace;
+        end if;
       end if;
     end if;
   end process;
-- 
GitLab


From cde639f99077677093cfa7bc0b55a4b39ca8085c Mon Sep 17 00:00:00 2001
From: Karol Krizka <kkrizka@gmail.com>
Date: Thu, 5 May 2022 10:23:38 -0700
Subject: [PATCH 11/16] Add rootfs on SD card option.

---
 .gitlab-ci.yml                               | 8 +++++++-
 petalinux/project-spec/configs/rootfs_config | 8 ++++----
 2 files changed, 11 insertions(+), 5 deletions(-)

diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml
index 739d3505..592c8b9c 100644
--- a/.gitlab-ci.yml
+++ b/.gitlab-ci.yml
@@ -84,11 +84,17 @@ generate_project:microzed_7020:
     - source ${HOME}/petalinux/settings.sh
     - sed -i -e "s/root_password_placeholder/${ROOT_PASSWORD}/" petalinux/project-spec/configs/rootfs_config
     - sed -i -e "s/petalinux_password_placeholder/${PETALINUX_PASSWORD}/" petalinux/project-spec/configs/rootfs_config
-    - ./Pog/BuildPetalinux.sh sdcard
+    - ./Pog/BuildPetalinux.sh initrd
     - ./Pog/SetPetalinuxConfig.sh CONFIG_SUBSYSTEM_USER_CMDLINE "\"console=ttyPS0,115200 earlyprintk root=/dev/nfs nfsroot=${NFSROOT},v4,tcp ip=dhcp rw uio_pdrv_genirq.of_id=generic-uio\""
     - ./Pog/SetPetalinuxConfig.sh CONFIG_SUBSYSTEM_ROOTFS_INITRD
     - ./Pog/SetPetalinuxConfig.sh CONFIG_SUBSYSTEM_ROOTFS_NFS y
     - ./Pog/BuildPetalinux.sh nfs
+    - ./Pog/SetPetalinuxConfig.sh CONFIG_SUBSYSTEM_ROOTFS_NFS
+    - ./Pog/SetPetalinuxConfig.sh CONFIG_SUBSYSTEM_USER_CMDLINE "\"console=ttyPS0,115200 earlycon root=/dev/mmcblk0p2 rw rootwait uio_pdrv_genirq.of_id=generic-uio\""
+    - ./Pog/SetPetalinuxConfig.sh CONFIG_SUBSYSTEM_ROOTFS_EXT4 y
+    - ./Pog/SetPetalinuxConfig.sh CONFIG_SUBSYSTEM_SDROOT_DEV "/dev/mmcblk0p2"
+    - ./Pog/BuildPetalinux.sh sdcard
+
   artifacts:
     name: petalinux
     when: always
diff --git a/petalinux/project-spec/configs/rootfs_config b/petalinux/project-spec/configs/rootfs_config
index 9abb8d1d..c80337b6 100644
--- a/petalinux/project-spec/configs/rootfs_config
+++ b/petalinux/project-spec/configs/rootfs_config
@@ -664,8 +664,8 @@ CONFIG_openssh-sftp-server=y
 #
 # git 
 #
-# CONFIG_git is not set
-# CONFIG_git-bash-completion is not set
+CONFIG_git=y
+CONFIG_git-bash-completion=y
 # CONFIG_gitweb is not set
 # CONFIG_git-perltools is not set
 # CONFIG_git-dev is not set
@@ -2334,7 +2334,7 @@ CONFIG_udev-extraconf=y
 #
 # gdb 
 #
-# CONFIG_gdb is not set
+CONFIG_gdb=y
 # CONFIG_gdb-dbg is not set
 # CONFIG_gdb-dev is not set
 # CONFIG_gdbserver is not set
@@ -2587,7 +2587,7 @@ CONFIG_packagegroup-core-boot=y
 #
 # packagegroup-core-buildessential 
 #
-# CONFIG_packagegroup-core-buildessential is not set
+CONFIG_packagegroup-core-buildessential=y
 # CONFIG_packagegroup-core-buildessential-dev is not set
 # CONFIG_packagegroup-core-buildessential-dbg is not set
 
-- 
GitLab


From 1a3989aa75fa96e3f931232f5e8ead4c8d131044 Mon Sep 17 00:00:00 2001
From: Karol Krizka <kkrizka@gmail.com>
Date: Thu, 5 May 2022 13:23:45 -0700
Subject: [PATCH 12/16] Add CONFIG_SUBSYSTEM_SDROOT_DEV to petalinux config.

---
 petalinux/project-spec/configs/config | 1 +
 1 file changed, 1 insertion(+)

diff --git a/petalinux/project-spec/configs/config b/petalinux/project-spec/configs/config
index 72658ea1..98e1e9f7 100644
--- a/petalinux/project-spec/configs/config
+++ b/petalinux/project-spec/configs/config
@@ -206,6 +206,7 @@ CONFIG_SUBSYSTEM_ROOTFS_INITRD=y
 # CONFIG_SUBSYSTEM_ROOTFS_OTHER is not set
 CONFIG_SUBSYSTEM_INITRD_RAMDISK_LOADADDR=0x0
 CONFIG_SUBSYSTEM_INITRAMFS_IMAGE_NAME="petalinux-image-minimal"
+# CONFIG_SUBSYSTEM_SDROOT_DEV is not set
 CONFIG_SUBSYSTEM_UIMAGE_NAME="image.ub"
 CONFIG_SUBSYSTEM_RFS_FORMATS="cpio.gz tar.gz"
 CONFIG_SUBSYSTEM_DTB_PADDING_SIZE=0x1000
-- 
GitLab


From bcc2790c552a773d7d668b8121a5a2bcb823bfa8 Mon Sep 17 00:00:00 2001
From: Karol Krizka <kkrizka@gmail.com>
Date: Thu, 5 May 2022 14:58:50 -0700
Subject: [PATCH 13/16] Add cmake.

---
 petalinux/project-spec/configs/rootfs_config            | 1 +
 petalinux/project-spec/meta-user/conf/user-rootfsconfig | 1 +
 2 files changed, 2 insertions(+)

diff --git a/petalinux/project-spec/configs/rootfs_config b/petalinux/project-spec/configs/rootfs_config
index c80337b6..e9f512de 100644
--- a/petalinux/project-spec/configs/rootfs_config
+++ b/petalinux/project-spec/configs/rootfs_config
@@ -3984,6 +3984,7 @@ CONFIG_endeavour=y
 #
 # user packages 
 #
+CONFIG_cmake=y
 
 #
 # PetaLinux RootFS Settings
diff --git a/petalinux/project-spec/meta-user/conf/user-rootfsconfig b/petalinux/project-spec/meta-user/conf/user-rootfsconfig
index 62876ea3..f70f1ba0 100644
--- a/petalinux/project-spec/meta-user/conf/user-rootfsconfig
+++ b/petalinux/project-spec/meta-user/conf/user-rootfsconfig
@@ -2,3 +2,4 @@
 #These packages will get added into rootfs menu entry
 
 CONFIG_endeavour
+CONFIG_cmake
-- 
GitLab


From c0d235ab9c7543325d96ad299afe0a91cfbff4c1 Mon Sep 17 00:00:00 2001
From: Karol Krizka <kkrizka@gmail.com>
Date: Fri, 6 May 2022 23:08:00 -0700
Subject: [PATCH 14/16] Debug.

---
 Pog/SetPetalinuxConfig.sh | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Pog/SetPetalinuxConfig.sh b/Pog/SetPetalinuxConfig.sh
index bb0c7f1e..ac194cb7 100755
--- a/Pog/SetPetalinuxConfig.sh
+++ b/Pog/SetPetalinuxConfig.sh
@@ -10,7 +10,7 @@ value=${2}
 
 # Exit if any of these commands fails
 set -e
-
+set -x
 # Reference to work directory
 config=petalinux/project-spec/configs/config
 
-- 
GitLab


From 4f22ec2780696fcd0ac514669fa0bfee0f9b709e Mon Sep 17 00:00:00 2001
From: Karol Krizka <kkrizka@gmail.com>
Date: Sat, 7 May 2022 13:06:42 -0700
Subject: [PATCH 15/16] More debug.

---
 Pog/SetPetalinuxConfig.sh | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Pog/SetPetalinuxConfig.sh b/Pog/SetPetalinuxConfig.sh
index ac194cb7..9607de4e 100755
--- a/Pog/SetPetalinuxConfig.sh
+++ b/Pog/SetPetalinuxConfig.sh
@@ -15,7 +15,7 @@ set -x
 config=petalinux/project-spec/configs/config
 
 # get current value
-# CONFIG_SUBSYSTEM_ROOTFS_INITRD is not set
+cat ${config}
 current=$(grep ${key} ${config})
 if [ "x${value}x" == "xx" ]; then # unset value
     sed -i -e "s|${current}|# ${key} is not set|" petalinux/project-spec/configs/config
-- 
GitLab


From 66d8194116365d2a2e75cfa6d8fb9b969be23b4c Mon Sep 17 00:00:00 2001
From: Karol Krizka <kkrizka@gmail.com>
Date: Thu, 12 May 2022 14:03:44 -0700
Subject: [PATCH 16/16] Fix SetPetalinuxConfig when config key does not already
 exist.

---
 Pog/SetPetalinuxConfig.sh | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/Pog/SetPetalinuxConfig.sh b/Pog/SetPetalinuxConfig.sh
index 9607de4e..530c1a4d 100755
--- a/Pog/SetPetalinuxConfig.sh
+++ b/Pog/SetPetalinuxConfig.sh
@@ -14,6 +14,11 @@ set -x
 # Reference to work directory
 config=petalinux/project-spec/configs/config
 
+# Check if current value exists, otherwise insert
+if ! grep -q ${key} ${config}; then
+    echo "# ${key} is not set" >> petalinux/project-spec/configs/config
+fi
+
 # get current value
 cat ${config}
 current=$(grep ${key} ${config})
-- 
GitLab