From 282fd0cbc70ed03db1cb9761eea5f0b126fea35f Mon Sep 17 00:00:00 2001
From: Karol Krizka <kkrizka@gmail.com>
Date: Wed, 12 Aug 2020 16:58:04 -0700
Subject: [PATCH 01/29] Configurable module-powerOn/Off.

---
 scripts/module-powerOff.sh | 31 +++++++++++++++-
 scripts/module-powerOn.sh  | 73 ++++++++++++++++++++++++++------------
 2 files changed, 81 insertions(+), 23 deletions(-)

diff --git a/scripts/module-powerOff.sh b/scripts/module-powerOff.sh
index f5f17b4d..c3bf21b4 100755
--- a/scripts/module-powerOff.sh
+++ b/scripts/module-powerOff.sh
@@ -1,8 +1,37 @@
 #!/bin/bash
 
 #
-# Disable the power on a X hybrid
+# Disable the power on a module
 #
+# Both hybrids are disabled, independent if the
+# module is LS or SS.
+
+TBCONFIG="config/equip_testbench.json"
+
+function usage
+{
+    echo "${0} [-e equip.json]"
+    echo ""
+    echo "Optional arguments:"
+    echo " -e equip.json   Equipment configuration file (default: ${TBCONFIG})"
+    exit 1
+}
+
+while getopts ":he:" opt; do
+    case ${opt} in
+	h )
+	    usage
+	    ;;
+	e )
+	    TBCONFIG=${OPTARG}
+	    ;;
+	\? )
+	    usage
+	    ;;
+    esac
+done
+
+OPTS="-e ${TBCONFIG}"
 
 # HV mux
 ./bin/pbv3_field write CntSetCHV0en 0
diff --git a/scripts/module-powerOn.sh b/scripts/module-powerOn.sh
index 9609a959..3e28e3e3 100755
--- a/scripts/module-powerOn.sh
+++ b/scripts/module-powerOn.sh
@@ -1,40 +1,69 @@
 #!/bin/bash
 
 #
-# Enable the power on a X hybrid
+# Enable the power on a module
 #
+# Both hybrids are enabled, independent if the
+# module is LS or SS.
+
+TBCONFIG="config/equip_testbench.json"
+
+function usage
+{
+    echo "${0} [-e equip.json]"
+    echo ""
+    echo "Optional arguments:"
+    echo " -e equip.json   Equipment configuration file (default: ${TBCONFIG})"
+    exit 1
+}
+
+while getopts ":he:" opt; do
+    case ${opt} in
+	h )
+	    usage
+	    ;;
+	e )
+	    TBCONFIG=${OPTARG}
+	    ;;
+	\? )
+	    usage
+	    ;;
+    esac
+done
+
+OPTS="-e ${TBCONFIG}"
 
 #
 # Enable the DCDC
-./bin/pbv3_field write DCDCen 1
-./bin/pbv3_field write DCDCenC 1
+./bin/pbv3_field ${OPTS} write DCDCen 1 || exit 1
+./bin/pbv3_field ${OPTS} write DCDCenC 1 || exit 1
 
 #
 # Enable the Hybrid
 
 # resetB
-./bin/pbv3_field write RstCntHyHCCresetB 1
-./bin/pbv3_field write RstCntCHyHCCresetB 1
-./bin/pbv3_field write RstCntHxHCCresetB 1
-./bin/pbv3_field write RstCntCHxHCCresetB 1
+./bin/pbv3_field ${OPTS} write RstCntHyHCCresetB 1 || exit 1
+./bin/pbv3_field ${OPTS} write RstCntCHyHCCresetB 1 || exit 1
+./bin/pbv3_field ${OPTS} write RstCntHxHCCresetB 1 || exit 1
+./bin/pbv3_field ${OPTS} write RstCntCHxHCCresetB 1 || exit 1
 
 # Hybrid LDOs
-./bin/pbv3_field write CntSetHyLDO0en 1
-./bin/pbv3_field write CntSetCHyLDO0en 1
-./bin/pbv3_field write CntSetHyLDO1en 1
-./bin/pbv3_field write CntSetCHyLDO1en 1
-./bin/pbv3_field write CntSetHyLDO2en 1
-./bin/pbv3_field write CntSetCHyLDO2en 1
-
-./bin/pbv3_field write CntSetHxLDO0en 1
-./bin/pbv3_field write CntSetCHxLDO0en 1
-./bin/pbv3_field write CntSetHxLDO1en 1
-./bin/pbv3_field write CntSetCHxLDO1en 1
-./bin/pbv3_field write CntSetHxLDO2en 1
-./bin/pbv3_field write CntSetCHxLDO2en 1
+./bin/pbv3_field ${OPTS} write CntSetHyLDO0en 1 || exit 1
+./bin/pbv3_field ${OPTS} write CntSetCHyLDO0en 1 || exit 1
+./bin/pbv3_field ${OPTS} write CntSetHyLDO1en 1 || exit 1
+./bin/pbv3_field ${OPTS} write CntSetCHyLDO1en 1 || exit 1
+./bin/pbv3_field ${OPTS} write CntSetHyLDO2en 1 || exit 1
+./bin/pbv3_field ${OPTS} write CntSetCHyLDO2en 1 || exit 1
+
+./bin/pbv3_field ${OPTS} write CntSetHxLDO0en 1 || exit 1
+./bin/pbv3_field ${OPTS} write CntSetCHxLDO0en 1 || exit 1
+./bin/pbv3_field ${OPTS} write CntSetHxLDO1en 1 || exit 1
+./bin/pbv3_field ${OPTS} write CntSetCHxLDO1en 1 || exit 1
+./bin/pbv3_field ${OPTS} write CntSetHxLDO2en 1 || exit 1
+./bin/pbv3_field ${OPTS} write CntSetCHxLDO2en 1 || exit 1
 
 # HV mux
-./bin/pbv3_field write CntSetCHV0en 1
-./bin/pbv3_field write CntSetHV0en 1
+./bin/pbv3_field ${OPTS} write CntSetCHV0en 1 || exit 1
+./bin/pbv3_field ${OPTS} write CntSetHV0en 1 || exit 1
 
 
-- 
GitLab


From 66c0b573de33c1578588950869c43f3931acb0ea Mon Sep 17 00:00:00 2001
From: Karol Krizka <kkrizka@gmail.com>
Date: Wed, 12 Aug 2020 17:11:07 -0700
Subject: [PATCH 02/29] Start working on module run that runs module stuff.

---
 scripts/module-run.sh | 80 +++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 80 insertions(+)
 create mode 100755 scripts/module-run.sh

diff --git a/scripts/module-run.sh b/scripts/module-run.sh
new file mode 100755
index 00000000..43f26921
--- /dev/null
+++ b/scripts/module-run.sh
@@ -0,0 +1,80 @@
+#!/bin/bash
+
+#
+# Script that handles running a test on a module from scratch (no power)
+#
+# The following steps are taken:
+#  - Enable LV power
+#  - Configure the Powerboard
+#  - Power the hybrids (module-powerOn.sh)
+#  - Launch two programs in parallel:
+#    1. ROOT macro for control of the hybrid
+#    2. Start Powerboard monitoring loop
+#
+# The Powerboard monitoring loop is started a few seconds after ITSDAQ
+# to prevent clashes on the I2C bus.
+#
+# If either ITSDAQ or pbv3_monitor exists, then this script also
+# completes.
+
+TBCONFIG="config/equip_testbench.json"
+PBCONFIG=""
+
+function usage
+{
+    echo "${0} [-e equip.json -c powerboard.json] datadir"
+    echo ""
+    echo "Optional arguments:"
+    echo " -e equip.json      Equipment configuration file (default: ${TBCONFIG})"
+    echo " -e powerboard.json Powerboard configuration file (default: ${PBCONFIG})"
+    exit 1
+}
+
+while getopts ":he:c:" opt; do
+    case ${opt} in
+	h )
+	    usage
+	    ;;
+	e )
+	    TBCONFIG=${OPTARG}
+	    ;;
+	c )
+	    PBCONFIG=${OPTARG}
+	    ;;
+	\? )
+	    usage
+	    ;;
+    esac
+done
+shift $((OPTIND -1))
+
+OPTS="-e ${TBCONFIG}"
+
+DATADIR=${1}
+
+#
+# Create output directory
+if [ ! -d ${DATADIR} ]; then
+    mkdir -p ${DATADIR}
+fi
+
+#
+# Turn on LV
+./bin/powersupply ${OPTS} -c Vin set-voltage 11 1 || exit 2
+./bin/powersupply ${OPTS} -e ${TBCONFIG} -c Vin power-on || exit 2
+
+#
+# Configure Powerboard
+if [ ! -z "${PBCONFIG}" ];
+then
+    echo "CONFIG"
+    ./bin/pbv3_config ${OPTS} ${PBCONFIG} || exit 2
+fi
+
+#
+# Power Hybrids
+./scripts/module-powerOn.sh ${OPTS} || exit 2
+
+#
+# Start monitoring loops
+
-- 
GitLab


From b8ef6b5bb76ae020e7c035050ccb979d8741f2b9 Mon Sep 17 00:00:00 2001
From: Karol Krizka <kkrizka@gmail.com>
Date: Wed, 12 Aug 2020 20:57:45 -0700
Subject: [PATCH 03/29] Add process monitoring to module-run.

---
 scripts/EXEITSDAQ.sh  | 67 +++++++++++++++++++++++++++++++++++++++++++
 scripts/module-run.sh | 51 ++++++++++++++++++++++++++++++--
 2 files changed, 116 insertions(+), 2 deletions(-)
 create mode 100755 scripts/EXEITSDAQ.sh

diff --git a/scripts/EXEITSDAQ.sh b/scripts/EXEITSDAQ.sh
new file mode 100755
index 00000000..21eab177
--- /dev/null
+++ b/scripts/EXEITSDAQ.sh
@@ -0,0 +1,67 @@
+#!/bin/bash
+
+if [ ${#} != 1 ]; then
+    echo "usage: ${0} macro.C"
+    exit -1
+fi
+
+EXECFILE=$(realpath ${1})
+
+echo "Running ITS DAQ"
+
+# Should work with both ./RUNITSDAQ.sh and . ./RUNITSDAQ.sh
+source_name=${BASH_SOURCE[0]}
+
+if [ "x${SCTDAQ_ROOT}" != "x" ]; then
+  echo "Using SCTDAQ_ROOT=$SCTDAQ_ROOT (from env)"
+else
+  which realpath 2> /dev/null > /dev/null && export SCTDAQ_ROOT=$(realpath $(dirname ${source_name}))
+  which realpath 2> /dev/null > /dev/null || export SCTDAQ_ROOT=$(dirname ${source_name})
+  if [ "${SCTDAQ_ROOT}" = "." ]; then
+    export SCTDAQ_ROOT=$(pwd)
+  fi
+  echo "Using SCTDAQ_ROOT=$SCTDAQ_ROOT (from script directory)"
+fi
+
+if [[ "$ROOTSYS" == "" && -x /usr/bin/root ]] ; then
+  echo "Using system ROOT"
+  export ROOTSYS=/usr
+fi
+
+# Set RUN_ROOT6=yes if using root6
+function check_root_version_6()
+{
+  RUN_ROOT6=no
+
+  # If root-config is in the path this is easy
+  if [[ -x $(which root-config) ]]
+  then
+    if root-config --version | grep "^6.*" > /dev/null
+    then
+      RUN_ROOT6=yes
+      return
+    fi
+  fi
+
+  # If no root-config look for clues in the ROOTSYS path
+  if [[ "x$(echo $ROOTSYS | sed 's:.*ROOT/\(.\).*:\1:')" = "x6" || "x$(echo $ROOTSYS | sed 's:.*\(root-6\).*:\1:')" = "xroot-6" ]]; then
+    RUN_ROOT6=yes
+  fi
+}
+
+check_root_version_6
+
+RUN_DIR=$SCTDAQ_ROOT
+
+if [[ $RUN_ROOT6 == yes ]]; then
+  echo Using root 6 setup
+  RUN_DIR=$SCTDAQ_ROOT/root6
+
+  # Macros expect to be able to refer to things from top directory
+  export ROOT_INCLUDE_PATH=$SCTDAQ_ROOT
+fi
+
+[[ "$SCTDAQ_VAR" == "" ]] && echo -e '\033[31mPlease set SCTDAQ_VAR to point to config area\033[39m'
+
+echo "Now running Stavelet macro in ROOT"
+(cd $RUN_DIR; $ROOTSYS/bin/root -b -q Stavelet.cpp ${EXECFILE})
diff --git a/scripts/module-run.sh b/scripts/module-run.sh
index 43f26921..ee6f73c6 100755
--- a/scripts/module-run.sh
+++ b/scripts/module-run.sh
@@ -17,12 +17,26 @@
 # If either ITSDAQ or pbv3_monitor exists, then this script also
 # completes.
 
+# trap Ctrl+c for cleanup
+trap cleanup INT
+trap cleanup SIGCHLD
+function cleanup() {
+    echo "Terminate processes ${ITSDAQPID} ${PBPID}"
+    if [ ! -z "${ITSDAQPID}" ]; then
+	ps -p ${ITSDAQPID} && kill -- ${ITSDAQPID} 
+    fi
+    if [ ! -z "${PBPID}" ]; then
+	ps -p ${PBPID} && kill -- ${PBPID}
+    fi
+    exit 0
+}
+
 TBCONFIG="config/equip_testbench.json"
 PBCONFIG=""
 
 function usage
 {
-    echo "${0} [-e equip.json -c powerboard.json] datadir"
+    echo "${0} [-e equip.json -c powerboard.json] datadir macro.C"
     echo ""
     echo "Optional arguments:"
     echo " -e equip.json      Equipment configuration file (default: ${TBCONFIG})"
@@ -51,6 +65,7 @@ shift $((OPTIND -1))
 OPTS="-e ${TBCONFIG}"
 
 DATADIR=${1}
+MACRO=${2}
 
 #
 # Create output directory
@@ -67,8 +82,8 @@ fi
 # Configure Powerboard
 if [ ! -z "${PBCONFIG}" ];
 then
-    echo "CONFIG"
     ./bin/pbv3_config ${OPTS} ${PBCONFIG} || exit 2
+    PBOPTS="-c ${PBCONFIG}"
 fi
 
 #
@@ -78,3 +93,35 @@ fi
 #
 # Start monitoring loops
 
+# ITSDAQ
+./scripts/EXEITSDAQ.sh ${MACRO} >> ${DATADIR}/itsdaq.out 2>> ${DATADIR}/itsdaq.err &
+ITSDAQPID=${!}
+echo "ITSDAQ running as ${ITSDAQPID}"
+
+sleep 30
+
+# Powerboard
+./bin/pbv3_monitor ${PBOPTS} ${OPTS} ${DATADIR}/ >> ${DATADIR}/pb.out 2>> ${DATADIR}/pb.err &
+PBPID=${!}
+echo "Powerboard running as ${PBPID}"
+
+#
+# Wait for monitoring loops
+while true
+do
+    ps -p ${ITSDAQPID} -o pid= > /dev/null
+    if [ ${?} != 0 ]; then
+	echo "ITSDAQ proccess has completed"
+	break
+    fi
+
+    ps -p ${PBPID} -o pid= > /dev/null
+    if [ ${?} != 0 ]; then
+	echo "Powerboard process has completed"
+	break
+    fi
+
+    sleep 1
+done
+
+cleanup
-- 
GitLab


From 5177ea7115597b4c818f9bbcf0f86215fd8ec22f Mon Sep 17 00:00:00 2001
From: Karol Krizka <kkrizka@gmail.com>
Date: Mon, 17 Aug 2020 15:26:35 -0700
Subject: [PATCH 04/29] Add simple itsdaq monitor script.

---
 itsdaq/monitor.C | 56 ++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 56 insertions(+)
 create mode 100644 itsdaq/monitor.C

diff --git a/itsdaq/monitor.C b/itsdaq/monitor.C
new file mode 100644
index 00000000..62cdfbc0
--- /dev/null
+++ b/itsdaq/monitor.C
@@ -0,0 +1,56 @@
+#include "macros/pedestal.cpp"
+
+#include <chrono>
+
+void monitor()
+{
+  e->Restart();
+  hcc_star_reg_write(16,4);
+  hcc_star_reg_write(17,0xf0004223); // Homer
+  abc_star_fast_command(2,2);
+  abc_star_fast_command(3,0);
+  e->ExecuteConfigs();
+  abc_star_fast_command(2,2);
+  abc_star_fast_command(3,0);
+  e->ExecuteConfigs();
+
+  /*
+  e->ConfigureVariable(ST_ODELAY_COM, 1);
+  e->HardReset();
+  e->ExecuteConfigs();
+
+  e->DebugSetOption("hcc_star_event_framer_report");
+  e->burst.save_raw_event_data = true;
+  */
+
+  double time_running=12*60*60; // seconds for duration of monitorin
+  auto t_bigloopstart = std::chrono::system_clock::now();
+
+  while(std::chrono::duration_cast<std::chrono::seconds>(std::chrono::system_clock::now()-t_bigloopstart).count()<time_running)
+    {
+      e->CacheMasks(1);
+
+      // Strobe Delay
+      std::cout << "=== Start Strobe Delay ===" << std::endl;
+      ABCStarStrobeDelay();
+
+      // // Pedestal Scan
+      // std::cout << "=== Start Pedestal Scan ===" << std::endl;
+      // pedestalScan(6,15,100);
+      // ABCStarNoiseTrimPlot(e->runnum, e->scannum, 6, 15);
+
+      // // High stats 3PG
+      // std::cout << "=== Start Three Point Gain ===" << std::endl;
+      // ABCStarThreePointGain(1.0, 32, 1024);
+
+      // // Noise occupancy
+      // std::cout << "=== Start Noise Occupancy ===" << std::endl;
+      // ABCStarNO(0, 3, 10000);
+
+      e->CacheMasks(0);
+      
+      sleep(10);
+    }
+
+  std::cout << "DONE WITH " << std::chrono::duration_cast<std::chrono::seconds>(std::chrono::system_clock::now()-t_bigloopstart).count() << std::endl;
+}
-- 
GitLab


From 171f78d9ae02d8b2ce3778b8e8efd17f008e6494 Mon Sep 17 00:00:00 2001
From: Berkeley Strippers <strips@lbl>
Date: Tue, 18 Aug 2020 08:16:15 -0700
Subject: [PATCH 05/29] Update monitor.C to dump registers.

---
 itsdaq/monitor.C | 422 +++++++++++++++++++++++++++++++++++++++++++----
 1 file changed, 392 insertions(+), 30 deletions(-)

diff --git a/itsdaq/monitor.C b/itsdaq/monitor.C
index 62cdfbc0..8b40ab8e 100644
--- a/itsdaq/monitor.C
+++ b/itsdaq/monitor.C
@@ -1,9 +1,391 @@
-#include "macros/pedestal.cpp"
+//#include "macros/pedestal.cpp"
 
 #include <chrono>
+#include <unordered_map>
+#include <vector>
+#include <memory>
+
+#include <TFile.h>
+#include <TTree.h>
+
+/**
+ * Register map and values for a given chip
+ */
+class RegisterDump
+{
+public:
+  RegisterDump(const std::unordered_map<int, std::string>& registerMap)
+    : m_registerMap(registerMap)
+  {
+    // Value holders
+    for(const std::pair<int, std::string>& kv : m_registerMap)
+      {
+	m_registerValues   [kv.first]=0;
+	m_registerValuesErr[kv.first]=true;
+      }
+  }
+  
+  void createBranches(TTree *t, const std::string& prefix)
+  {
+    for(const std::pair<int, std::string>& kv : m_registerMap)
+      {
+	t->Branch((prefix+"_"+kv.second       ).c_str(), &m_registerValues   [kv.first]);
+	t->Branch((prefix+"_"+kv.second+"_err").c_str(), &m_registerValuesErr[kv.first]);
+      }
+  }
+
+  void resetValue(int reg)
+  {
+    m_registerValues   [reg]=0x0;
+    m_registerValuesErr[reg]=true;
+  }
+
+  void setValue(int reg, uint32_t value)
+  {
+    m_registerValues   [reg]=value;
+    m_registerValuesErr[reg]=false;
+  }
+
+private:
+  std::unordered_map<int, std::string> m_registerMap;
+  std::unordered_map<int, uint32_t> m_registerValues;
+  std::unordered_map<int, uint8_t > m_registerValuesErr;
+};
+
+/**
+ * Reads all registers from HCC + ABC and dumps them to a
+ * TTree.
+ */
+class RegisterDumper
+{
+public:
+  RegisterDumper(const std::string& outputpath, TST *e)
+    : m_e(e)
+  {
+    m_fh=TFile::Open(outputpath.c_str(), "RECREATE");
+    createTree();
+  }
+
+  ~RegisterDumper()
+  {
+    m_tree->Write();
+    m_fh->Close();
+  }
+
+  void run()
+  {
+    br_timestamp = std::chrono::duration_cast<std::chrono::seconds>((std::chrono::system_clock::now().time_since_epoch())).count();
+
+    bool hccFormat=m_e->HccPresent();
+    for (int n=0; n<m_e->GetMaxModules(); ++n)
+      {
+	if(!m_e->m[n]->present) continue;
+
+	// Peform HCC register read
+	for(const std::pair<int, std::string>& kv : hcc_regs)
+	  {
+	    br_hccregs[n]->resetValue(kv.first);
+
+	    m_e->ReadChipRegister(kv.first+256);
+
+	    // Find packets in streams
+	    std::vector<std::vector<uint8_t>> packets;
+	    find_hcc_packets(n, packets);
+
+	    // Decode packets
+	    for(const std::vector<uint8_t>& packet : packets)
+	      {
+		StarChipPacket p(false);
+		p.add_word(0x13c);
+		for(uint8_t byte : packet)
+		  p.add_word(byte);
+		p.add_word(0x1dc);
+		p.parse();
+
+		if(p.type!=TYP_HCC_RR)
+		  {
+		    std::cerr << "WARNING! Unexpected packet type: " << packet_type_names[p.type] << std::endl;
+		    continue;
+		  }
+
+		if(p.address!=kv.first)
+		  {
+		    std::cerr << "ERROR! Wrong address: " << (uint32_t)p.address << "(expected " << (uint32_t)kv.first << ")" << std::endl;
+		    continue;
+		  }
+
+		br_hccregs[n]->setValue(kv.first, p.value);
+	      }
+
+	    // Peform ABC register read
+	    bool v1=(get_chipset()==9);
+	    const std::unordered_map<int, std::string>& abc_regs=(v1)?(abcv1_regs):(abcv0_regs);
+	    for(const std::pair<int, std::string>& kv : abc_regs)
+	      {
+		for(int a=0; a<m_e->GetNChips(); ++a)
+		  br_abcregs[n][a]->resetValue(kv.first);
+
+		m_e->ReadChipRegister(kv.first);
+
+		// Find packets in streams
+		std::vector<std::vector<uint8_t>> packets;
+		find_hcc_packets(n, packets);
+
+		// Decode packets
+		for(const std::vector<uint8_t>& packet : packets)
+		  {
+		    StarChipPacket p(false);
+		    p.add_word(0x13c);
+		    for(uint8_t byte : packet)
+		      p.add_word(byte);
+		    p.add_word(0x1dc);
+		    p.parse();
+
+		    if(p.type!=TYP_ABC_RR)
+		      {
+			std::cerr << "WARNING! Unexpected packet type: " << packet_type_names[p.type] << std::endl;
+			continue;
+		      }
+
+		    if(p.address!=kv.first)
+		      {
+			std::cerr << "ERROR! Wrong address: " << (uint32_t)p.address << "(expected " << (uint32_t)kv.first << ")" << std::endl;
+			continue;
+		      }
+		    
+		    uint32_t abc_index=(p.abc_status>>12)&0xF;
+		    if(!br_abcregs[n][abc_index])
+		      {
+			std::cerr << "ERROR! Invalid ABC index: " << (uint32_t) p.channel_abc << std::endl;
+			continue;
+		      }
+
+		    br_abcregs[n][abc_index]->setValue(kv.first, p.value);
+		  }
+	      }
+	  }
+
+	// Fill tree
+	m_tree->Fill();
+      }
+  }
+
+  bool find_hcc_packets(int module_id, std::vector<std::vector<uint8_t>>& result)
+  {
+    result.clear();
+
+    int l = 0; // "link" 1 should be empty
+    int burst = m_e->burst_count;
+    int scan_width = e->m[module_id]->scan_size(burst, l);
+
+    int offset = 1; // Why is bit 0 0?
+    // Skip 1s at the beginning
+    while(e->m[module_id]->scan_lookup(burst, l, offset))
+      {
+	offset ++;
+	if(offset >= scan_width)
+	  return true; // No data detected
+      }
+
+    // This is for unencoded mode (not 8b10b)
+    // SOP|10-bit words|EOP
+    // Each 10-bit word has 00 then 8-bit byte
+    uint16_t word = 0;
+
+    std::vector<uint8_t> bytes;
+
+    bool inPacket = false;
+    bool found_end = false;
+
+    for(int b=0; b+offset<scan_width; b++)
+      {
+	int bit = m_e->m[module_id]->scan_lookup(burst, l, offset + b);
+	//std::cout << b+offset << "/" << scan_width << " - " << (b%10) << ": " << bit << std::endl;
+
+	if(found_end)
+	  {
+	    if(bit == 0)
+	      continue;
+	    else
+	      {
+		std::cerr << "Found non-zero bit after end of capture2 buffer" << std::endl;
+		// Capture2 doesn't fill the whole of the burst width
+		break;
+	      }
+	  }
+
+	word <<= 1;
+	if(bit) word |= 1;
+
+	if((b % 10) != 9) // Continue parsing until end of "byte" reached
+	  continue;
+
+	if(word == 0x3ff)
+	  {
+	    // Ignore idle
+	    if(inPacket)
+	      {
+		std::cerr << "Bad idle inside packet" << std::endl;
+		bytes.clear();
+		inPacket = false;
+	      }
+	  }
+	else if(word == 0x13c) // SOP
+	  {
+	    inPacket = true;
+	  }
+	else if(word == 0x1dc) // EOP
+	  {
+	    result.push_back(bytes);
+	    bytes.clear();
+	    inPacket = false;
+	  }
+	else
+	  {
+	    if(word & 0x300)
+	      {
+		// We're in capture2 mode, so might come to the end of the data
+		// before the end of the burst histo.
+		uint16_t test_word = word;
+		while(test_word & 0x200)
+		  test_word = (test_word << 1) & 0x3ff;
+
+		if(test_word)
+		  {
+		    std::cerr << "Non data word is NOT IDLE, EOP or SOP!, but is 0x" << std::hex << std::setw(4) << std::setfill('0') << word << std::dec << std::endl;
+
+		    inPacket = false;
+		    bytes.clear();
+		  }
+		else
+		  {
+		    // End of buffer we copied from the packet
+		    found_end = true;
+		  }
+	      }
+	    bytes.push_back(word&0xFF);
+	  }
+
+	word = 0;
+      }
+
+    return false;
+  }
+
+private:
+  // module
+  TST *m_e=nullptr;
+
+  // output data
+  TFile *m_fh=nullptr;
+  TTree *m_tree=nullptr;
+  std::unordered_map<int, std::shared_ptr<RegisterDump>> br_hccregs;
+  std::unordered_map<int, std::vector<std::shared_ptr<RegisterDump>>> br_abcregs;
+  uint32_t br_timestamp;
+
+  // Register map
+  static const std::unordered_map<int, std::string> hcc_regs;
+  static const std::unordered_map<int, std::string> abcv0_regs;
+  static const std::unordered_map<int, std::string> abcv1_regs;
+
+  void createTree()
+  {      
+    // Create the tree
+    m_fh->cd();
+    m_tree=new TTree("registers", "registers");
+    m_tree->Branch("time", &br_timestamp);
+
+    // Query module to get structure
+    for (int n=0; n<m_e->GetMaxModules(); ++n)
+      {
+	if(!m_e->m[n]->present) continue;
+
+	// HCC Registers
+	if(m_e->HccPresent())
+	  {
+	    br_hccregs[n]=std::make_shared<RegisterDump>(hcc_regs);
+	    br_hccregs[n]->createBranches(m_tree, "Mod"+std::to_string(n)+"_HCC");
+	  }
+
+	// ABC Registers
+	bool v1=get_chipset()==9;
+	const std::unordered_map<int, std::string>& abc_regs=(v1)?(abcv1_regs):(abcv0_regs);
+	std::vector<std::shared_ptr<RegisterDump>> abcdumps(e->GetNChips(), nullptr);
+	for(int a=0; a<m_e->GetNChips(); ++a)
+	  {
+	    abcdumps[a]=std::make_shared<RegisterDump>(abc_regs);
+	    abcdumps[a]->createBranches(m_tree, "Mod"+std::to_string(n)+"_ABC"+std::to_string(a));
+	  }
+	br_abcregs[n]=abcdumps;
+      }
+  }
+
+  int get_chipset()
+  {
+    for(int n=0; n<m_e->GetLastPresentId()+1; ++n)
+      {
+	if(e->m[n]->present == 0) continue;
+	float chipset = e->RetrieveVariable(n, ST_CHIPSET);
+	return (int)(chipset + 0.5);
+      }
+    return -1;
+  }
+};
+
+const std::unordered_map<int, std::string> RegisterDumper::hcc_regs =
+  { {0, "SEU1"}, {1, "SEU2"}, {2, "SEU3"}, {3, "FrameRaw"}, {4,"LCBerr"}, {5,"ADCStatus"}, {6,"Status"},
+    {15,"HPR"}, {17,"Addressing"}, {32,"Delay1"}, {33,"Delay2"}, {34,"Delay3"}, {35,"PLL1"}, {36,"PLL2"}, {37,"PLL3"}, {38,"DRV1"},
+    {39,"DRV2"}, {40,"ICenable"}, {41,"OPmodeLo"}, {42,"OPmodeHi"}, {43,"Cfg1"}, {44,"Cfg2"}, {45,"ExtRst"}, {46,"ExtRstC"}, {47,"ErrCfg"},{48,"ADCcfg"} };
+
+const std::unordered_map<int, std::string> RegisterDumper::abcv0_regs =
+  { {1, "DCS1"}, {2, "DCS2"}, {3, "DCS3"}, {4, "DCS4"}, {6, "DCS6"}, {7, "DCS7"},
+    {32, "Config0"}, {33, "Config1"}, {34, "Config2"}, {35, "Config3"}, {36, "Config4"}, {37, "Config5"}, {38, "Config6"},
+    {48, "SEUStat"}, {49, "SEUStat2"}, {50, "FuseStat"}, {51, "ADCStat"}, {52,"LCBErr"},
+    {63, "HPR"},
+    {16, "Mask0"}, {17, "Mask1"}, {18, "Mask2"}, {19, "Mask3"}, {20, "Mask4"}, {21, "Mask5"}, {22, "Mask6"}, {23, "Mask7"},
+    {64, "TrimLo0" }, {65, "TrimLo1" }, {66, "TrimLo2" }, {67, "TrimLo3" }, {68, "TrimLo4" }, {69, "TrimLo5" }, {70, "TrimLo6" }, {71, "TrimLo7" },
+    {72, "TrimLo8" }, {73, "TrimLo9" }, {74, "TrimLo10"}, {75, "TrimLo11"}, {76, "TrimLo12"}, {77, "TrimLo13"}, {78, "TrimLo14"}, {79, "TrimLo15"},
+    {80, "TrimLo16"}, {81, "TrimLo17"}, {82, "TrimLo18"}, {83, "TrimLo19"}, {84, "TrimLo20"}, {85, "TrimLo21"}, {86, "TrimLo22"}, {87, "TrimLo23"},
+    {88, "TrimLo24"}, {89, "TrimLo25"}, {90, "TrimLo26"}, {91, "TrimLo27"}, {92, "TrimLo28"}, {93, "TrimLo29"}, {94, "TrimLo30"}, {95, "TrimLo31"},
+    {96, "TrimHi0"}, {97, "TrimHi1"}, {98, "TrimHi2"}, {99, "TrimHi3"}, {100, "TrimHi4"}, {101, "TrimHi5"}, {102, "TrimHi6"}, {103, "TrimHi7"},
+    {104, "CalMask0"}, {105, "CalMask1"}, {106, "CalMask2"}, {107, "CalMask3"}, {108, "CalMask4"}, {109, "CalMask5"}, {110, "CalMask6"}, {111, "CalMask7"}, 
+    {128, "Counter0" }, {129, "Counter1" }, {130, "Counter2" }, {131, "Counter3" }, {132, "Counter4" }, {133, "Counter5" }, {134, "Counter6" }, {135, "Counter7" },
+    {136, "Counter8" }, {137, "Counter9" }, {138, "Counter10"}, {139, "Counter11"}, {140, "Counter12"}, {141, "Counter13"}, {142, "Counter14"}, {143, "Counter15"},
+    {144, "Counter16"}, {145, "Counter17"}, {146, "Counter18"}, {147, "Counter19"}, {148, "Counter20"}, {149, "Counter21"}, {150, "Counter22"}, {151, "Counter23"},
+    {152, "Counter24"}, {153, "Counter25"}, {154, "Counter26"}, {155, "Counter27"}, {156, "Counter28"}, {157, "Counter29"}, {158, "Counter30"}, {159, "Counter31"},
+    {160, "Counter32"}, {161, "Counter33"}, {162, "Counter34"}, {163, "Counter35"}, {164, "Counter36"}, {165, "Counter37"}, {166, "Counter38"}, {167, "Counter39"},
+    {168, "Counter40"}, {169, "Counter41"}, {170, "Counter42"}, {171, "Counter43"}, {172, "Counter44"}, {173, "Counter45"}, {174, "Counter46"}, {175, "Counter47"},
+    {176, "Counter48"}, {177, "Counter49"}, {178, "Counter50"}, {179, "Counter51"}, {180, "Counter52"}, {181, "Counter53"}, {182, "Counter54"}, {183, "Counter55"},
+    {184, "Counter56"}, {185, "Counter57"}, {186, "Counter58"}, {187, "Counter59"}, {188, "Counter60"}, {189, "Counter61"}, {190, "Counter62"}, {191, "Counter63"}
+  };
+
+const std::unordered_map<int, std::string> RegisterDumper::abcv1_regs =
+  { {0, "MAGIC"}, {1, "DCS1"}, {2, "DCS2"}, {3, "DCS3"},
+    {32, "Config0"}, {33, "Config1"},
+    {48, "SEU_STAT0"}, {49, "STAT1"}, {50, "FuseSTAT2"}, {51, "ADC_STAT3"}, {52,"STAT4"}, {53,"STAT5"}, {54,"STAT6"},
+    {63, "HPR"},
+    {16, "Mask0"}, {17, "Mask1"}, {18, "Mask2"}, {19, "Mask3"}, {20, "Mask4"}, {21, "Mask5"}, {22, "Mask6"}, {23, "Mask7"},
+    {64, "TrimLo0" }, {65, "TrimLo1" }, {66, "TrimLo2" }, {67, "TrimLo3" }, {68, "TrimLo4" }, {69, "TrimLo5" }, {70, "TrimLo6" }, {71, "TrimLo7" },
+    {72, "TrimLo8" }, {73, "TrimLo9" }, {74, "TrimLo10"}, {75, "TrimLo11"}, {76, "TrimLo12"}, {77, "TrimLo13"}, {78, "TrimLo14"}, {79, "TrimLo15"},
+    {80, "TrimLo16"}, {81, "TrimLo17"}, {82, "TrimLo18"}, {83, "TrimLo19"}, {84, "TrimLo20"}, {85, "TrimLo21"}, {86, "TrimLo22"}, {87, "TrimLo23"},
+    {88, "TrimLo24"}, {89, "TrimLo25"}, {90, "TrimLo26"}, {91, "TrimLo27"}, {92, "TrimLo28"}, {93, "TrimLo29"}, {94, "TrimLo30"}, {95, "TrimLo31"},
+    {96, "TrimHi0"}, {97, "TrimHi1"}, {98, "TrimHi2"}, {99, "TrimHi3"}, {100, "TrimHi4"}, {101, "TrimHi5"}, {102, "TrimHi6"}, {103, "TrimHi7"},
+    {104, "CalMask0"}, {105, "CalMask1"}, {106, "CalMask2"}, {107, "CalMask3"}, {108, "CalMask4"}, {109, "CalMask5"}, {110, "CalMask6"}, {111, "CalMask7"}, 
+    {128, "Counter0" }, {129, "Counter1" }, {130, "Counter2" }, {131, "Counter3" }, {132, "Counter4" }, {133, "Counter5" }, {134, "Counter6" }, {135, "Counter7" },
+    {136, "Counter8" }, {137, "Counter9" }, {138, "Counter10"}, {139, "Counter11"}, {140, "Counter12"}, {141, "Counter13"}, {142, "Counter14"}, {143, "Counter15"},
+    {144, "Counter16"}, {145, "Counter17"}, {146, "Counter18"}, {147, "Counter19"}, {148, "Counter20"}, {149, "Counter21"}, {150, "Counter22"}, {151, "Counter23"},
+    {152, "Counter24"}, {153, "Counter25"}, {154, "Counter26"}, {155, "Counter27"}, {156, "Counter28"}, {157, "Counter29"}, {158, "Counter30"}, {159, "Counter31"},
+    {160, "Counter32"}, {161, "Counter33"}, {162, "Counter34"}, {163, "Counter35"}, {164, "Counter36"}, {165, "Counter37"}, {166, "Counter38"}, {167, "Counter39"},
+    {168, "Counter40"}, {169, "Counter41"}, {170, "Counter42"}, {171, "Counter43"}, {172, "Counter44"}, {173, "Counter45"}, {174, "Counter46"}, {175, "Counter47"},
+    {176, "Counter48"}, {177, "Counter49"}, {178, "Counter50"}, {179, "Counter51"}, {180, "Counter52"}, {181, "Counter53"}, {182, "Counter54"}, {183, "Counter55"},
+    {184, "Counter56"}, {185, "Counter57"}, {186, "Counter58"}, {187, "Counter59"}, {188, "Counter60"}, {189, "Counter61"}, {190, "Counter62"}, {191, "Counter63"}
+  };
+
 
 void monitor()
 {
+  //
+  // Initialize ITSDAQ and Hybrids
   e->Restart();
   hcc_star_reg_write(16,4);
   hcc_star_reg_write(17,0xf0004223); // Homer
@@ -14,43 +396,23 @@ void monitor()
   abc_star_fast_command(3,0);
   e->ExecuteConfigs();
 
-  /*
-  e->ConfigureVariable(ST_ODELAY_COM, 1);
-  e->HardReset();
+  abc_star_hpr_stop();
+  hcc_star_hpr_stop();
   e->ExecuteConfigs();
 
-  e->DebugSetOption("hcc_star_event_framer_report");
-  e->burst.save_raw_event_data = true;
-  */
+  //
+  // Test structures
+  RegisterDumper d("test.root", e);
 
+  //
+  // RUN ME!
   double time_running=12*60*60; // seconds for duration of monitorin
   auto t_bigloopstart = std::chrono::system_clock::now();
 
   while(std::chrono::duration_cast<std::chrono::seconds>(std::chrono::system_clock::now()-t_bigloopstart).count()<time_running)
     {
-      e->CacheMasks(1);
-
-      // Strobe Delay
-      std::cout << "=== Start Strobe Delay ===" << std::endl;
-      ABCStarStrobeDelay();
-
-      // // Pedestal Scan
-      // std::cout << "=== Start Pedestal Scan ===" << std::endl;
-      // pedestalScan(6,15,100);
-      // ABCStarNoiseTrimPlot(e->runnum, e->scannum, 6, 15);
-
-      // // High stats 3PG
-      // std::cout << "=== Start Three Point Gain ===" << std::endl;
-      // ABCStarThreePointGain(1.0, 32, 1024);
-
-      // // Noise occupancy
-      // std::cout << "=== Start Noise Occupancy ===" << std::endl;
-      // ABCStarNO(0, 3, 10000);
-
-      e->CacheMasks(0);
+      d.run();
       
-      sleep(10);
+      sleep(1);
     }
-
-  std::cout << "DONE WITH " << std::chrono::duration_cast<std::chrono::seconds>(std::chrono::system_clock::now()-t_bigloopstart).count() << std::endl;
 }
-- 
GitLab


From 63ed13838fd42aea1c2dbb7887776f08490a698a Mon Sep 17 00:00:00 2001
From: Berkeley Strippers <strips@lbl>
Date: Tue, 18 Aug 2020 08:16:28 -0700
Subject: [PATCH 06/29] Exit on failure in module-powerOff.

---
 scripts/module-powerOff.sh | 40 +++++++++++++++++++-------------------
 1 file changed, 20 insertions(+), 20 deletions(-)

diff --git a/scripts/module-powerOff.sh b/scripts/module-powerOff.sh
index c3bf21b4..a479617f 100755
--- a/scripts/module-powerOff.sh
+++ b/scripts/module-powerOff.sh
@@ -34,31 +34,31 @@ done
 OPTS="-e ${TBCONFIG}"
 
 # HV mux
-./bin/pbv3_field write CntSetCHV0en 0
-./bin/pbv3_field write CntSetHV0en 0
+./bin/pbv3_field ${OPTS} write CntSetCHV0en 0 || exit 1
+./bin/pbv3_field ${OPTS} write CntSetHV0en 0 || exit 1
 
 # Hybrid LDOs
-./bin/pbv3_field write CntSetHyLDO0en 0
-./bin/pbv3_field write CntSetCHyLDO0en 0
-./bin/pbv3_field write CntSetHyLDO1en 0
-./bin/pbv3_field write CntSetCHyLDO1en 0
-./bin/pbv3_field write CntSetHyLDO2en 0
-./bin/pbv3_field write CntSetCHyLDO2en 0
+./bin/pbv3_field ${OPTS} write CntSetHyLDO0en 0 || exit 1
+./bin/pbv3_field ${OPTS} write CntSetCHyLDO0en 0 || exit 1
+./bin/pbv3_field ${OPTS} write CntSetHyLDO1en 0 || exit 1
+./bin/pbv3_field ${OPTS} write CntSetCHyLDO1en 0 || exit 1
+./bin/pbv3_field ${OPTS} write CntSetHyLDO2en 0 || exit 1
+./bin/pbv3_field ${OPTS} write CntSetCHyLDO2en 0 || exit 1
 
-./bin/pbv3_field write CntSetHxLDO0en 0
-./bin/pbv3_field write CntSetCHxLDO0en 0
-./bin/pbv3_field write CntSetHxLDO1en 0
-./bin/pbv3_field write CntSetCHxLDO1en 0
-./bin/pbv3_field write CntSetHxLDO2en 0
-./bin/pbv3_field write CntSetCHxLDO2en 0
+./bin/pbv3_field ${OPTS} write CntSetHxLDO0en 0 || exit 1
+./bin/pbv3_field ${OPTS} write CntSetCHxLDO0en 0 || exit 1
+./bin/pbv3_field ${OPTS} write CntSetHxLDO1en 0 || exit 1
+./bin/pbv3_field ${OPTS} write CntSetCHxLDO1en 0 || exit 1
+./bin/pbv3_field ${OPTS} write CntSetHxLDO2en 0 || exit 1
+./bin/pbv3_field ${OPTS} write CntSetCHxLDO2en 0 || exit 1
 
 # resetB
-./bin/pbv3_field write RstCntHyHCCresetB 0
-./bin/pbv3_field write RstCntCHyHCCresetB 0
-./bin/pbv3_field write RstCntHxHCCresetB 0
-./bin/pbv3_field write RstCntCHxHCCresetB 0
+./bin/pbv3_field ${OPTS} write RstCntHyHCCresetB 0 || exit 1
+./bin/pbv3_field ${OPTS} write RstCntCHyHCCresetB 0 || exit 1
+./bin/pbv3_field ${OPTS} write RstCntHxHCCresetB 0 || exit 1
+./bin/pbv3_field ${OPTS} write RstCntCHxHCCresetB 0 || exit 1
 
 
 # DCDC
-./bin/pbv3_field write DCDCen 0
-./bin/pbv3_field write DCDCenC 0
+./bin/pbv3_field ${OPTS} write DCDCen 0 || exit 1
+./bin/pbv3_field ${OPTS} write DCDCenC 0 || exit 1
-- 
GitLab


From f323aa9b1d5b848c0f66b80df1de5780f3415161 Mon Sep 17 00:00:00 2001
From: Berkeley Strippers <strips@lbl>
Date: Tue, 18 Aug 2020 11:43:06 -0700
Subject: [PATCH 07/29] Fixes to cleanup to EXEITSDAQ.

---
 scripts/EXEITSDAQ.sh  | 2 +-
 scripts/module-run.sh | 8 ++++----
 2 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/scripts/EXEITSDAQ.sh b/scripts/EXEITSDAQ.sh
index 21eab177..b47f235b 100755
--- a/scripts/EXEITSDAQ.sh
+++ b/scripts/EXEITSDAQ.sh
@@ -64,4 +64,4 @@ fi
 [[ "$SCTDAQ_VAR" == "" ]] && echo -e '\033[31mPlease set SCTDAQ_VAR to point to config area\033[39m'
 
 echo "Now running Stavelet macro in ROOT"
-(cd $RUN_DIR; $ROOTSYS/bin/root -b -q Stavelet.cpp ${EXECFILE})
+(cd ${RUN_DIR}; ${ROOTSYS}/bin/root -b -q Stavelet.cpp ${EXECFILE})
diff --git a/scripts/module-run.sh b/scripts/module-run.sh
index ee6f73c6..bdf15efd 100755
--- a/scripts/module-run.sh
+++ b/scripts/module-run.sh
@@ -23,10 +23,10 @@ trap cleanup SIGCHLD
 function cleanup() {
     echo "Terminate processes ${ITSDAQPID} ${PBPID}"
     if [ ! -z "${ITSDAQPID}" ]; then
-	ps -p ${ITSDAQPID} && kill -- ${ITSDAQPID} 
+	ps -p ${ITSDAQPID} && kill -- -${ITSDAQPID} 
     fi
     if [ ! -z "${PBPID}" ]; then
-	ps -p ${PBPID} && kill -- ${PBPID}
+	ps -p ${PBPID} && kill -- -${PBPID}
     fi
     exit 0
 }
@@ -94,14 +94,14 @@ fi
 # Start monitoring loops
 
 # ITSDAQ
-./scripts/EXEITSDAQ.sh ${MACRO} >> ${DATADIR}/itsdaq.out 2>> ${DATADIR}/itsdaq.err &
+setsid ./scripts/EXEITSDAQ.sh ${MACRO} >> ${DATADIR}/itsdaq.out 2>> ${DATADIR}/itsdaq.err &
 ITSDAQPID=${!}
 echo "ITSDAQ running as ${ITSDAQPID}"
 
 sleep 30
 
 # Powerboard
-./bin/pbv3_monitor ${PBOPTS} ${OPTS} ${DATADIR}/ >> ${DATADIR}/pb.out 2>> ${DATADIR}/pb.err &
+setsid ./bin/pbv3_monitor ${PBOPTS} ${OPTS} ${DATADIR}/ >> ${DATADIR}/pb.out 2>> ${DATADIR}/pb.err &
 PBPID=${!}
 echo "Powerboard running as ${PBPID}"
 
-- 
GitLab


From 08b73c370d1d446515c42d60b0b6838066dec42c Mon Sep 17 00:00:00 2001
From: Berkeley Strippers <strips@lbl>
Date: Tue, 18 Aug 2020 11:45:56 -0700
Subject: [PATCH 08/29] Big and small loops to monitor.C

---
 itsdaq/monitor.C | 25 ++++++++++++++++++-------
 1 file changed, 18 insertions(+), 7 deletions(-)

diff --git a/itsdaq/monitor.C b/itsdaq/monitor.C
index 8b40ab8e..7023abad 100644
--- a/itsdaq/monitor.C
+++ b/itsdaq/monitor.C
@@ -384,6 +384,9 @@ const std::unordered_map<int, std::string> RegisterDumper::abcv1_regs =
 
 void monitor()
 {
+  double time_running =12*60*60; // seconds for duration of monitoring
+  double stime_running=60; // seconds between saving results
+
   //
   // Initialize ITSDAQ and Hybrids
   e->Restart();
@@ -400,19 +403,27 @@ void monitor()
   hcc_star_hpr_stop();
   e->ExecuteConfigs();
 
-  //
-  // Test structures
-  RegisterDumper d("test.root", e);
 
   //
   // RUN ME!
-  double time_running=12*60*60; // seconds for duration of monitorin
   auto t_bigloopstart = std::chrono::system_clock::now();
-
   while(std::chrono::duration_cast<std::chrono::seconds>(std::chrono::system_clock::now()-t_bigloopstart).count()<time_running)
     {
-      d.run();
+      //
+      // Test structures
+      char f_name[128];
+      BuildScanFileName(f_name,e->runnum,e->scannum++);
+      RegisterDumper d(f_name, e);
+
+      auto t_smallloopstart = std::chrono::system_clock::now();
+
+      //
+      // Continious monitoring
+      while(std::chrono::duration_cast<std::chrono::seconds>(std::chrono::system_clock::now()-t_smallloopstart).count()<stime_running)
+	{
+	  d.run();
       
-      sleep(1);
+	  sleep(1);
+	}
     }
 }
-- 
GitLab


From 6e71c3de38200fa9767efd70f3dd04f68b037ac0 Mon Sep 17 00:00:00 2001
From: Berkeley Strippers <strips@lbl>
Date: Thu, 20 Aug 2020 15:02:33 -0700
Subject: [PATCH 09/29] Configurable number of powerboards for PBv3TBModule.

---
 pbv3/PBv3TBModule.cpp | 26 ++++++++++++++++++++++----
 pbv3/PBv3TBModule.h   |  7 ++++++-
 2 files changed, 28 insertions(+), 5 deletions(-)

diff --git a/pbv3/PBv3TBModule.cpp b/pbv3/PBv3TBModule.cpp
index 5eded582..e0b6ff30 100644
--- a/pbv3/PBv3TBModule.cpp
+++ b/pbv3/PBv3TBModule.cpp
@@ -36,6 +36,15 @@ void PBv3TBModule::setConfiguration(const nlohmann::json& config)
 	{
 	  m_port=kv.value();
 	}
+      else if(kv.key()=="pbs")
+	{
+	  for(const auto &pb : kv.value())
+	    {
+	      m_pb_idpads.push_back(pb.value("idpads",0));
+	      m_pb_commid.push_back(pb.value("commid",0));
+	    }
+	}
+
     }
 
   PBv3TB::setConfiguration(config);
@@ -45,10 +54,19 @@ void PBv3TBModule::init()
 {
   // PB com
   m_com=std::make_shared<ITSDAQCom>(m_ip, m_port);
-  m_pb=std::make_shared<AMACv2>(0,std::unique_ptr<EndeavourRawITSDAQ>(new EndeavourRawITSDAQ(m_com)));
+  for(uint32_t i=0; i<m_pb_commid.size(); i++)
+    {
+      m_pbs.push_back(
+		      std::make_shared<AMACv2>(m_pb_commid[i],
+					       std::unique_ptr<EndeavourRawITSDAQ>(new EndeavourRawITSDAQ(m_com))
+					       )
+		      );
+      m_pbs.back()->setPADID(m_pb_idpads[i]);
+    }
 
   // CAL
   std::shared_ptr<I2CCom> i2c=std::make_shared<ITSDAQI2CCom>(0x56, m_com);
+  i2c->write_block({0x4F,0x00,0x3F}); // Power up all channels
   setCalDAC(std::make_shared<AD56X9>(1.5, AD56X9::Model::AD5629, i2c));
 }
 
@@ -65,9 +83,9 @@ double PBv3TBModule::getVin()
 
 std::shared_ptr<AMACv2> PBv3TBModule::getPB(uint8_t pbNum)
 {
-  if(pbNum>=1)
-    throw OutOfRangeException(pbNum,0,0);
-  return m_pb;
+  if(pbNum>=m_pbs.size())
+    throw OutOfRangeException(pbNum,0,m_pbs.size()-1);
+  return m_pbs[pbNum];
 }
 
 void PBv3TBModule::loadOn(uint8_t pbNum)
diff --git a/pbv3/PBv3TBModule.h b/pbv3/PBv3TBModule.h
index fba3fba5..de91132e 100644
--- a/pbv3/PBv3TBModule.h
+++ b/pbv3/PBv3TBModule.h
@@ -60,11 +60,16 @@ private:
   //! Port to access the ITSDAQ firmware
   uint32_t m_port=60003;
 
+  //! AMAC padid
+  std::vector<uint8_t> m_pb_idpads;
+  //! Comm ID
+  std::vector<uint8_t> m_pb_commid;
+
   /** @} */
 
   // Objects
   std::shared_ptr<ITSDAQCom> m_com;
-  std::shared_ptr<AMACv2> m_pb;
+  std::vector<std::shared_ptr<AMACv2>> m_pbs;
 };
 
 #endif // PBV3TBMODULE_H
-- 
GitLab


From 277c212c4dab60ca83baa7e9386ca8f4b285f4c1 Mon Sep 17 00:00:00 2001
From: Berkeley Strippers <strips@lbl>
Date: Thu, 20 Aug 2020 15:02:48 -0700
Subject: [PATCH 10/29] EndeavourComException should inherit public
 ComException.

---
 pbv3/EndeavourComException.h | 2 +-
 pbv3/ITSDAQComException.h    | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/pbv3/EndeavourComException.h b/pbv3/EndeavourComException.h
index de8ba058..df28f1aa 100644
--- a/pbv3/EndeavourComException.h
+++ b/pbv3/EndeavourComException.h
@@ -7,7 +7,7 @@
 
 #include "ComException.h"
 
-class EndeavourComException : ComException
+class EndeavourComException : public ComException
 {
 public:
   EndeavourComException(const std::string& msg);
diff --git a/pbv3/ITSDAQComException.h b/pbv3/ITSDAQComException.h
index c7a1262c..ff258804 100644
--- a/pbv3/ITSDAQComException.h
+++ b/pbv3/ITSDAQComException.h
@@ -7,7 +7,7 @@
 
 #include "ComException.h"
 
-class ITSDAQComException : ComException
+class ITSDAQComException : public ComException
 {
 public:
   ITSDAQComException(const std::string& msg);
-- 
GitLab


From 82037211b2e55ad0c71209ae245d887288226742 Mon Sep 17 00:00:00 2001
From: Berkeley Strippers <strips@lbl>
Date: Thu, 20 Aug 2020 15:05:01 -0700
Subject: [PATCH 11/29] Increment timeout in ITSDAQCom.

---
 pbv3/ITSDAQCom.cpp | 14 ++++++++------
 1 file changed, 8 insertions(+), 6 deletions(-)

diff --git a/pbv3/ITSDAQCom.cpp b/pbv3/ITSDAQCom.cpp
index 59d30776..f9f5e2d5 100644
--- a/pbv3/ITSDAQCom.cpp
+++ b/pbv3/ITSDAQCom.cpp
@@ -72,13 +72,13 @@ ITSDAQPacket ITSDAQCom::receive()
   FD_ZERO(&selList);
   FD_SET(m_socket, &selList);
 
-  timeval timeOutVal;
-  timeOutVal.tv_sec = 0;
-  timeOutVal.tv_usec = 1000 * 100; // 100 ms
+  timeval timeOutVal;  // 2s
+  timeOutVal.tv_sec = 2;
+  timeOutVal.tv_usec = 0;
 
   int32_t result = select(m_socket + 1, &selList, NULL, NULL, &timeOutVal);
   if(result!=1)
-    throw ITSDAQComException("No or too many replies from FPGA!");
+    throw ITSDAQComException("No or too many replies from FPGA: "+std::to_string(result));
 
   std::vector<uint8_t> buffer(128);
   ssize_t rsize=::recv(m_socket, &buffer[0], 128, 0);
@@ -89,10 +89,12 @@ ITSDAQPacket ITSDAQCom::receive()
   for(uint32_t i=0;i<rsize/2;i++)
       rawdata[i]=(buffer[2*i+0]<<8)|(buffer[2*i+1]<<0);
 
-  /*std::cout << "start receive" << std::endl;
+  /*
+  std::cout << "start receive" << std::endl;
   for(uint16_t x : rawdata)
     std::cout << "0x" << std::hex << std::setw(4) << std::setfill('0') << (uint32_t)x << std::dec << std::endl;
-  std::cout << "end receive" << std::endl;*/
+  std::cout << "end receive" << std::endl;
+  */
 
   return ITSDAQPacket(rawdata);
 }
-- 
GitLab


From 5169b617a879392b6e50190a4b7c29c06c4b6bfe Mon Sep 17 00:00:00 2001
From: Berkeley Strippers <strips@lbl>
Date: Thu, 20 Aug 2020 15:05:16 -0700
Subject: [PATCH 12/29] Tweak powerup sequence in module-powerOn

---
 scripts/module-powerOff.sh | 13 ++++++-------
 scripts/module-powerOn.sh  | 12 ++++++------
 2 files changed, 12 insertions(+), 13 deletions(-)

diff --git a/scripts/module-powerOff.sh b/scripts/module-powerOff.sh
index a479617f..668fecc2 100755
--- a/scripts/module-powerOff.sh
+++ b/scripts/module-powerOff.sh
@@ -37,6 +37,12 @@ OPTS="-e ${TBCONFIG}"
 ./bin/pbv3_field ${OPTS} write CntSetCHV0en 0 || exit 1
 ./bin/pbv3_field ${OPTS} write CntSetHV0en 0 || exit 1
 
+# resetB
+./bin/pbv3_field ${OPTS} write RstCntHyHCCresetB 0 || exit 1
+./bin/pbv3_field ${OPTS} write RstCntCHyHCCresetB 0 || exit 1
+./bin/pbv3_field ${OPTS} write RstCntHxHCCresetB 0 || exit 1
+./bin/pbv3_field ${OPTS} write RstCntCHxHCCresetB 0 || exit 1
+
 # Hybrid LDOs
 ./bin/pbv3_field ${OPTS} write CntSetHyLDO0en 0 || exit 1
 ./bin/pbv3_field ${OPTS} write CntSetCHyLDO0en 0 || exit 1
@@ -52,13 +58,6 @@ OPTS="-e ${TBCONFIG}"
 ./bin/pbv3_field ${OPTS} write CntSetHxLDO2en 0 || exit 1
 ./bin/pbv3_field ${OPTS} write CntSetCHxLDO2en 0 || exit 1
 
-# resetB
-./bin/pbv3_field ${OPTS} write RstCntHyHCCresetB 0 || exit 1
-./bin/pbv3_field ${OPTS} write RstCntCHyHCCresetB 0 || exit 1
-./bin/pbv3_field ${OPTS} write RstCntHxHCCresetB 0 || exit 1
-./bin/pbv3_field ${OPTS} write RstCntCHxHCCresetB 0 || exit 1
-
-
 # DCDC
 ./bin/pbv3_field ${OPTS} write DCDCen 0 || exit 1
 ./bin/pbv3_field ${OPTS} write DCDCenC 0 || exit 1
diff --git a/scripts/module-powerOn.sh b/scripts/module-powerOn.sh
index 3e28e3e3..a6e1757d 100755
--- a/scripts/module-powerOn.sh
+++ b/scripts/module-powerOn.sh
@@ -41,12 +41,6 @@ OPTS="-e ${TBCONFIG}"
 #
 # Enable the Hybrid
 
-# resetB
-./bin/pbv3_field ${OPTS} write RstCntHyHCCresetB 1 || exit 1
-./bin/pbv3_field ${OPTS} write RstCntCHyHCCresetB 1 || exit 1
-./bin/pbv3_field ${OPTS} write RstCntHxHCCresetB 1 || exit 1
-./bin/pbv3_field ${OPTS} write RstCntCHxHCCresetB 1 || exit 1
-
 # Hybrid LDOs
 ./bin/pbv3_field ${OPTS} write CntSetHyLDO0en 1 || exit 1
 ./bin/pbv3_field ${OPTS} write CntSetCHyLDO0en 1 || exit 1
@@ -62,6 +56,12 @@ OPTS="-e ${TBCONFIG}"
 ./bin/pbv3_field ${OPTS} write CntSetHxLDO2en 1 || exit 1
 ./bin/pbv3_field ${OPTS} write CntSetCHxLDO2en 1 || exit 1
 
+# resetB
+./bin/pbv3_field ${OPTS} write RstCntHyHCCresetB 1 || exit 1
+./bin/pbv3_field ${OPTS} write RstCntCHyHCCresetB 1 || exit 1
+./bin/pbv3_field ${OPTS} write RstCntHxHCCresetB 1 || exit 1
+./bin/pbv3_field ${OPTS} write RstCntCHxHCCresetB 1 || exit 1
+
 # HV mux
 ./bin/pbv3_field ${OPTS} write CntSetCHV0en 1 || exit 1
 ./bin/pbv3_field ${OPTS} write CntSetHV0en 1 || exit 1
-- 
GitLab


From 91ca891462f420d479bfda181f3987734640f9bb Mon Sep 17 00:00:00 2001
From: Berkeley Strippers <strips@lbl>
Date: Thu, 20 Aug 2020 15:05:36 -0700
Subject: [PATCH 13/29] Work on monitor code.

---
 itsdaq/monitor.C | 165 ++++++++++++++++++++++++++---------------------
 1 file changed, 91 insertions(+), 74 deletions(-)

diff --git a/itsdaq/monitor.C b/itsdaq/monitor.C
index 7023abad..6a003fb8 100644
--- a/itsdaq/monitor.C
+++ b/itsdaq/monitor.C
@@ -82,91 +82,103 @@ public:
 	if(!m_e->m[n]->present) continue;
 
 	// Peform HCC register read
-	for(const std::pair<int, std::string>& kv : hcc_regs)
-	  {
-	    br_hccregs[n]->resetValue(kv.first);
+	run_hcc_registers(n);
 
-	    m_e->ReadChipRegister(kv.first+256);
+	// Peform ABC register read
+	run_abc_registers(n);
 
-	    // Find packets in streams
-	    std::vector<std::vector<uint8_t>> packets;
-	    find_hcc_packets(n, packets);
+	// Fill tree
+	m_tree->Fill();
+      }
+  }
 
-	    // Decode packets
-	    for(const std::vector<uint8_t>& packet : packets)
-	      {
-		StarChipPacket p(false);
-		p.add_word(0x13c);
-		for(uint8_t byte : packet)
-		  p.add_word(byte);
-		p.add_word(0x1dc);
-		p.parse();
-
-		if(p.type!=TYP_HCC_RR)
-		  {
-		    std::cerr << "WARNING! Unexpected packet type: " << packet_type_names[p.type] << std::endl;
-		    continue;
-		  }
+  void run_hcc_registers(int n)
+  {
+    for(const std::pair<int, std::string>& kv : hcc_regs)
+      {
+	br_hccregs[n]->resetValue(kv.first);
 
-		if(p.address!=kv.first)
-		  {
-		    std::cerr << "ERROR! Wrong address: " << (uint32_t)p.address << "(expected " << (uint32_t)kv.first << ")" << std::endl;
-		    continue;
-		  }
+	m_e->ReadChipRegister(kv.first+256);
+
+	// Find packets in streams
+	std::vector<std::vector<uint8_t>> packets;
+	find_hcc_packets(n, packets);
 
-		br_hccregs[n]->setValue(kv.first, p.value);
+	// Decode packets
+	for(const std::vector<uint8_t>& packet : packets)
+	  {
+	    StarChipPacket p(false);
+	    p.add_word(0x13c);
+	    for(uint8_t byte : packet)
+	      p.add_word(byte);
+	    p.add_word(0x1dc);
+	    p.parse();
+
+	    if(p.type!=TYP_HCC_RR)
+	      {
+		std::cerr << "WARNING! Unexpected packet type: " << packet_type_names[p.type] << std::endl;
+		continue;
 	      }
 
-	    // Peform ABC register read
-	    bool v1=(get_chipset()==9);
-	    const std::unordered_map<int, std::string>& abc_regs=(v1)?(abcv1_regs):(abcv0_regs);
-	    for(const std::pair<int, std::string>& kv : abc_regs)
+	    if(p.address!=kv.first)
 	      {
-		for(int a=0; a<m_e->GetNChips(); ++a)
-		  br_abcregs[n][a]->resetValue(kv.first);
+		std::cerr << "ERROR! Wrong address: " << (uint32_t)p.address << "(expected " << (uint32_t)kv.first << ")" << std::endl;
+		continue;
+	      }
 
-		m_e->ReadChipRegister(kv.first);
+	    br_hccregs[n]->setValue(kv.first, p.value);
+	  }
+      }
+  }
 
-		// Find packets in streams
-		std::vector<std::vector<uint8_t>> packets;
-		find_hcc_packets(n, packets);
+  void run_abc_registers(int n)
+  {
+    if(m_e->GetNChips()==0) return; // No ABC's
 
-		// Decode packets
-		for(const std::vector<uint8_t>& packet : packets)
-		  {
-		    StarChipPacket p(false);
-		    p.add_word(0x13c);
-		    for(uint8_t byte : packet)
-		      p.add_word(byte);
-		    p.add_word(0x1dc);
-		    p.parse();
-
-		    if(p.type!=TYP_ABC_RR)
-		      {
-			std::cerr << "WARNING! Unexpected packet type: " << packet_type_names[p.type] << std::endl;
-			continue;
-		      }
-
-		    if(p.address!=kv.first)
-		      {
-			std::cerr << "ERROR! Wrong address: " << (uint32_t)p.address << "(expected " << (uint32_t)kv.first << ")" << std::endl;
-			continue;
-		      }
-		    
-		    uint32_t abc_index=(p.abc_status>>12)&0xF;
-		    if(!br_abcregs[n][abc_index])
-		      {
-			std::cerr << "ERROR! Invalid ABC index: " << (uint32_t) p.channel_abc << std::endl;
-			continue;
-		      }
-
-		    br_abcregs[n][abc_index]->setValue(kv.first, p.value);
-		  }
+    bool v1=(get_chipset()==9);
+    const std::unordered_map<int, std::string>& abc_regs=(v1)?(abcv1_regs):(abcv0_regs);
+    for(const std::pair<int, std::string>& kv : abc_regs)
+      {
+	for(int a=0; a<m_e->GetNChips(); ++a)
+	  br_abcregs[n][a]->resetValue(kv.first);
+
+	m_e->ReadChipRegister(kv.first);
+
+	// Find packets in streams
+	std::vector<std::vector<uint8_t>> packets;
+	find_hcc_packets(n, packets);
+
+	// Decode packets
+	for(const std::vector<uint8_t>& packet : packets)
+	  {
+	    StarChipPacket p(false);
+	    p.add_word(0x13c);
+	    for(uint8_t byte : packet)
+	      p.add_word(byte);
+	    p.add_word(0x1dc);
+	    p.parse();
+
+	    if(p.type!=TYP_ABC_RR)
+	      {
+		std::cerr << "WARNING! Unexpected packet type: " << packet_type_names[p.type] << std::endl;
+		continue;
 	      }
-	  }
 
-	// Fill tree
-	m_tree->Fill();
+	    if(p.address!=kv.first)
+	      {
+		std::cerr << "ERROR! Wrong address: " << (uint32_t)p.address << "(expected " << (uint32_t)kv.first << ")" << std::endl;
+		continue;
+	      }
+
+	    uint32_t abc_index=(p.abc_status>>12)&0xF;
+	    if(!br_abcregs[n][abc_index])
+	      {
+		std::cerr << "ERROR! Invalid ABC index: " << (uint32_t) p.channel_abc << std::endl;
+		continue;
+	      }
+
+	    br_abcregs[n][abc_index]->setValue(kv.first, p.value);
+	  }
       }
   }
 
@@ -390,8 +402,14 @@ void monitor()
   //
   // Initialize ITSDAQ and Hybrids
   e->Restart();
+
+  e->ConfigureVariable(10048,0xffff);
+  e->ConfigureVariable(10011,0x22);
+  e->ConfigureVariable(0,53,1);
+  e->ExecuteConfigs();
+
   hcc_star_reg_write(16,4);
-  hcc_star_reg_write(17,0xf0004223); // Homer
+  hcc_star_reg_write(17,0xf0004a0c); // BETSEE
   abc_star_fast_command(2,2);
   abc_star_fast_command(3,0);
   e->ExecuteConfigs();
@@ -403,7 +421,6 @@ void monitor()
   hcc_star_hpr_stop();
   e->ExecuteConfigs();
 
-
   //
   // RUN ME!
   auto t_bigloopstart = std::chrono::system_clock::now();
-- 
GitLab


From fd9594911beaf751ec7a0912e6046707f78fce9f Mon Sep 17 00:00:00 2001
From: Berkeley Strippers <strips@lbl>
Date: Thu, 20 Aug 2020 15:08:25 -0700
Subject: [PATCH 14/29] Tweaks to run script.

---
 scripts/module-run.sh | 9 ++++++---
 1 file changed, 6 insertions(+), 3 deletions(-)

diff --git a/scripts/module-run.sh b/scripts/module-run.sh
index bdf15efd..5cf8900f 100755
--- a/scripts/module-run.sh
+++ b/scripts/module-run.sh
@@ -26,7 +26,7 @@ function cleanup() {
 	ps -p ${ITSDAQPID} && kill -- -${ITSDAQPID} 
     fi
     if [ ! -z "${PBPID}" ]; then
-	ps -p ${PBPID} && kill -- -${PBPID}
+    	ps -p ${PBPID} && kill -- -${PBPID}
     fi
     exit 0
 }
@@ -90,6 +90,8 @@ fi
 # Power Hybrids
 ./scripts/module-powerOn.sh ${OPTS} || exit 2
 
+sleep 10
+
 #
 # Start monitoring loops
 
@@ -117,11 +119,12 @@ do
 
     ps -p ${PBPID} -o pid= > /dev/null
     if [ ${?} != 0 ]; then
-	echo "Powerboard process has completed"
-	break
+    	echo "Powerboard process has completed"
+    	break
     fi
 
     sleep 1
 done
 
+sleep 60 # Log a bit more data
 cleanup
-- 
GitLab


From 4a9252a14ea207452a8b4b8398393ccb9f103de3 Mon Sep 17 00:00:00 2001
From: Karol Krizka <kkrizka@gmail.com>
Date: Mon, 24 Aug 2020 16:20:44 -0700
Subject: [PATCH 15/29] Add whole register definitions

---
 pbv3/AMACv2.cpp    |   27 +-
 pbv3/AMACv2.h      |    1 +
 pbv3/AMACv2Reg.cpp | 1034 +++++++++++++++++++++++++-------------------
 pbv3/AMACv2Reg.h   |    7 +-
 4 files changed, 617 insertions(+), 452 deletions(-)

diff --git a/pbv3/AMACv2.cpp b/pbv3/AMACv2.cpp
index a989785d..d78d4a53 100644
--- a/pbv3/AMACv2.cpp
+++ b/pbv3/AMACv2.cpp
@@ -26,28 +26,32 @@ void AMACv2::init()
 void AMACv2::initRegisters()
 { 
   // Initialize registers with default values
-  for(auto fieldKV : regMap)
+  for(auto fieldKV : m_fieldMap)
     {
       if((this->*fieldKV.second).canBeWrittenField())
 	(this->*fieldKV.second).writeDefaultVal();
     }
 
   // Write AMAC registers into the chip
-  for(uint reg=0;reg<AMACv2Reg::numRegs;reg++)
+  for(const std::pair<uint32_t, rw_t>& reg : AMACv2Reg::Registers)
     {
-      EndeavourCom::write_reg(reg, getReg(reg));
-      usleep(10);
+      if(reg.second!=RW)
+	continue;
+
+      EndeavourCom::write_reg(reg.first, getReg(reg.first));
     }
 }
 
 void AMACv2::loadRegisters()
 { 
   // Load register map with current values
-  for(uint reg=0;reg<AMACv2Reg::numRegs;reg++)
+  for(const std::pair<uint32_t, rw_t>& reg : AMACv2Reg::Registers)
     {
-      uint32_t value=EndeavourCom::read_reg(reg);
-      setReg(reg, value);
-      usleep(10);
+      if(reg.second!=RW && reg.second!=RO)
+	continue;
+
+      uint32_t value=EndeavourCom::read_reg(reg.first);
+      setReg(reg.first, value);
     }
 }
 
@@ -100,6 +104,13 @@ void AMACv2::write_reg(unsigned int address, unsigned int data)
   usleep(1e4);
 }
 
+unsigned int AMACv2::read_reg(unsigned int address)
+{
+  uint32_t value=EndeavourCom::read_reg(address);
+  setReg(address, value);
+  return value;
+}
+
 void AMACv2::setPADID(uint8_t padid)
 {
   m_padid=padid;
diff --git a/pbv3/AMACv2.h b/pbv3/AMACv2.h
index 290b3780..423b3714 100644
--- a/pbv3/AMACv2.h
+++ b/pbv3/AMACv2.h
@@ -23,6 +23,7 @@ public:
   bool isCommIDSet();
 
   virtual void write_reg(unsigned int address, unsigned int data);
+  virtual unsigned int read_reg(unsigned int address);
 
   void wrField(AMACv2Field AMACv2Reg::* ref, uint32_t data);
   void wrField(const std::string& fieldName, uint32_t data);
diff --git a/pbv3/AMACv2Reg.cpp b/pbv3/AMACv2Reg.cpp
index 24643438..fef6aa4d 100644
--- a/pbv3/AMACv2Reg.cpp
+++ b/pbv3/AMACv2Reg.cpp
@@ -91,6 +91,156 @@ void AMACv2Field::writeRaw(const uint32_t& cfgBits)
 uint8_t AMACv2Field::addr() const
 { return m_regNbr; }
 
+const std::unordered_map<uint32_t, rw_t> AMACv2Reg::Registers =
+  {
+    {  0, RO},
+    {  1, RO},
+    {  2, RO},
+    {  3, RO},
+    {  4, RO},
+    {  5, RO},
+    {  6, RO},
+    {  7, RO},
+
+    { 10, RO},
+    { 11, RO},
+    { 12, RO},
+    { 13, RO},
+    { 14, RO},
+    { 15, RO},
+
+    { 31, RO},
+
+    { 32, WO},
+    { 33, WO},
+    { 34, WO},
+
+    { 40, RW},
+    { 41, RW},
+    { 42, RW},
+    { 43, RW},
+    { 44, RW},
+    { 45, RW},
+    { 46, RW},
+    { 47, RW},
+    { 48, RW},
+    { 49, RW},
+    { 50, RW},
+    { 51, RW},
+    { 52, RW},
+    { 53, RW},
+    { 54, RW},
+    { 55, RW},
+    { 56, RW},
+    { 57, RW},
+
+    { 60, RW},
+    { 61, RW},
+    { 62, RW},
+    { 63, RW},
+    { 64, RW},
+    { 65, RW},
+
+    { 70, RW},
+    { 71, RW},
+    { 72, RW},
+    { 73, RW},
+    { 74, RW},
+    { 75, RW},
+    { 76, RW},
+    { 77, RW},
+    { 78, RW},
+    { 79, RW},
+    { 80, RW},
+    { 81, RW},
+    { 82, RW},
+    { 83, RW},
+    { 84, RW},
+    { 85, RW},
+    { 86, RW},
+    { 87, RW},
+    { 88, RW},
+    { 89, RW},
+    { 90, RW},
+    { 91, RW},
+    { 92, RW},
+    { 93, RW},
+    { 94, RW},
+    { 95, RW},
+
+    {100, RW},
+    {101, RW},
+    {102, RW},
+    {103, RW},
+    {104, RW},
+    {105, RW},
+    {106, RW},
+    {107, RW},
+    {108, RW},
+    {109, RW},
+    {110, RW},
+    {111, RW},
+    {112, RW},
+    {113, RW},
+    {114, RW},
+    {115, RW},
+    {116, RW},
+    {117, RW},
+    {118, RW},
+    {119, RW},
+    {120, RW},
+    {121, RW},
+    {122, RW},
+    {123, RW},
+    {124, RW},
+    {125, RW},
+    {126, RW},
+    {127, RW},
+    {128, RW},
+    {129, RW},
+    {130, RW},
+    {131, RW},
+    {132, RW},
+    {133, RW},
+    {134, RW},
+    {135, RW},
+    {136, RW},
+    {137, RW},
+    {138, RW},
+    {139, RW},
+    {140, RW},
+    {141, RW},
+    {142, RW},
+    {143, RW},
+    {144, RW},
+    {145, RW},
+    {146, RW},
+    {147, RW},
+    {148, RW},
+    {149, RW},
+    {150, RW},
+    {151, RW},
+    {152, RW},
+    {153, RW},
+    {154, RW},
+    {155, RW},
+    {156, RW},
+    {157, RW},
+    {158, RW},
+    {159, RW},
+    {160, RW},
+    {161, RW},
+    {162, RW},
+    {163, RW},
+    {164, RW},
+    {165, RW},
+    {166, RW},
+    {167, RW},
+    {168, RW},
+    {169, RW},
+    {170, RW},
+    {171, RW}
+  };
 
 AMACv2Reg::AMACv2Reg()
 {
@@ -102,582 +252,582 @@ void AMACv2Reg::init()
 	
   for (unsigned int i=0; i<numRegs; i++) m_cfg[i] = 0;
 	
-  StatusAM  .initReg(m_cfg, RO, 0, 1, 31, 0, "StatusAM"  ); regMap["StatusAM"  ] = &AMACv2Reg::StatusAM;
-  StatusWARN.initReg(m_cfg, RO, 0, 1, 29, 0, "StatusWARN"); regMap["StatusWARN"] = &AMACv2Reg::StatusWARN;
-  StatusDCDC.initReg(m_cfg, RO, 0, 1, 28, 0, "StatusDCDC"); regMap["StatusDCDC"] = &AMACv2Reg::StatusDCDC;
-  StatusHV3.initReg(m_cfg, RO, 0, 1, 27, 0, "StatusHV3"); regMap["StatusHV3"] = &AMACv2Reg::StatusHV3;
-  StatusHV2.initReg(m_cfg, RO, 0, 1, 26, 0, "StatusHV2"); regMap["StatusHV2"] = &AMACv2Reg::StatusHV2;
-  StatusHV1.initReg(m_cfg, RO, 0, 1, 25, 0, "StatusHV1"); regMap["StatusHV1"] = &AMACv2Reg::StatusHV1;
-  StatusHV0.initReg(m_cfg, RO, 0, 1, 24, 0, "StatusHV0"); regMap["StatusHV0"] = &AMACv2Reg::StatusHV0;
-  StatusY2LDO.initReg(m_cfg, RO, 0, 1, 22, 0, "StatusY2LDO"); regMap["StatusY2LDO"] = &AMACv2Reg::StatusY2LDO;
-  StatusY1LDO.initReg(m_cfg, RO, 0, 1, 21, 0, "StatusY1LDO"); regMap["StatusY1LDO"] = &AMACv2Reg::StatusY1LDO;
-  StatusY0LDO.initReg(m_cfg, RO, 0, 1, 20, 0, "StatusY0LDO"); regMap["StatusY0LDO"] = &AMACv2Reg::StatusY0LDO;
-  StatusX2LDO.initReg(m_cfg, RO, 0, 1, 18, 0, "StatusX2LDO"); regMap["StatusX2LDO"] = &AMACv2Reg::StatusX2LDO;
-  StatusX1LDO.initReg(m_cfg, RO, 0, 1, 17, 0, "StatusX1LDO"); regMap["StatusX1LDO"] = &AMACv2Reg::StatusX1LDO;
-  StatusX0LDO.initReg(m_cfg, RO, 0, 1, 16, 0, "StatusX0LDO"); regMap["StatusX0LDO"] = &AMACv2Reg::StatusX0LDO;
-  StatusGPI.initReg(m_cfg, RO, 0, 1, 12, 0, "StatusGPI"); regMap["StatusGPI"] = &AMACv2Reg::StatusGPI;
-  StatusPGOOD.initReg(m_cfg, RO, 0, 1, 8, 0, "StatusPGOOD"); regMap["StatusPGOOD"] = &AMACv2Reg::StatusPGOOD;
-  StatusILockWARN.initReg(m_cfg, RO, 0, 1, 5, 0, "StatusILockWARN"); regMap["StatusILockWARN"] = &AMACv2Reg::StatusILockWARN;
-  StatusILockDCDC.initReg(m_cfg, RO, 0, 1, 4, 0, "StatusILockDCDC"); regMap["StatusILockDCDC"] = &AMACv2Reg::StatusILockDCDC;
-  StatusILockHV2.initReg(m_cfg, RO, 0, 1, 3, 0, "StatusILockHV2"); regMap["StatusILockHV2"] = &AMACv2Reg::StatusILockHV2;
-  StatusILockHV2.initReg(m_cfg, RO, 0, 1, 2, 0, "StatusILockHV2"); regMap["StatusILockHV2"] = &AMACv2Reg::StatusILockHV2;
-  StatusILockYLDO.initReg(m_cfg, RO, 0, 1, 1, 0, "StatusILockYLDO"); regMap["StatusILockYLDO"] = &AMACv2Reg::StatusILockYLDO;
-  StatusILockxLDO.initReg(m_cfg, RO, 0, 1, 0, 0, "StatusILockxLDO"); regMap["StatusILockxLDO"] = &AMACv2Reg::StatusILockxLDO;
+  StatusAM  .initReg(m_cfg, RO, 0, 1, 31, 0, "StatusAM"  ); m_fieldMap["StatusAM"  ] = &AMACv2Reg::StatusAM;
+  StatusWARN.initReg(m_cfg, RO, 0, 1, 29, 0, "StatusWARN"); m_fieldMap["StatusWARN"] = &AMACv2Reg::StatusWARN;
+  StatusDCDC.initReg(m_cfg, RO, 0, 1, 28, 0, "StatusDCDC"); m_fieldMap["StatusDCDC"] = &AMACv2Reg::StatusDCDC;
+  StatusHV3.initReg(m_cfg, RO, 0, 1, 27, 0, "StatusHV3"); m_fieldMap["StatusHV3"] = &AMACv2Reg::StatusHV3;
+  StatusHV2.initReg(m_cfg, RO, 0, 1, 26, 0, "StatusHV2"); m_fieldMap["StatusHV2"] = &AMACv2Reg::StatusHV2;
+  StatusHV1.initReg(m_cfg, RO, 0, 1, 25, 0, "StatusHV1"); m_fieldMap["StatusHV1"] = &AMACv2Reg::StatusHV1;
+  StatusHV0.initReg(m_cfg, RO, 0, 1, 24, 0, "StatusHV0"); m_fieldMap["StatusHV0"] = &AMACv2Reg::StatusHV0;
+  StatusY2LDO.initReg(m_cfg, RO, 0, 1, 22, 0, "StatusY2LDO"); m_fieldMap["StatusY2LDO"] = &AMACv2Reg::StatusY2LDO;
+  StatusY1LDO.initReg(m_cfg, RO, 0, 1, 21, 0, "StatusY1LDO"); m_fieldMap["StatusY1LDO"] = &AMACv2Reg::StatusY1LDO;
+  StatusY0LDO.initReg(m_cfg, RO, 0, 1, 20, 0, "StatusY0LDO"); m_fieldMap["StatusY0LDO"] = &AMACv2Reg::StatusY0LDO;
+  StatusX2LDO.initReg(m_cfg, RO, 0, 1, 18, 0, "StatusX2LDO"); m_fieldMap["StatusX2LDO"] = &AMACv2Reg::StatusX2LDO;
+  StatusX1LDO.initReg(m_cfg, RO, 0, 1, 17, 0, "StatusX1LDO"); m_fieldMap["StatusX1LDO"] = &AMACv2Reg::StatusX1LDO;
+  StatusX0LDO.initReg(m_cfg, RO, 0, 1, 16, 0, "StatusX0LDO"); m_fieldMap["StatusX0LDO"] = &AMACv2Reg::StatusX0LDO;
+  StatusGPI.initReg(m_cfg, RO, 0, 1, 12, 0, "StatusGPI"); m_fieldMap["StatusGPI"] = &AMACv2Reg::StatusGPI;
+  StatusPGOOD.initReg(m_cfg, RO, 0, 1, 8, 0, "StatusPGOOD"); m_fieldMap["StatusPGOOD"] = &AMACv2Reg::StatusPGOOD;
+  StatusILockWARN.initReg(m_cfg, RO, 0, 1, 5, 0, "StatusILockWARN"); m_fieldMap["StatusILockWARN"] = &AMACv2Reg::StatusILockWARN;
+  StatusILockDCDC.initReg(m_cfg, RO, 0, 1, 4, 0, "StatusILockDCDC"); m_fieldMap["StatusILockDCDC"] = &AMACv2Reg::StatusILockDCDC;
+  StatusILockHV2.initReg(m_cfg, RO, 0, 1, 3, 0, "StatusILockHV2"); m_fieldMap["StatusILockHV2"] = &AMACv2Reg::StatusILockHV2;
+  StatusILockHV2.initReg(m_cfg, RO, 0, 1, 2, 0, "StatusILockHV2"); m_fieldMap["StatusILockHV2"] = &AMACv2Reg::StatusILockHV2;
+  StatusILockYLDO.initReg(m_cfg, RO, 0, 1, 1, 0, "StatusILockYLDO"); m_fieldMap["StatusILockYLDO"] = &AMACv2Reg::StatusILockYLDO;
+  StatusILockxLDO.initReg(m_cfg, RO, 0, 1, 0, 0, "StatusILockxLDO"); m_fieldMap["StatusILockxLDO"] = &AMACv2Reg::StatusILockxLDO;
   // 1 - HxFlags
-  HxFlagsHi.initReg(m_cfg, RO, 0, 16, 16, 1, "HxFlagsHi"); regMap["HxFlagsHi"] = &AMACv2Reg::HxFlagsHi;
-  HxFlagsLo.initReg(m_cfg, RO, 0, 16, 0, 1, "HxFlagsLo"); regMap["HxFlagsLo"] = &AMACv2Reg::HxFlagsLo;
+  HxFlagsHi.initReg(m_cfg, RO, 0, 16, 16, 1, "HxFlagsHi"); m_fieldMap["HxFlagsHi"] = &AMACv2Reg::HxFlagsHi;
+  HxFlagsLo.initReg(m_cfg, RO, 0, 16, 0, 1, "HxFlagsLo"); m_fieldMap["HxFlagsLo"] = &AMACv2Reg::HxFlagsLo;
   // 2 - HyFlags
-  HyFlagsHi.initReg(m_cfg, RO, 0, 16, 16, 2, "HyFlagsHi"); regMap["HyFlagsHi"] = &AMACv2Reg::HyFlagsHi;
-  HyFlagsLo.initReg(m_cfg, RO, 0, 16, 0, 2, "HyFlagsLo"); regMap["HyFlagsLo"] = &AMACv2Reg::HyFlagsLo;
+  HyFlagsHi.initReg(m_cfg, RO, 0, 16, 16, 2, "HyFlagsHi"); m_fieldMap["HyFlagsHi"] = &AMACv2Reg::HyFlagsHi;
+  HyFlagsLo.initReg(m_cfg, RO, 0, 16, 0, 2, "HyFlagsLo"); m_fieldMap["HyFlagsLo"] = &AMACv2Reg::HyFlagsLo;
   // 3 - HV0Flags
-  HV0FlagsHi.initReg(m_cfg, RO, 0, 16, 16, 3, "HV0FlagsHi"); regMap["HV0FlagsHi"] = &AMACv2Reg::HV0FlagsHi;
-  HV0FlagsLo.initReg(m_cfg, RO, 0, 16, 0, 3, "HV0FlagsLo"); regMap["HV0FlagsLo"] = &AMACv2Reg::HV0FlagsLo;
+  HV0FlagsHi.initReg(m_cfg, RO, 0, 16, 16, 3, "HV0FlagsHi"); m_fieldMap["HV0FlagsHi"] = &AMACv2Reg::HV0FlagsHi;
+  HV0FlagsLo.initReg(m_cfg, RO, 0, 16, 0, 3, "HV0FlagsLo"); m_fieldMap["HV0FlagsLo"] = &AMACv2Reg::HV0FlagsLo;
   // 4 - HV2Flags
-  HV2FlagsHi.initReg(m_cfg, RO, 0, 16, 16, 4, "HV2FlagsHi"); regMap["HV2FlagsHi"] = &AMACv2Reg::HV2FlagsHi;
-  HV2FlagsLo.initReg(m_cfg, RO, 0, 16, 0, 4, "HV2FlagsLo"); regMap["HV2FlagsLo"] = &AMACv2Reg::HV2FlagsLo;
+  HV2FlagsHi.initReg(m_cfg, RO, 0, 16, 16, 4, "HV2FlagsHi"); m_fieldMap["HV2FlagsHi"] = &AMACv2Reg::HV2FlagsHi;
+  HV2FlagsLo.initReg(m_cfg, RO, 0, 16, 0, 4, "HV2FlagsLo"); m_fieldMap["HV2FlagsLo"] = &AMACv2Reg::HV2FlagsLo;
   // 5 - DCDCflags
-  DCDCflagsHi.initReg(m_cfg, RO, 0, 16, 16, 5, "DCDCflagsHi"); regMap["DCDCflagsHi"] = &AMACv2Reg::DCDCflagsHi;
-  DCDCflagsLo.initReg(m_cfg, RO, 0, 16, 0, 5, "DCDCflagsLo"); regMap["DCDCflagsLo"] = &AMACv2Reg::DCDCflagsLo;
+  DCDCflagsHi.initReg(m_cfg, RO, 0, 16, 16, 5, "DCDCflagsHi"); m_fieldMap["DCDCflagsHi"] = &AMACv2Reg::DCDCflagsHi;
+  DCDCflagsLo.initReg(m_cfg, RO, 0, 16, 0, 5, "DCDCflagsLo"); m_fieldMap["DCDCflagsLo"] = &AMACv2Reg::DCDCflagsLo;
   // 6 - WRNflags
-  WRNflagsHi.initReg(m_cfg, RO, 0, 16, 16, 6, "WRNflagsHi"); regMap["WRNflagsHi"] = &AMACv2Reg::WRNflagsHi;
-  WRNflagsLo.initReg(m_cfg, RO, 0, 16, 0, 6, "WRNflagsLo"); regMap["WRNflagsLo"] = &AMACv2Reg::WRNflagsLo;
+  WRNflagsHi.initReg(m_cfg, RO, 0, 16, 16, 6, "WRNflagsHi"); m_fieldMap["WRNflagsHi"] = &AMACv2Reg::WRNflagsHi;
+  WRNflagsLo.initReg(m_cfg, RO, 0, 16, 0, 6, "WRNflagsLo"); m_fieldMap["WRNflagsLo"] = &AMACv2Reg::WRNflagsLo;
   // 7 - SynFlags
-  SynFlagsWRN.initReg(m_cfg, RO, 0, 2, 20, 7, "SynFlagsWRN"); regMap["SynFlagsWRN"] = &AMACv2Reg::SynFlagsWRN;
-  SynFlagsDCDC.initReg(m_cfg, RO, 0, 2, 16, 7, "SynFlagsDCDC"); regMap["SynFlagsDCDC"] = &AMACv2Reg::SynFlagsDCDC;
-  SynFlagsHV2.initReg(m_cfg, RO, 0, 2, 12, 7, "SynFlagsHV2"); regMap["SynFlagsHV2"] = &AMACv2Reg::SynFlagsHV2;
-  SynFlagsHV2.initReg(m_cfg, RO, 0, 2, 8, 7, "SynFlagsHV2"); regMap["SynFlagsHV2"] = &AMACv2Reg::SynFlagsHV2;
-  SynFlagsHy.initReg(m_cfg, RO, 0, 2, 4, 7, "SynFlagsHy"); regMap["SynFlagsHy"] = &AMACv2Reg::SynFlagsHy;
-  SynFlagsHx.initReg(m_cfg, RO, 0, 2, 0, 7, "SynFlagsHx"); regMap["SynFlagsHx"] = &AMACv2Reg::SynFlagsHx;
+  SynFlagsWRN.initReg(m_cfg, RO, 0, 2, 20, 7, "SynFlagsWRN"); m_fieldMap["SynFlagsWRN"] = &AMACv2Reg::SynFlagsWRN;
+  SynFlagsDCDC.initReg(m_cfg, RO, 0, 2, 16, 7, "SynFlagsDCDC"); m_fieldMap["SynFlagsDCDC"] = &AMACv2Reg::SynFlagsDCDC;
+  SynFlagsHV2.initReg(m_cfg, RO, 0, 2, 12, 7, "SynFlagsHV2"); m_fieldMap["SynFlagsHV2"] = &AMACv2Reg::SynFlagsHV2;
+  SynFlagsHV2.initReg(m_cfg, RO, 0, 2, 8, 7, "SynFlagsHV2"); m_fieldMap["SynFlagsHV2"] = &AMACv2Reg::SynFlagsHV2;
+  SynFlagsHy.initReg(m_cfg, RO, 0, 2, 4, 7, "SynFlagsHy"); m_fieldMap["SynFlagsHy"] = &AMACv2Reg::SynFlagsHy;
+  SynFlagsHx.initReg(m_cfg, RO, 0, 2, 0, 7, "SynFlagsHx"); m_fieldMap["SynFlagsHx"] = &AMACv2Reg::SynFlagsHx;
   // 10 - Value0
-  Value0AMen.initReg(m_cfg, RO, 0, 1, 31, 10, "Value0AMen"); regMap["Value0AMen"] = &AMACv2Reg::Value0AMen;
-  Ch0Value.initReg(m_cfg, RO, 0, 10, 0, 10, "Ch0Value"); regMap["Ch0Value"] = &AMACv2Reg::Ch0Value;
-  Ch1Value.initReg(m_cfg, RO, 0, 10, 10, 10, "Ch1Value"); regMap["Ch1Value"] = &AMACv2Reg::Ch1Value;
-  Ch2Value.initReg(m_cfg, RO, 0, 10, 20, 10, "Ch2Value"); regMap["Ch2Value"] = &AMACv2Reg::Ch2Value;
+  Value0AMen.initReg(m_cfg, RO, 0, 1, 31, 10, "Value0AMen"); m_fieldMap["Value0AMen"] = &AMACv2Reg::Value0AMen;
+  Ch0Value.initReg(m_cfg, RO, 0, 10, 0, 10, "Ch0Value"); m_fieldMap["Ch0Value"] = &AMACv2Reg::Ch0Value;
+  Ch1Value.initReg(m_cfg, RO, 0, 10, 10, 10, "Ch1Value"); m_fieldMap["Ch1Value"] = &AMACv2Reg::Ch1Value;
+  Ch2Value.initReg(m_cfg, RO, 0, 10, 20, 10, "Ch2Value"); m_fieldMap["Ch2Value"] = &AMACv2Reg::Ch2Value;
   // 11 - Value1
-  Value1AMen.initReg(m_cfg, RO, 0, 1, 31, 11, "Value1AMen"); regMap["Value1AMen"] = &AMACv2Reg::Value1AMen;
-  Ch3Value.initReg(m_cfg, RO, 0, 10, 0, 11, "Ch3Value"); regMap["Ch3Value"] = &AMACv2Reg::Ch3Value;
-  Ch4Value.initReg(m_cfg, RO, 0, 10, 10, 11, "Ch4Value"); regMap["Ch4Value"] = &AMACv2Reg::Ch4Value;
-  Ch5Value.initReg(m_cfg, RO, 0, 10, 20, 11, "Ch5Value"); regMap["Ch5Value"] = &AMACv2Reg::Ch5Value;
+  Value1AMen.initReg(m_cfg, RO, 0, 1, 31, 11, "Value1AMen"); m_fieldMap["Value1AMen"] = &AMACv2Reg::Value1AMen;
+  Ch3Value.initReg(m_cfg, RO, 0, 10, 0, 11, "Ch3Value"); m_fieldMap["Ch3Value"] = &AMACv2Reg::Ch3Value;
+  Ch4Value.initReg(m_cfg, RO, 0, 10, 10, 11, "Ch4Value"); m_fieldMap["Ch4Value"] = &AMACv2Reg::Ch4Value;
+  Ch5Value.initReg(m_cfg, RO, 0, 10, 20, 11, "Ch5Value"); m_fieldMap["Ch5Value"] = &AMACv2Reg::Ch5Value;
   // 12 - Value2
-  Value2AMen.initReg(m_cfg, RO, 0, 1, 31, 12, "Value2AMen"); regMap["Value2AMen"] = &AMACv2Reg::Value2AMen;
-  Ch6Value.initReg(m_cfg, RO, 0, 10, 0, 12, "Ch6Value"); regMap["Ch6Value"] = &AMACv2Reg::Ch6Value;
-  Ch7Value.initReg(m_cfg, RO, 0, 10, 10, 12, "Ch7Value"); regMap["Ch7Value"] = &AMACv2Reg::Ch7Value;
-  Ch8Value.initReg(m_cfg, RO, 0, 10, 20, 12, "Ch8Value"); regMap["Ch8Value"] = &AMACv2Reg::Ch8Value;
+  Value2AMen.initReg(m_cfg, RO, 0, 1, 31, 12, "Value2AMen"); m_fieldMap["Value2AMen"] = &AMACv2Reg::Value2AMen;
+  Ch6Value.initReg(m_cfg, RO, 0, 10, 0, 12, "Ch6Value"); m_fieldMap["Ch6Value"] = &AMACv2Reg::Ch6Value;
+  Ch7Value.initReg(m_cfg, RO, 0, 10, 10, 12, "Ch7Value"); m_fieldMap["Ch7Value"] = &AMACv2Reg::Ch7Value;
+  Ch8Value.initReg(m_cfg, RO, 0, 10, 20, 12, "Ch8Value"); m_fieldMap["Ch8Value"] = &AMACv2Reg::Ch8Value;
   // 13 - Value3
-  Value3AMen.initReg(m_cfg, RO, 0, 1, 31, 13, "Value3AMen"); regMap["Value3AMen"] = &AMACv2Reg::Value3AMen;
-  Ch9Value.initReg(m_cfg, RO, 0, 10, 0, 13, "Ch9Value"); regMap["Ch9Value"] = &AMACv2Reg::Ch9Value;
-  Ch10Value.initReg(m_cfg, RO, 0, 10, 10, 13, "Ch10Value"); regMap["Ch10Value"] = &AMACv2Reg::Ch10Value;
-  Ch11Value.initReg(m_cfg, RO, 0, 10, 20, 13, "Ch11Value"); regMap["Ch11Value"] = &AMACv2Reg::Ch11Value;
+  Value3AMen.initReg(m_cfg, RO, 0, 1, 31, 13, "Value3AMen"); m_fieldMap["Value3AMen"] = &AMACv2Reg::Value3AMen;
+  Ch9Value.initReg(m_cfg, RO, 0, 10, 0, 13, "Ch9Value"); m_fieldMap["Ch9Value"] = &AMACv2Reg::Ch9Value;
+  Ch10Value.initReg(m_cfg, RO, 0, 10, 10, 13, "Ch10Value"); m_fieldMap["Ch10Value"] = &AMACv2Reg::Ch10Value;
+  Ch11Value.initReg(m_cfg, RO, 0, 10, 20, 13, "Ch11Value"); m_fieldMap["Ch11Value"] = &AMACv2Reg::Ch11Value;
   // 14 - Value4
-  Value4AMen.initReg(m_cfg, RO, 0, 1, 31, 14, "Value4AMen"); regMap["Value4AMen"] = &AMACv2Reg::Value4AMen;
-  Ch12Value.initReg(m_cfg, RO, 0, 10, 0, 14, "Ch12Value"); regMap["Ch12Value"] = &AMACv2Reg::Ch12Value;
-  Ch13Value.initReg(m_cfg, RO, 0, 10, 10, 14, "Ch13Value"); regMap["Ch13Value"] = &AMACv2Reg::Ch13Value;
-  Ch14Value.initReg(m_cfg, RO, 0, 10, 20, 14, "Ch14Value"); regMap["Ch14Value"] = &AMACv2Reg::Ch14Value;
+  Value4AMen.initReg(m_cfg, RO, 0, 1, 31, 14, "Value4AMen"); m_fieldMap["Value4AMen"] = &AMACv2Reg::Value4AMen;
+  Ch12Value.initReg(m_cfg, RO, 0, 10, 0, 14, "Ch12Value"); m_fieldMap["Ch12Value"] = &AMACv2Reg::Ch12Value;
+  Ch13Value.initReg(m_cfg, RO, 0, 10, 10, 14, "Ch13Value"); m_fieldMap["Ch13Value"] = &AMACv2Reg::Ch13Value;
+  Ch14Value.initReg(m_cfg, RO, 0, 10, 20, 14, "Ch14Value"); m_fieldMap["Ch14Value"] = &AMACv2Reg::Ch14Value;
   // 15 - Value5
-  Value5AMen.initReg(m_cfg, RO, 0, 1, 31, 15, "Value5AMen"); regMap["Value5AMen"] = &AMACv2Reg::Value5AMen;
-  Ch15Value.initReg(m_cfg, RO, 0, 10, 0, 15, "Ch15Value"); regMap["Ch15Value"] = &AMACv2Reg::Ch15Value;
+  Value5AMen.initReg(m_cfg, RO, 0, 1, 31, 15, "Value5AMen"); m_fieldMap["Value5AMen"] = &AMACv2Reg::Value5AMen;
+  Ch15Value.initReg(m_cfg, RO, 0, 10, 0, 15, "Ch15Value"); m_fieldMap["Ch15Value"] = &AMACv2Reg::Ch15Value;
   // 31 - SerNum
-  PadID.initReg(m_cfg, RO, 0, 5, 24, 31, "PadID"); regMap["PadID"] = &AMACv2Reg::PadID;
-  SerNum.initReg(m_cfg, RO, 0, 16, 0, 31, "SerNum"); regMap["SerNum"] = &AMACv2Reg::SerNum;
+  PadID.initReg(m_cfg, RO, 0, 5, 24, 31, "PadID"); m_fieldMap["PadID"] = &AMACv2Reg::PadID;
+  SerNum.initReg(m_cfg, RO, 0, 16, 0, 31, "SerNum"); m_fieldMap["SerNum"] = &AMACv2Reg::SerNum;
   // 32 - FlagResets
-  FlagResetWRN.initReg(m_cfg, WO, 0, 1, 5, 32, "FlagResetWRN"); regMap["FlagResetWRN"] = &AMACv2Reg::FlagResetWRN;
-  FlagResetDCDC.initReg(m_cfg, WO, 0, 1, 4, 32, "FlagResetDCDC"); regMap["FlagResetDCDC"] = &AMACv2Reg::FlagResetDCDC;
-  FlagResetHV2.initReg(m_cfg, WO, 0, 1, 3, 32, "FlagResetHV2"); regMap["FlagResetHV2"] = &AMACv2Reg::FlagResetHV2;
-  FlagResetHV0.initReg(m_cfg, WO, 0, 1, 2, 32, "FlagResetHV0"); regMap["FlagResetHV0"] = &AMACv2Reg::FlagResetHV0;
-  FlagResetXLDO.initReg(m_cfg, WO, 0, 1, 1, 32, "FlagResetXLDO"); regMap["FlagResetXLDO"] = &AMACv2Reg::FlagResetXLDO;
-  FlagResetYLDO.initReg(m_cfg, WO, 0, 1, 0, 32, "FlagResetYLDO"); regMap["FlagResetYLDO"] = &AMACv2Reg::FlagResetYLDO;
+  FlagResetWRN.initReg(m_cfg, WO, 0, 1, 5, 32, "FlagResetWRN"); m_fieldMap["FlagResetWRN"] = &AMACv2Reg::FlagResetWRN;
+  FlagResetDCDC.initReg(m_cfg, WO, 0, 1, 4, 32, "FlagResetDCDC"); m_fieldMap["FlagResetDCDC"] = &AMACv2Reg::FlagResetDCDC;
+  FlagResetHV2.initReg(m_cfg, WO, 0, 1, 3, 32, "FlagResetHV2"); m_fieldMap["FlagResetHV2"] = &AMACv2Reg::FlagResetHV2;
+  FlagResetHV0.initReg(m_cfg, WO, 0, 1, 2, 32, "FlagResetHV0"); m_fieldMap["FlagResetHV0"] = &AMACv2Reg::FlagResetHV0;
+  FlagResetXLDO.initReg(m_cfg, WO, 0, 1, 1, 32, "FlagResetXLDO"); m_fieldMap["FlagResetXLDO"] = &AMACv2Reg::FlagResetXLDO;
+  FlagResetYLDO.initReg(m_cfg, WO, 0, 1, 0, 32, "FlagResetYLDO"); m_fieldMap["FlagResetYLDO"] = &AMACv2Reg::FlagResetYLDO;
   // 33 - LogicReset
-  LogicReset.initReg(m_cfg, WO, 0, 32, 0, 33, "LogicReset"); regMap["LogicReset"] = &AMACv2Reg::LogicReset;
+  LogicReset.initReg(m_cfg, WO, 0, 32, 0, 33, "LogicReset"); m_fieldMap["LogicReset"] = &AMACv2Reg::LogicReset;
   // 34 - HardReset
-  HardReset.initReg(m_cfg, WO, 0, 32, 0, 34, "HardReset"); regMap["HardReset"] = &AMACv2Reg::HardReset;
+  HardReset.initReg(m_cfg, WO, 0, 32, 0, 34, "HardReset"); m_fieldMap["HardReset"] = &AMACv2Reg::HardReset;
   // 40 - CntSet
-  CntSetHV3frq.initReg(m_cfg, RW, 3, 2, 29, 40, "CntSetHV3frq"); regMap["CntSetHV3frq"] = &AMACv2Reg::CntSetHV3frq;
-  CntSetHV3en.initReg(m_cfg, RW, 0, 1, 28, 40, "CntSetHV3en"); regMap["CntSetHV3en"] = &AMACv2Reg::CntSetHV3en;
-  CntSetHV2frq.initReg(m_cfg, RW, 3, 2, 25, 40, "CntSetHV2frq"); regMap["CntSetHV2frq"] = &AMACv2Reg::CntSetHV2frq;
-  CntSetHV2en.initReg(m_cfg, RW, 0, 1, 24, 40, "CntSetHV2en"); regMap["CntSetHV2en"] = &AMACv2Reg::CntSetHV2en;
-  CntSetHV1frq.initReg(m_cfg, RW, 3, 2, 21, 40, "CntSetHV1frq"); regMap["CntSetHV1frq"] = &AMACv2Reg::CntSetHV1frq;
-  CntSetHV1en.initReg(m_cfg, RW, 0, 1, 20, 40, "CntSetHV1en"); regMap["CntSetHV1en"] = &AMACv2Reg::CntSetHV1en;
-  CntSetHV0frq.initReg(m_cfg, RW, 3, 2, 17, 40, "CntSetHV0frq"); regMap["CntSetHV0frq"] = &AMACv2Reg::CntSetHV0frq;
-  CntSetHV0en.initReg(m_cfg, RW, 0, 1, 16, 40, "CntSetHV0en"); regMap["CntSetHV0en"] = &AMACv2Reg::CntSetHV0en;
-  CntSetHyLDO2en.initReg(m_cfg, RW, 0, 1, 14, 40, "CntSetHyLDO2en"); regMap["CntSetHyLDO2en"] = &AMACv2Reg::CntSetHyLDO2en;
-  CntSetHyLDO1en.initReg(m_cfg, RW, 0, 1, 13, 40, "CntSetHyLDO1en"); regMap["CntSetHyLDO1en"] = &AMACv2Reg::CntSetHyLDO1en;
-  CntSetHyLDO0en.initReg(m_cfg, RW, 0, 1, 12, 40, "CntSetHyLDO0en"); regMap["CntSetHyLDO0en"] = &AMACv2Reg::CntSetHyLDO0en;
-  CntSetHxLDO2en.initReg(m_cfg, RW, 0, 1, 10, 40, "CntSetHxLDO2en"); regMap["CntSetHxLDO2en"] = &AMACv2Reg::CntSetHxLDO2en;
-  CntSetHxLDO1en.initReg(m_cfg, RW, 0, 1, 9, 40, "CntSetHxLDO1en"); regMap["CntSetHxLDO1en"] = &AMACv2Reg::CntSetHxLDO1en;
-  CntSetHxLDO0en.initReg(m_cfg, RW, 0, 1, 8, 40, "CntSetHxLDO0en"); regMap["CntSetHxLDO0en"] = &AMACv2Reg::CntSetHxLDO0en;
-  CntSetWARN.initReg(m_cfg, RW, 0, 1, 4, 40, "CntSetWARN"); regMap["CntSetWARN"] = &AMACv2Reg::CntSetWARN;
+  CntSetHV3frq.initReg(m_cfg, RW, 3, 2, 29, 40, "CntSetHV3frq"); m_fieldMap["CntSetHV3frq"] = &AMACv2Reg::CntSetHV3frq;
+  CntSetHV3en.initReg(m_cfg, RW, 0, 1, 28, 40, "CntSetHV3en"); m_fieldMap["CntSetHV3en"] = &AMACv2Reg::CntSetHV3en;
+  CntSetHV2frq.initReg(m_cfg, RW, 3, 2, 25, 40, "CntSetHV2frq"); m_fieldMap["CntSetHV2frq"] = &AMACv2Reg::CntSetHV2frq;
+  CntSetHV2en.initReg(m_cfg, RW, 0, 1, 24, 40, "CntSetHV2en"); m_fieldMap["CntSetHV2en"] = &AMACv2Reg::CntSetHV2en;
+  CntSetHV1frq.initReg(m_cfg, RW, 3, 2, 21, 40, "CntSetHV1frq"); m_fieldMap["CntSetHV1frq"] = &AMACv2Reg::CntSetHV1frq;
+  CntSetHV1en.initReg(m_cfg, RW, 0, 1, 20, 40, "CntSetHV1en"); m_fieldMap["CntSetHV1en"] = &AMACv2Reg::CntSetHV1en;
+  CntSetHV0frq.initReg(m_cfg, RW, 3, 2, 17, 40, "CntSetHV0frq"); m_fieldMap["CntSetHV0frq"] = &AMACv2Reg::CntSetHV0frq;
+  CntSetHV0en.initReg(m_cfg, RW, 0, 1, 16, 40, "CntSetHV0en"); m_fieldMap["CntSetHV0en"] = &AMACv2Reg::CntSetHV0en;
+  CntSetHyLDO2en.initReg(m_cfg, RW, 0, 1, 14, 40, "CntSetHyLDO2en"); m_fieldMap["CntSetHyLDO2en"] = &AMACv2Reg::CntSetHyLDO2en;
+  CntSetHyLDO1en.initReg(m_cfg, RW, 0, 1, 13, 40, "CntSetHyLDO1en"); m_fieldMap["CntSetHyLDO1en"] = &AMACv2Reg::CntSetHyLDO1en;
+  CntSetHyLDO0en.initReg(m_cfg, RW, 0, 1, 12, 40, "CntSetHyLDO0en"); m_fieldMap["CntSetHyLDO0en"] = &AMACv2Reg::CntSetHyLDO0en;
+  CntSetHxLDO2en.initReg(m_cfg, RW, 0, 1, 10, 40, "CntSetHxLDO2en"); m_fieldMap["CntSetHxLDO2en"] = &AMACv2Reg::CntSetHxLDO2en;
+  CntSetHxLDO1en.initReg(m_cfg, RW, 0, 1, 9, 40, "CntSetHxLDO1en"); m_fieldMap["CntSetHxLDO1en"] = &AMACv2Reg::CntSetHxLDO1en;
+  CntSetHxLDO0en.initReg(m_cfg, RW, 0, 1, 8, 40, "CntSetHxLDO0en"); m_fieldMap["CntSetHxLDO0en"] = &AMACv2Reg::CntSetHxLDO0en;
+  CntSetWARN.initReg(m_cfg, RW, 0, 1, 4, 40, "CntSetWARN"); m_fieldMap["CntSetWARN"] = &AMACv2Reg::CntSetWARN;
   // 41 - CntSetC
-  CntSetCHV3frq.initReg(m_cfg, RW, 3, 2, 29, 41, "CntSetCHV3frq"); regMap["CntSetCHV3frq"] = &AMACv2Reg::CntSetCHV3frq;
-  CntSetCHV3en.initReg(m_cfg, RW, 0, 1, 28, 41, "CntSetCHV3en"); regMap["CntSetCHV3en"] = &AMACv2Reg::CntSetCHV3en;
-  CntSetCHV2frq.initReg(m_cfg, RW, 3, 2, 25, 41, "CntSetCHV2frq"); regMap["CntSetCHV2frq"] = &AMACv2Reg::CntSetCHV2frq;
-  CntSetCHV2en.initReg(m_cfg, RW, 0, 1, 24, 41, "CntSetCHV2en"); regMap["CntSetCHV2en"] = &AMACv2Reg::CntSetCHV2en;
-  CntSetCHV1frq.initReg(m_cfg, RW, 3, 2, 21, 41, "CntSetCHV1frq"); regMap["CntSetCHV1frq"] = &AMACv2Reg::CntSetCHV1frq;
-  CntSetCHV1en.initReg(m_cfg, RW, 0, 1, 20, 41, "CntSetCHV1en"); regMap["CntSetCHV1en"] = &AMACv2Reg::CntSetCHV1en;
-  CntSetCHV0frq.initReg(m_cfg, RW, 3, 2, 17, 41, "CntSetCHV0frq"); regMap["CntSetCHV0frq"] = &AMACv2Reg::CntSetCHV0frq;
-  CntSetCHV0en.initReg(m_cfg, RW, 0, 1, 16, 41, "CntSetCHV0en"); regMap["CntSetCHV0en"] = &AMACv2Reg::CntSetCHV0en;
-  CntSetCHyLDO2en.initReg(m_cfg, RW, 0, 1, 14, 41, "CntSetCHyLDO2en"); regMap["CntSetCHyLDO2en"] = &AMACv2Reg::CntSetCHyLDO2en;
-  CntSetCHyLDO1en.initReg(m_cfg, RW, 0, 1, 13, 41, "CntSetCHyLDO1en"); regMap["CntSetCHyLDO1en"] = &AMACv2Reg::CntSetCHyLDO1en;
-  CntSetCHyLDO0en.initReg(m_cfg, RW, 0, 1, 12, 41, "CntSetCHyLDO0en"); regMap["CntSetCHyLDO0en"] = &AMACv2Reg::CntSetCHyLDO0en;
-  CntSetCHxLDO2en.initReg(m_cfg, RW, 0, 1, 10, 41, "CntSetCHxLDO2en"); regMap["CntSetCHxLDO2en"] = &AMACv2Reg::CntSetCHxLDO2en;
-  CntSetCHxLDO1en.initReg(m_cfg, RW, 0, 1, 9, 41, "CntSetCHxLDO1en"); regMap["CntSetCHxLDO1en"] = &AMACv2Reg::CntSetCHxLDO1en;
-  CntSetCHxLDO0en.initReg(m_cfg, RW, 0, 1, 8, 41, "CntSetCHxLDO0en"); regMap["CntSetCHxLDO0en"] = &AMACv2Reg::CntSetCHxLDO0en;
-  CntSetCWARN.initReg(m_cfg, RW, 0, 1, 4, 41, "CntSetCWARN"); regMap["CntSetCWARN"] = &AMACv2Reg::CntSetCWARN;
+  CntSetCHV3frq.initReg(m_cfg, RW, 3, 2, 29, 41, "CntSetCHV3frq"); m_fieldMap["CntSetCHV3frq"] = &AMACv2Reg::CntSetCHV3frq;
+  CntSetCHV3en.initReg(m_cfg, RW, 0, 1, 28, 41, "CntSetCHV3en"); m_fieldMap["CntSetCHV3en"] = &AMACv2Reg::CntSetCHV3en;
+  CntSetCHV2frq.initReg(m_cfg, RW, 3, 2, 25, 41, "CntSetCHV2frq"); m_fieldMap["CntSetCHV2frq"] = &AMACv2Reg::CntSetCHV2frq;
+  CntSetCHV2en.initReg(m_cfg, RW, 0, 1, 24, 41, "CntSetCHV2en"); m_fieldMap["CntSetCHV2en"] = &AMACv2Reg::CntSetCHV2en;
+  CntSetCHV1frq.initReg(m_cfg, RW, 3, 2, 21, 41, "CntSetCHV1frq"); m_fieldMap["CntSetCHV1frq"] = &AMACv2Reg::CntSetCHV1frq;
+  CntSetCHV1en.initReg(m_cfg, RW, 0, 1, 20, 41, "CntSetCHV1en"); m_fieldMap["CntSetCHV1en"] = &AMACv2Reg::CntSetCHV1en;
+  CntSetCHV0frq.initReg(m_cfg, RW, 3, 2, 17, 41, "CntSetCHV0frq"); m_fieldMap["CntSetCHV0frq"] = &AMACv2Reg::CntSetCHV0frq;
+  CntSetCHV0en.initReg(m_cfg, RW, 0, 1, 16, 41, "CntSetCHV0en"); m_fieldMap["CntSetCHV0en"] = &AMACv2Reg::CntSetCHV0en;
+  CntSetCHyLDO2en.initReg(m_cfg, RW, 0, 1, 14, 41, "CntSetCHyLDO2en"); m_fieldMap["CntSetCHyLDO2en"] = &AMACv2Reg::CntSetCHyLDO2en;
+  CntSetCHyLDO1en.initReg(m_cfg, RW, 0, 1, 13, 41, "CntSetCHyLDO1en"); m_fieldMap["CntSetCHyLDO1en"] = &AMACv2Reg::CntSetCHyLDO1en;
+  CntSetCHyLDO0en.initReg(m_cfg, RW, 0, 1, 12, 41, "CntSetCHyLDO0en"); m_fieldMap["CntSetCHyLDO0en"] = &AMACv2Reg::CntSetCHyLDO0en;
+  CntSetCHxLDO2en.initReg(m_cfg, RW, 0, 1, 10, 41, "CntSetCHxLDO2en"); m_fieldMap["CntSetCHxLDO2en"] = &AMACv2Reg::CntSetCHxLDO2en;
+  CntSetCHxLDO1en.initReg(m_cfg, RW, 0, 1, 9, 41, "CntSetCHxLDO1en"); m_fieldMap["CntSetCHxLDO1en"] = &AMACv2Reg::CntSetCHxLDO1en;
+  CntSetCHxLDO0en.initReg(m_cfg, RW, 0, 1, 8, 41, "CntSetCHxLDO0en"); m_fieldMap["CntSetCHxLDO0en"] = &AMACv2Reg::CntSetCHxLDO0en;
+  CntSetCWARN.initReg(m_cfg, RW, 0, 1, 4, 41, "CntSetCWARN"); m_fieldMap["CntSetCWARN"] = &AMACv2Reg::CntSetCWARN;
   // 42 - DCDCen
-  DCDCAdj.initReg(m_cfg, RW, 0, 2, 4, 42, "DCDCAdj"); regMap["DCDCAdj"] = &AMACv2Reg::DCDCAdj;
-  DCDCen.initReg(m_cfg, RW, 0, 1, 0, 42, "DCDCen"); regMap["DCDCen"] = &AMACv2Reg::DCDCen;
+  DCDCAdj.initReg(m_cfg, RW, 0, 2, 4, 42, "DCDCAdj"); m_fieldMap["DCDCAdj"] = &AMACv2Reg::DCDCAdj;
+  DCDCen.initReg(m_cfg, RW, 0, 1, 0, 42, "DCDCen"); m_fieldMap["DCDCen"] = &AMACv2Reg::DCDCen;
   // 43 - DCDCenC
-  DCDCAdjC.initReg(m_cfg, RW, 0, 2, 4, 43, "DCDCAdjC"); regMap["DCDCAdjC"] = &AMACv2Reg::DCDCAdjC;
-  DCDCenC.initReg(m_cfg, RW, 0, 1, 0, 43, "DCDCenC"); regMap["DCDCenC"] = &AMACv2Reg::DCDCenC;
+  DCDCAdjC.initReg(m_cfg, RW, 0, 2, 4, 43, "DCDCAdjC"); m_fieldMap["DCDCAdjC"] = &AMACv2Reg::DCDCAdjC;
+  DCDCenC.initReg(m_cfg, RW, 0, 1, 0, 43, "DCDCenC"); m_fieldMap["DCDCenC"] = &AMACv2Reg::DCDCenC;
   // 44 - Ilock
-  IlockWRN.initReg(m_cfg, RW, 0, 1, 5, 44, "IlockWRN"); regMap["IlockWRN"] = &AMACv2Reg::IlockWRN;
-  IlockDCDC.initReg(m_cfg, RW, 0, 1, 4, 44, "IlockDCDC"); regMap["IlockDCDC"] = &AMACv2Reg::IlockDCDC;
-  IlockHV2.initReg(m_cfg, RW, 0, 1, 3, 44, "IlockHV2"); regMap["IlockHV2"] = &AMACv2Reg::IlockHV2;
-  IlockHV2.initReg(m_cfg, RW, 0, 1, 2, 44, "IlockHV2"); regMap["IlockHV2"] = &AMACv2Reg::IlockHV2;
-  IlockHy.initReg(m_cfg, RW, 0, 1, 1, 44, "IlockHy"); regMap["IlockHy"] = &AMACv2Reg::IlockHy;
-  IlockHx.initReg(m_cfg, RW, 0, 1, 0, 44, "IlockHx"); regMap["IlockHx"] = &AMACv2Reg::IlockHx;
+  IlockWRN.initReg(m_cfg, RW, 0, 1, 5, 44, "IlockWRN"); m_fieldMap["IlockWRN"] = &AMACv2Reg::IlockWRN;
+  IlockDCDC.initReg(m_cfg, RW, 0, 1, 4, 44, "IlockDCDC"); m_fieldMap["IlockDCDC"] = &AMACv2Reg::IlockDCDC;
+  IlockHV2.initReg(m_cfg, RW, 0, 1, 3, 44, "IlockHV2"); m_fieldMap["IlockHV2"] = &AMACv2Reg::IlockHV2;
+  IlockHV2.initReg(m_cfg, RW, 0, 1, 2, 44, "IlockHV2"); m_fieldMap["IlockHV2"] = &AMACv2Reg::IlockHV2;
+  IlockHy.initReg(m_cfg, RW, 0, 1, 1, 44, "IlockHy"); m_fieldMap["IlockHy"] = &AMACv2Reg::IlockHy;
+  IlockHx.initReg(m_cfg, RW, 0, 1, 0, 44, "IlockHx"); m_fieldMap["IlockHx"] = &AMACv2Reg::IlockHx;
   // 45 - IlockC
-  IlockCWRN.initReg(m_cfg, RW, 0, 1, 5, 45, "IlockCWRN"); regMap["IlockCWRN"] = &AMACv2Reg::IlockCWRN;
-  IlockCDCDC.initReg(m_cfg, RW, 0, 1, 4, 45, "IlockCDCDC"); regMap["IlockCDCDC"] = &AMACv2Reg::IlockCDCDC;
-  IlockCHV2.initReg(m_cfg, RW, 0, 1, 3, 45, "IlockCHV2"); regMap["IlockCHV2"] = &AMACv2Reg::IlockCHV2;
-  IlockCHV2.initReg(m_cfg, RW, 0, 1, 2, 45, "IlockCHV2"); regMap["IlockCHV2"] = &AMACv2Reg::IlockCHV2;
-  IlockCHy.initReg(m_cfg, RW, 0, 1, 1, 45, "IlockCHy"); regMap["IlockCHy"] = &AMACv2Reg::IlockCHy;
-  IlockCHx.initReg(m_cfg, RW, 0, 1, 0, 45, "IlockCHx"); regMap["IlockCHx"] = &AMACv2Reg::IlockCHx;
+  IlockCWRN.initReg(m_cfg, RW, 0, 1, 5, 45, "IlockCWRN"); m_fieldMap["IlockCWRN"] = &AMACv2Reg::IlockCWRN;
+  IlockCDCDC.initReg(m_cfg, RW, 0, 1, 4, 45, "IlockCDCDC"); m_fieldMap["IlockCDCDC"] = &AMACv2Reg::IlockCDCDC;
+  IlockCHV2.initReg(m_cfg, RW, 0, 1, 3, 45, "IlockCHV2"); m_fieldMap["IlockCHV2"] = &AMACv2Reg::IlockCHV2;
+  IlockCHV2.initReg(m_cfg, RW, 0, 1, 2, 45, "IlockCHV2"); m_fieldMap["IlockCHV2"] = &AMACv2Reg::IlockCHV2;
+  IlockCHy.initReg(m_cfg, RW, 0, 1, 1, 45, "IlockCHy"); m_fieldMap["IlockCHy"] = &AMACv2Reg::IlockCHy;
+  IlockCHx.initReg(m_cfg, RW, 0, 1, 0, 45, "IlockCHx"); m_fieldMap["IlockCHx"] = &AMACv2Reg::IlockCHx;
   // 46 - RstCnt
-  RstCntHyHCCresetB.initReg(m_cfg, RW, 0, 1, 16, 46, "RstCntHyHCCresetB"); regMap["RstCntHyHCCresetB"] = &AMACv2Reg::RstCntHyHCCresetB;
-  RstCntHxHCCresetB.initReg(m_cfg, RW, 0, 1, 8, 46, "RstCntHxHCCresetB"); regMap["RstCntHxHCCresetB"] = &AMACv2Reg::RstCntHxHCCresetB;
-  RstCntOF.initReg(m_cfg, RW, 0, 1, 0, 46, "RstCntOF"); regMap["RstCntOF"] = &AMACv2Reg::RstCntOF;
+  RstCntHyHCCresetB.initReg(m_cfg, RW, 0, 1, 16, 46, "RstCntHyHCCresetB"); m_fieldMap["RstCntHyHCCresetB"] = &AMACv2Reg::RstCntHyHCCresetB;
+  RstCntHxHCCresetB.initReg(m_cfg, RW, 0, 1, 8, 46, "RstCntHxHCCresetB"); m_fieldMap["RstCntHxHCCresetB"] = &AMACv2Reg::RstCntHxHCCresetB;
+  RstCntOF.initReg(m_cfg, RW, 0, 1, 0, 46, "RstCntOF"); m_fieldMap["RstCntOF"] = &AMACv2Reg::RstCntOF;
   // 47 - RstCntC
-  RstCntCHyHCCresetB.initReg(m_cfg, RW, 0, 1, 16, 47, "RstCntCHyHCCresetB"); regMap["RstCntCHyHCCresetB"] = &AMACv2Reg::RstCntCHyHCCresetB;
-  RstCntCHxHCCresetB.initReg(m_cfg, RW, 0, 1, 8, 47, "RstCntCHxHCCresetB"); regMap["RstCntCHxHCCresetB"] = &AMACv2Reg::RstCntCHxHCCresetB;
-  RstCntCOF.initReg(m_cfg, RW, 0, 1, 0, 47, "RstCntCOF"); regMap["RstCntCOF"] = &AMACv2Reg::RstCntCOF;
+  RstCntCHyHCCresetB.initReg(m_cfg, RW, 0, 1, 16, 47, "RstCntCHyHCCresetB"); m_fieldMap["RstCntCHyHCCresetB"] = &AMACv2Reg::RstCntCHyHCCresetB;
+  RstCntCHxHCCresetB.initReg(m_cfg, RW, 0, 1, 8, 47, "RstCntCHxHCCresetB"); m_fieldMap["RstCntCHxHCCresetB"] = &AMACv2Reg::RstCntCHxHCCresetB;
+  RstCntCOF.initReg(m_cfg, RW, 0, 1, 0, 47, "RstCntCOF"); m_fieldMap["RstCntCOF"] = &AMACv2Reg::RstCntCOF;
   // 48 - AMen
-  AMzeroCalib.initReg(m_cfg, RW, 0, 1, 8, 48, "AMzeroCalib"); regMap["AMzeroCalib"] = &AMACv2Reg::AMzeroCalib;
-  AMen.initReg(m_cfg, RW, 1, 1, 0, 48, "AMen"); regMap["AMen"] = &AMACv2Reg::AMen;
+  AMzeroCalib.initReg(m_cfg, RW, 0, 1, 8, 48, "AMzeroCalib"); m_fieldMap["AMzeroCalib"] = &AMACv2Reg::AMzeroCalib;
+  AMen.initReg(m_cfg, RW, 1, 1, 0, 48, "AMen"); m_fieldMap["AMen"] = &AMACv2Reg::AMen;
   // 49 - AMenC
-  AMzeroCalibC.initReg(m_cfg, RW, 0, 1, 8, 49, "AMzeroCalibC"); regMap["AMzeroCalibC"] = &AMACv2Reg::AMzeroCalibC;
-  AMenC.initReg(m_cfg, RW, 1, 1, 0, 49, "AMenC"); regMap["AMenC"] = &AMACv2Reg::AMenC;
+  AMzeroCalibC.initReg(m_cfg, RW, 0, 1, 8, 49, "AMzeroCalibC"); m_fieldMap["AMzeroCalibC"] = &AMACv2Reg::AMzeroCalibC;
+  AMenC.initReg(m_cfg, RW, 1, 1, 0, 49, "AMenC"); m_fieldMap["AMenC"] = &AMACv2Reg::AMenC;
   // 50 - AMpwr
-  ReqDCDCPGOOD.initReg(m_cfg, RW, 1, 1, 8, 50, "ReqDCDCPGOOD"); regMap["ReqDCDCPGOOD"] = &AMACv2Reg::ReqDCDCPGOOD;
-  DCDCenToPwrAMAC.initReg(m_cfg, RW, 0, 1, 0, 50, "DCDCenToPwrAMAC"); regMap["DCDCenToPwrAMAC"] = &AMACv2Reg::DCDCenToPwrAMAC;
+  ReqDCDCPGOOD.initReg(m_cfg, RW, 1, 1, 8, 50, "ReqDCDCPGOOD"); m_fieldMap["ReqDCDCPGOOD"] = &AMACv2Reg::ReqDCDCPGOOD;
+  DCDCenToPwrAMAC.initReg(m_cfg, RW, 0, 1, 0, 50, "DCDCenToPwrAMAC"); m_fieldMap["DCDCenToPwrAMAC"] = &AMACv2Reg::DCDCenToPwrAMAC;
   // 51 - AMpwrC
-  ReqDCDCPGOODC.initReg(m_cfg, RW, 1, 1, 8, 51, "ReqDCDCPGOODC"); regMap["ReqDCDCPGOODC"] = &AMACv2Reg::ReqDCDCPGOODC;
-  DCDCenToPwrAMACC.initReg(m_cfg, RW, 0, 1, 0, 51, "DCDCenToPwrAMACC"); regMap["DCDCenToPwrAMACC"] = &AMACv2Reg::DCDCenToPwrAMACC;
+  ReqDCDCPGOODC.initReg(m_cfg, RW, 1, 1, 8, 51, "ReqDCDCPGOODC"); m_fieldMap["ReqDCDCPGOODC"] = &AMACv2Reg::ReqDCDCPGOODC;
+  DCDCenToPwrAMACC.initReg(m_cfg, RW, 0, 1, 0, 51, "DCDCenToPwrAMACC"); m_fieldMap["DCDCenToPwrAMACC"] = &AMACv2Reg::DCDCenToPwrAMACC;
   // 52 - BgCnt
-  AMbgen .initReg(m_cfg, RW, 0, 1, 15, 52, "AMbgen" ); regMap["AMbgen" ] = &AMACv2Reg::AMbgen;
-  AMbg   .initReg(m_cfg, RW, 0, 5,  8, 52, "AMbg"   ); regMap["AMbg"   ] = &AMACv2Reg::AMbg;
-  VDDbgen.initReg(m_cfg, RW, 0, 1,  7, 52, "VDDbgen"); regMap["VDDbgen"] = &AMACv2Reg::VDDbgen;
-  VDDbg  .initReg(m_cfg, RW, 0, 5,  0, 52, "VDDbg"  ); regMap["VDDbg"  ] = &AMACv2Reg::VDDbg;
+  AMbgen .initReg(m_cfg, RW, 0, 1, 15, 52, "AMbgen" ); m_fieldMap["AMbgen" ] = &AMACv2Reg::AMbgen;
+  AMbg   .initReg(m_cfg, RW, 0, 5,  8, 52, "AMbg"   ); m_fieldMap["AMbg"   ] = &AMACv2Reg::AMbg;
+  VDDbgen.initReg(m_cfg, RW, 0, 1,  7, 52, "VDDbgen"); m_fieldMap["VDDbgen"] = &AMACv2Reg::VDDbgen;
+  VDDbg  .initReg(m_cfg, RW, 0, 5,  0, 52, "VDDbg"  ); m_fieldMap["VDDbg"  ] = &AMACv2Reg::VDDbg;
   // 53 - AMcnt
-  AMintCalib.initReg(m_cfg, RW, 0, 4, 24, 53, "AMintCalib"); regMap["AMintCalib"] = &AMACv2Reg::AMintCalib;
-  Ch13Mux.initReg(m_cfg, RW, 0, 2, 20, 53, "Ch13Mux"); regMap["Ch13Mux"] = &AMACv2Reg::Ch13Mux;
-  Ch12Mux.initReg(m_cfg, RW, 0, 2, 16, 53, "Ch12Mux"); regMap["Ch12Mux"] = &AMACv2Reg::Ch12Mux;
-  Ch5Mux.initReg(m_cfg, RW, 0, 2, 13, 53, "Ch5Mux"); regMap["Ch5Mux"] = &AMACv2Reg::Ch5Mux;
-  Ch4Mux.initReg(m_cfg, RW, 0, 2, 8, 53, "Ch4Mux"); regMap["Ch4Mux"] = &AMACv2Reg::Ch4Mux;
-  Ch3Mux.initReg(m_cfg, RW, 0, 2, 4, 53, "Ch3Mux"); regMap["Ch3Mux"] = &AMACv2Reg::Ch3Mux;
+  AMintCalib.initReg(m_cfg, RW, 0, 4, 24, 53, "AMintCalib"); m_fieldMap["AMintCalib"] = &AMACv2Reg::AMintCalib;
+  Ch13Mux.initReg(m_cfg, RW, 0, 2, 20, 53, "Ch13Mux"); m_fieldMap["Ch13Mux"] = &AMACv2Reg::Ch13Mux;
+  Ch12Mux.initReg(m_cfg, RW, 0, 2, 16, 53, "Ch12Mux"); m_fieldMap["Ch12Mux"] = &AMACv2Reg::Ch12Mux;
+  Ch5Mux.initReg(m_cfg, RW, 0, 2, 13, 53, "Ch5Mux"); m_fieldMap["Ch5Mux"] = &AMACv2Reg::Ch5Mux;
+  Ch4Mux.initReg(m_cfg, RW, 0, 2, 8, 53, "Ch4Mux"); m_fieldMap["Ch4Mux"] = &AMACv2Reg::Ch4Mux;
+  Ch3Mux.initReg(m_cfg, RW, 0, 2, 4, 53, "Ch3Mux"); m_fieldMap["Ch3Mux"] = &AMACv2Reg::Ch3Mux;
   // 54 - Dacs0
-  DACShunty.initReg(m_cfg, RW, 0, 8, 24, 54, "DACShunty"); regMap["DACShunty"] = &AMACv2Reg::DACShunty;
-  DACShuntx.initReg(m_cfg, RW, 0, 8, 16, 54, "DACShuntx"); regMap["DACShuntx"] = &AMACv2Reg::DACShuntx;
-  DACCALy.initReg(m_cfg, RW, 0, 8, 8, 54, "DACCALy"); regMap["DACCALy"] = &AMACv2Reg::DACCALy;
-  DACCalx.initReg(m_cfg, RW, 0, 8, 0, 54, "DACCalx"); regMap["DACCalx"] = &AMACv2Reg::DACCalx;
+  DACShunty.initReg(m_cfg, RW, 0, 8, 24, 54, "DACShunty"); m_fieldMap["DACShunty"] = &AMACv2Reg::DACShunty;
+  DACShuntx.initReg(m_cfg, RW, 0, 8, 16, 54, "DACShuntx"); m_fieldMap["DACShuntx"] = &AMACv2Reg::DACShuntx;
+  DACCALy.initReg(m_cfg, RW, 0, 8, 8, 54, "DACCALy"); m_fieldMap["DACCALy"] = &AMACv2Reg::DACCALy;
+  DACCalx.initReg(m_cfg, RW, 0, 8, 0, 54, "DACCalx"); m_fieldMap["DACCalx"] = &AMACv2Reg::DACCalx;
   // 55 - DACbias
-  DACbias.initReg(m_cfg, RW, 0xD, 5, 0, 55, "DACbias"); regMap["DACbias"] = &AMACv2Reg::DACbias;
+  DACbias.initReg(m_cfg, RW, 0xD, 5, 0, 55, "DACbias"); m_fieldMap["DACbias"] = &AMACv2Reg::DACbias;
   // 56 - AMACcnt
-  HVcurGain .initReg(m_cfg, RW, 0, 4, 16, 56, "HVcurGain" ); regMap["HVcurGain" ] = &AMACv2Reg::HVcurGain;
-  DRcomMode .initReg(m_cfg, RW, 0, 2, 12, 56, "DRcomMode" ); regMap["DRcomMode" ] = &AMACv2Reg::DRcomMode;
-  DRcurr    .initReg(m_cfg, RW, 4, 3,  8, 56, "DRcurr"    ); regMap["DRcurr"    ] = &AMACv2Reg::DRcurr;
-  RingOscFrq.initReg(m_cfg, RW, 4, 3,  0, 56, "RingOscFrq"); regMap["RingOscFrq"] = &AMACv2Reg::RingOscFrq;
+  HVcurGain .initReg(m_cfg, RW, 0, 4, 16, 56, "HVcurGain" ); m_fieldMap["HVcurGain" ] = &AMACv2Reg::HVcurGain;
+  DRcomMode .initReg(m_cfg, RW, 0, 2, 12, 56, "DRcomMode" ); m_fieldMap["DRcomMode" ] = &AMACv2Reg::DRcomMode;
+  DRcurr    .initReg(m_cfg, RW, 4, 3,  8, 56, "DRcurr"    ); m_fieldMap["DRcurr"    ] = &AMACv2Reg::DRcurr;
+  RingOscFrq.initReg(m_cfg, RW, 4, 3,  0, 56, "RingOscFrq"); m_fieldMap["RingOscFrq"] = &AMACv2Reg::RingOscFrq;
   // 57 - NTC
-  CTAToffset     .initReg(m_cfg, RW, 0, 4, 20, 57, "CTAToffset"     ); regMap["CTAToffset"     ] = &AMACv2Reg::CTAToffset;
-  NTCpbCal       .initReg(m_cfg, RW, 1, 1, 19, 57, "NTCpbCal"       ); regMap["NTCpbCal"       ] = &AMACv2Reg::NTCpbCal;
-  NTCpbSenseRange.initReg(m_cfg, RW, 4, 3, 16, 57, "NTCpbSenseRange"); regMap["NTCpbSenseRange"] = &AMACv2Reg::NTCpbSenseRange;
-  NTCy0Cal       .initReg(m_cfg, RW, 1, 1, 11, 57, "NTCy0Cal"       ); regMap["NTCy0Cal"       ] = &AMACv2Reg::NTCy0Cal;
-  NTCy0SenseRange.initReg(m_cfg, RW, 4, 3,  8, 57, "NTCy0SenseRange"); regMap["NTCy0SenseRange"] = &AMACv2Reg::NTCy0SenseRange;
-  NTCx0Cal       .initReg(m_cfg, RW, 1, 1,  3, 57, "NTCx0Cal"       ); regMap["NTCx0Cal"       ] = &AMACv2Reg::NTCx0Cal;
-  NTCx0SenseRange.initReg(m_cfg, RW, 4, 3,  0, 57, "NTCx0SenseRange"); regMap["NTCx0SenseRange"] = &AMACv2Reg::NTCx0SenseRange;
+  CTAToffset     .initReg(m_cfg, RW, 0, 4, 20, 57, "CTAToffset"     ); m_fieldMap["CTAToffset"     ] = &AMACv2Reg::CTAToffset;
+  NTCpbCal       .initReg(m_cfg, RW, 1, 1, 19, 57, "NTCpbCal"       ); m_fieldMap["NTCpbCal"       ] = &AMACv2Reg::NTCpbCal;
+  NTCpbSenseRange.initReg(m_cfg, RW, 4, 3, 16, 57, "NTCpbSenseRange"); m_fieldMap["NTCpbSenseRange"] = &AMACv2Reg::NTCpbSenseRange;
+  NTCy0Cal       .initReg(m_cfg, RW, 1, 1, 11, 57, "NTCy0Cal"       ); m_fieldMap["NTCy0Cal"       ] = &AMACv2Reg::NTCy0Cal;
+  NTCy0SenseRange.initReg(m_cfg, RW, 4, 3,  8, 57, "NTCy0SenseRange"); m_fieldMap["NTCy0SenseRange"] = &AMACv2Reg::NTCy0SenseRange;
+  NTCx0Cal       .initReg(m_cfg, RW, 1, 1,  3, 57, "NTCx0Cal"       ); m_fieldMap["NTCx0Cal"       ] = &AMACv2Reg::NTCx0Cal;
+  NTCx0SenseRange.initReg(m_cfg, RW, 4, 3,  0, 57, "NTCx0SenseRange"); m_fieldMap["NTCx0SenseRange"] = &AMACv2Reg::NTCx0SenseRange;
   // 58 - LvCurCal
-  DCDCoOffset     .initReg(m_cfg, RW, 4, 4, 20, 58, "DCDCoOffset"     ); regMap["DCDCoOffset"     ] = &AMACv2Reg::DCDCoOffset;
-  DCDCoZeroReading.initReg(m_cfg, RW, 0, 1, 19, 58, "DCDCoZeroReading"); regMap["DCDCoZeroReading"] = &AMACv2Reg::DCDCoZeroReading;
-  DCDCoN          .initReg(m_cfg, RW, 0, 1, 17, 58, "DCDCoN"          ); regMap["DCDCoN"          ] = &AMACv2Reg::DCDCoN;
-  DCDCoP          .initReg(m_cfg, RW, 0, 1, 16, 58, "DCDCoP"          ); regMap["DCDCoP"          ] = &AMACv2Reg::DCDCoP;
-  DCDCiZeroReading.initReg(m_cfg, RW, 0, 1, 15, 58, "DCDCiZeroReading"); regMap["DCDCiZeroReading"] = &AMACv2Reg::DCDCiZeroReading;
-  DCDCiRangeSW    .initReg(m_cfg, RW, 1, 1, 12, 58, "DCDCiRangeSW"    ); regMap["DCDCiRangeSW"    ] = &AMACv2Reg::DCDCiRangeSW;
-  DCDCiOffset     .initReg(m_cfg, RW, 8, 4,  8, 58, "DCDCiOffset"     ); regMap["DCDCiOffset"     ] = &AMACv2Reg::DCDCiOffset;
-  DCDCiP          .initReg(m_cfg, RW, 0, 3,  4, 58, "DCDCiP"          ); regMap["DCDCiP"          ] = &AMACv2Reg::DCDCiP;
-  DCDCiN          .initReg(m_cfg, RW, 0, 3,  0, 58, "DCDCiN"          ); regMap["DCDCiN"          ] = &AMACv2Reg::DCDCiN;
+  DCDCoOffset     .initReg(m_cfg, RW, 4, 4, 20, 58, "DCDCoOffset"     ); m_fieldMap["DCDCoOffset"     ] = &AMACv2Reg::DCDCoOffset;
+  DCDCoZeroReading.initReg(m_cfg, RW, 0, 1, 19, 58, "DCDCoZeroReading"); m_fieldMap["DCDCoZeroReading"] = &AMACv2Reg::DCDCoZeroReading;
+  DCDCoN          .initReg(m_cfg, RW, 0, 1, 17, 58, "DCDCoN"          ); m_fieldMap["DCDCoN"          ] = &AMACv2Reg::DCDCoN;
+  DCDCoP          .initReg(m_cfg, RW, 0, 1, 16, 58, "DCDCoP"          ); m_fieldMap["DCDCoP"          ] = &AMACv2Reg::DCDCoP;
+  DCDCiZeroReading.initReg(m_cfg, RW, 0, 1, 15, 58, "DCDCiZeroReading"); m_fieldMap["DCDCiZeroReading"] = &AMACv2Reg::DCDCiZeroReading;
+  DCDCiRangeSW    .initReg(m_cfg, RW, 1, 1, 12, 58, "DCDCiRangeSW"    ); m_fieldMap["DCDCiRangeSW"    ] = &AMACv2Reg::DCDCiRangeSW;
+  DCDCiOffset     .initReg(m_cfg, RW, 8, 4,  8, 58, "DCDCiOffset"     ); m_fieldMap["DCDCiOffset"     ] = &AMACv2Reg::DCDCiOffset;
+  DCDCiP          .initReg(m_cfg, RW, 0, 3,  4, 58, "DCDCiP"          ); m_fieldMap["DCDCiP"          ] = &AMACv2Reg::DCDCiP;
+  DCDCiN          .initReg(m_cfg, RW, 0, 3,  0, 58, "DCDCiN"          ); m_fieldMap["DCDCiN"          ] = &AMACv2Reg::DCDCiN;
   // 60 - HxICm_cfg
-  HxLAM.initReg(m_cfg, RW, 0, 1, 16, 60, "HxLAM"); regMap["HxLAM"] = &AMACv2Reg::HxLAM;
-  HxFlagsLatch.initReg(m_cfg, RW, 1, 1, 12, 60, "HxFlagsLatch"); regMap["HxFlagsLatch"] = &AMACv2Reg::HxFlagsLatch;
-  HxFlagsLogic.initReg(m_cfg, RW, 0, 1, 8, 60, "HxFlagsLogic"); regMap["HxFlagsLogic"] = &AMACv2Reg::HxFlagsLogic;
-  HxFlagValid.initReg(m_cfg, RW, 0, 1, 4, 60, "HxFlagValid"); regMap["HxFlagValid"] = &AMACv2Reg::HxFlagsLogic;
-  HxFlagsValidConf.initReg(m_cfg, RW, 0, 2, 0, 60, "HxFlagValid"); regMap["HxFlagValid"] = &AMACv2Reg::HxFlagsLogic;
+  HxLAM.initReg(m_cfg, RW, 0, 1, 16, 60, "HxLAM"); m_fieldMap["HxLAM"] = &AMACv2Reg::HxLAM;
+  HxFlagsLatch.initReg(m_cfg, RW, 1, 1, 12, 60, "HxFlagsLatch"); m_fieldMap["HxFlagsLatch"] = &AMACv2Reg::HxFlagsLatch;
+  HxFlagsLogic.initReg(m_cfg, RW, 0, 1, 8, 60, "HxFlagsLogic"); m_fieldMap["HxFlagsLogic"] = &AMACv2Reg::HxFlagsLogic;
+  HxFlagValid.initReg(m_cfg, RW, 0, 1, 4, 60, "HxFlagValid"); m_fieldMap["HxFlagValid"] = &AMACv2Reg::HxFlagsLogic;
+  HxFlagsValidConf.initReg(m_cfg, RW, 0, 2, 0, 60, "HxFlagValid"); m_fieldMap["HxFlagValid"] = &AMACv2Reg::HxFlagsLogic;
   // 61 - HyICm_cfg
-  HyLAM.initReg(m_cfg, RW, 0, 1, 16, 61, "HyLAM"); regMap["HyLAM"] = &AMACv2Reg::HyLAM;
-  HyFlagsLatch.initReg(m_cfg, RW, 1, 1, 12, 61, "HyFlagsLatch"); regMap["HyFlagsLatch"] = &AMACv2Reg::HyFlagsLatch;
-  HyFlagsLogic.initReg(m_cfg, RW, 0, 1, 8, 61, "HyFlagsLogic"); regMap["HyFlagsLogic"] = &AMACv2Reg::HyFlagsLogic;
-  HyFlagValid.initReg(m_cfg, RW, 0, 1, 4, 61, "HyFlagValid"); regMap["HyFlagValid"] = &AMACv2Reg::HyFlagsLogic;
-  HyFlagsValidConf.initReg(m_cfg, RW, 0, 2, 0, 61, "HyFlagValid"); regMap["HyFlagValid"] = &AMACv2Reg::HyFlagsLogic;
+  HyLAM.initReg(m_cfg, RW, 0, 1, 16, 61, "HyLAM"); m_fieldMap["HyLAM"] = &AMACv2Reg::HyLAM;
+  HyFlagsLatch.initReg(m_cfg, RW, 1, 1, 12, 61, "HyFlagsLatch"); m_fieldMap["HyFlagsLatch"] = &AMACv2Reg::HyFlagsLatch;
+  HyFlagsLogic.initReg(m_cfg, RW, 0, 1, 8, 61, "HyFlagsLogic"); m_fieldMap["HyFlagsLogic"] = &AMACv2Reg::HyFlagsLogic;
+  HyFlagValid.initReg(m_cfg, RW, 0, 1, 4, 61, "HyFlagValid"); m_fieldMap["HyFlagValid"] = &AMACv2Reg::HyFlagsLogic;
+  HyFlagsValidConf.initReg(m_cfg, RW, 0, 2, 0, 61, "HyFlagValid"); m_fieldMap["HyFlagValid"] = &AMACv2Reg::HyFlagsLogic;
   // 62 - HV0ICm_cfg
-  HV0LAM.initReg(m_cfg, RW, 0, 1, 16, 62, "HV0LAM"); regMap["HV0LAM"] = &AMACv2Reg::HV0LAM;
-  HV0FlagsLatch.initReg(m_cfg, RW, 1, 1, 12, 62, "HV0FlagsLatch"); regMap["HV0FlagsLatch"] = &AMACv2Reg::HV0FlagsLatch;
-  HV0FlagsLogic.initReg(m_cfg, RW, 0, 1, 8, 62, "HV0FlagsLogic"); regMap["HV0FlagsLogic"] = &AMACv2Reg::HV0FlagsLogic;
-  HV0FlagValid.initReg(m_cfg, RW, 0, 1, 4, 62, "HV0FlagValid"); regMap["HV0FlagValid"] = &AMACv2Reg::HV0FlagsLogic;
-  HV0FlagsValidConf.initReg(m_cfg, RW, 0, 2, 0, 62, "HV0FlagValid"); regMap["HV0FlagValid"] = &AMACv2Reg::HV0FlagsLogic;
+  HV0LAM.initReg(m_cfg, RW, 0, 1, 16, 62, "HV0LAM"); m_fieldMap["HV0LAM"] = &AMACv2Reg::HV0LAM;
+  HV0FlagsLatch.initReg(m_cfg, RW, 1, 1, 12, 62, "HV0FlagsLatch"); m_fieldMap["HV0FlagsLatch"] = &AMACv2Reg::HV0FlagsLatch;
+  HV0FlagsLogic.initReg(m_cfg, RW, 0, 1, 8, 62, "HV0FlagsLogic"); m_fieldMap["HV0FlagsLogic"] = &AMACv2Reg::HV0FlagsLogic;
+  HV0FlagValid.initReg(m_cfg, RW, 0, 1, 4, 62, "HV0FlagValid"); m_fieldMap["HV0FlagValid"] = &AMACv2Reg::HV0FlagsLogic;
+  HV0FlagsValidConf.initReg(m_cfg, RW, 0, 2, 0, 62, "HV0FlagValid"); m_fieldMap["HV0FlagValid"] = &AMACv2Reg::HV0FlagsLogic;
   // 63 - HV2ICm_cfg
-  HV2LAM.initReg(m_cfg, RW, 0, 1, 16, 63, "HV2LAM"); regMap["HV2LAM"] = &AMACv2Reg::HV2LAM;
-  HV2FlagsLatch.initReg(m_cfg, RW, 1, 1, 12, 63, "HV2FlagsLatch"); regMap["HV2FlagsLatch"] = &AMACv2Reg::HV2FlagsLatch;
-  HV2FlagsLogic.initReg(m_cfg, RW, 0, 1, 8, 63, "HV2FlagsLogic"); regMap["HV2FlagsLogic"] = &AMACv2Reg::HV2FlagsLogic;
-  HV2FlagValid.initReg(m_cfg, RW, 0, 1, 4, 63, "HV2FlagValid"); regMap["HV2FlagValid"] = &AMACv2Reg::HV2FlagsLogic;
-  HV2FlagsValidConf.initReg(m_cfg, RW, 0, 2, 0, 63, "HV2FlagValid"); regMap["HV2FlagValid"] = &AMACv2Reg::HV2FlagsLogic;
+  HV2LAM.initReg(m_cfg, RW, 0, 1, 16, 63, "HV2LAM"); m_fieldMap["HV2LAM"] = &AMACv2Reg::HV2LAM;
+  HV2FlagsLatch.initReg(m_cfg, RW, 1, 1, 12, 63, "HV2FlagsLatch"); m_fieldMap["HV2FlagsLatch"] = &AMACv2Reg::HV2FlagsLatch;
+  HV2FlagsLogic.initReg(m_cfg, RW, 0, 1, 8, 63, "HV2FlagsLogic"); m_fieldMap["HV2FlagsLogic"] = &AMACv2Reg::HV2FlagsLogic;
+  HV2FlagValid.initReg(m_cfg, RW, 0, 1, 4, 63, "HV2FlagValid"); m_fieldMap["HV2FlagValid"] = &AMACv2Reg::HV2FlagsLogic;
+  HV2FlagsValidConf.initReg(m_cfg, RW, 0, 2, 0, 63, "HV2FlagValid"); m_fieldMap["HV2FlagValid"] = &AMACv2Reg::HV2FlagsLogic;
   // 64 - DCDCICm_cfg
-  DCDCLAM.initReg(m_cfg, RW, 0, 1, 16, 64, "DCDCLAM"); regMap["DCDCLAM"] = &AMACv2Reg::DCDCLAM;
-  DCDCFlagsLatch.initReg(m_cfg, RW, 1, 1, 12, 64, "DCDCFlagsLatch"); regMap["DCDCFlagsLatch"] = &AMACv2Reg::DCDCFlagsLatch;
-  DCDCFlagsLogic.initReg(m_cfg, RW, 0, 1, 8, 64, "DCDCFlagsLogic"); regMap["DCDCFlagsLogic"] = &AMACv2Reg::DCDCFlagsLogic;
-  DCDCFlagValid.initReg(m_cfg, RW, 0, 1, 4, 64, "DCDCFlagValid"); regMap["DCDCFlagValid"] = &AMACv2Reg::DCDCFlagsLogic;
-  DCDCFlagsValidConf.initReg(m_cfg, RW, 0, 2, 0, 64, "DCDCFlagValid"); regMap["DCDCFlagValid"] = &AMACv2Reg::DCDCFlagsLogic;
+  DCDCLAM.initReg(m_cfg, RW, 0, 1, 16, 64, "DCDCLAM"); m_fieldMap["DCDCLAM"] = &AMACv2Reg::DCDCLAM;
+  DCDCFlagsLatch.initReg(m_cfg, RW, 1, 1, 12, 64, "DCDCFlagsLatch"); m_fieldMap["DCDCFlagsLatch"] = &AMACv2Reg::DCDCFlagsLatch;
+  DCDCFlagsLogic.initReg(m_cfg, RW, 0, 1, 8, 64, "DCDCFlagsLogic"); m_fieldMap["DCDCFlagsLogic"] = &AMACv2Reg::DCDCFlagsLogic;
+  DCDCFlagValid.initReg(m_cfg, RW, 0, 1, 4, 64, "DCDCFlagValid"); m_fieldMap["DCDCFlagValid"] = &AMACv2Reg::DCDCFlagsLogic;
+  DCDCFlagsValidConf.initReg(m_cfg, RW, 0, 2, 0, 64, "DCDCFlagValid"); m_fieldMap["DCDCFlagValid"] = &AMACv2Reg::DCDCFlagsLogic;
   // 65 - WRNICm_cfg
-  WRNLAM.initReg(m_cfg, RW, 0, 1, 16, 65, "WRNLAM"); regMap["WRNLAM"] = &AMACv2Reg::WRNLAM;
-  WRNFlagsLatch.initReg(m_cfg, RW, 1, 1, 12, 65, "WRNFlagsLatch"); regMap["WRNFlagsLatch"] = &AMACv2Reg::WRNFlagsLatch;
-  WRNFlagsLogic.initReg(m_cfg, RW, 0, 1, 8, 65, "WRNFlagsLogic"); regMap["WRNFlagsLogic"] = &AMACv2Reg::WRNFlagsLogic;
-  WRNFlagValid.initReg(m_cfg, RW, 0, 1, 4, 65, "WRNFlagValid"); regMap["WRNFlagValid"] = &AMACv2Reg::WRNFlagsLogic;
-  WRNFlagsValidConf.initReg(m_cfg, RW, 0, 2, 0, 65, "WRNFlagValid"); regMap["WRNFlagValid"] = &AMACv2Reg::WRNFlagsLogic;
+  WRNLAM.initReg(m_cfg, RW, 0, 1, 16, 65, "WRNLAM"); m_fieldMap["WRNLAM"] = &AMACv2Reg::WRNLAM;
+  WRNFlagsLatch.initReg(m_cfg, RW, 1, 1, 12, 65, "WRNFlagsLatch"); m_fieldMap["WRNFlagsLatch"] = &AMACv2Reg::WRNFlagsLatch;
+  WRNFlagsLogic.initReg(m_cfg, RW, 0, 1, 8, 65, "WRNFlagsLogic"); m_fieldMap["WRNFlagsLogic"] = &AMACv2Reg::WRNFlagsLogic;
+  WRNFlagValid.initReg(m_cfg, RW, 0, 1, 4, 65, "WRNFlagValid"); m_fieldMap["WRNFlagValid"] = &AMACv2Reg::WRNFlagsLogic;
+  WRNFlagsValidConf.initReg(m_cfg, RW, 0, 2, 0, 65, "WRNFlagValid"); m_fieldMap["WRNFlagValid"] = &AMACv2Reg::WRNFlagsLogic;
   // 70 - HxTlut
-  HxTlut.initReg(m_cfg, RW, 0, 8, 0, 70, "HxTlut"); regMap["HxTlut"] = &AMACv2Reg::HxTlut;
+  HxTlut.initReg(m_cfg, RW, 0, 8, 0, 70, "HxTlut"); m_fieldMap["HxTlut"] = &AMACv2Reg::HxTlut;
   // 71 - HxModlut1
-  HxModlut1.initReg(m_cfg, RW, 0, 32, 0, 71, "HxModlut1"); regMap["HxModlut1"] = &AMACv2Reg::HxModlut1;
+  HxModlut1.initReg(m_cfg, RW, 0, 32, 0, 71, "HxModlut1"); m_fieldMap["HxModlut1"] = &AMACv2Reg::HxModlut1;
   // 72 - HxModlut2
-  HxModlut2.initReg(m_cfg, RW, 0, 32, 0, 72, "HxModlut2"); regMap["HxModlut2"] = &AMACv2Reg::HxModlut2;
+  HxModlut2.initReg(m_cfg, RW, 0, 32, 0, 72, "HxModlut2"); m_fieldMap["HxModlut2"] = &AMACv2Reg::HxModlut2;
   // 73 - HyTlut
-  HyTlut.initReg(m_cfg, RW, 0, 8, 0, 73, "HyTlut"); regMap["HyTlut"] = &AMACv2Reg::HyTlut;
+  HyTlut.initReg(m_cfg, RW, 0, 8, 0, 73, "HyTlut"); m_fieldMap["HyTlut"] = &AMACv2Reg::HyTlut;
   // 74 - HyModlut1
-  HyModlut1.initReg(m_cfg, RW, 0, 32, 0, 74, "HyModlut1"); regMap["HyModlut1"] = &AMACv2Reg::HyModlut1;
+  HyModlut1.initReg(m_cfg, RW, 0, 32, 0, 74, "HyModlut1"); m_fieldMap["HyModlut1"] = &AMACv2Reg::HyModlut1;
   // 75 - HyModlut2
-  HyModlut2.initReg(m_cfg, RW, 0, 32, 0, 75, "HyModlut2"); regMap["HyModlut2"] = &AMACv2Reg::HyModlut2;
+  HyModlut2.initReg(m_cfg, RW, 0, 32, 0, 75, "HyModlut2"); m_fieldMap["HyModlut2"] = &AMACv2Reg::HyModlut2;
   // 76 - HV0Tlut;
-  HV0Tlut.initReg(m_cfg, RW, 0, 8, 0, 76, "HV0Tlut"); regMap["HV0Tlut"] = &AMACv2Reg::HV0Tlut;
+  HV0Tlut.initReg(m_cfg, RW, 0, 8, 0, 76, "HV0Tlut"); m_fieldMap["HV0Tlut"] = &AMACv2Reg::HV0Tlut;
   // 77 - HV0Modlut1
-  HV0Modlut1.initReg(m_cfg, RW, 0, 32, 0, 77, "HV0Modlut1"); regMap["HV0Modlut1"] = &AMACv2Reg::HV0Modlut1;
+  HV0Modlut1.initReg(m_cfg, RW, 0, 32, 0, 77, "HV0Modlut1"); m_fieldMap["HV0Modlut1"] = &AMACv2Reg::HV0Modlut1;
   // 78 - HV0Modlut2
-  HV0Modlut2.initReg(m_cfg, RW, 0, 32, 0, 78, "HV0Modlut2"); regMap["HV0Modlut2"] = &AMACv2Reg::HV0Modlut2;
+  HV0Modlut2.initReg(m_cfg, RW, 0, 32, 0, 78, "HV0Modlut2"); m_fieldMap["HV0Modlut2"] = &AMACv2Reg::HV0Modlut2;
   // 79 - HV2Tlut
-  HV2Tlut.initReg(m_cfg, RW, 0, 8, 0, 79, "HV2Tlut"); regMap["HV2Tlut"] = &AMACv2Reg::HV2Tlut;
+  HV2Tlut.initReg(m_cfg, RW, 0, 8, 0, 79, "HV2Tlut"); m_fieldMap["HV2Tlut"] = &AMACv2Reg::HV2Tlut;
   // 80 - HV2Modlut1
-  HV2Modlut1.initReg(m_cfg, RW, 0, 32, 0, 80, "HV2Modlut1"); regMap["HV2Modlut1"] = &AMACv2Reg::HV2Modlut1;
+  HV2Modlut1.initReg(m_cfg, RW, 0, 32, 0, 80, "HV2Modlut1"); m_fieldMap["HV2Modlut1"] = &AMACv2Reg::HV2Modlut1;
   // 81 - HV2Modlut2
-  HV2Modlut2.initReg(m_cfg, RW, 0, 32, 0, 81, "HV2Modlut2"); regMap["HV2Modlut2"] = &AMACv2Reg::HV2Modlut2;
+  HV2Modlut2.initReg(m_cfg, RW, 0, 32, 0, 81, "HV2Modlut2"); m_fieldMap["HV2Modlut2"] = &AMACv2Reg::HV2Modlut2;
   // 82 - DCDCTlut
-  DCDCTlut.initReg(m_cfg, RW, 0, 8, 0, 82, "DCDCTlut"); regMap["DCDCTlut"] = &AMACv2Reg::DCDCTlut;
+  DCDCTlut.initReg(m_cfg, RW, 0, 8, 0, 82, "DCDCTlut"); m_fieldMap["DCDCTlut"] = &AMACv2Reg::DCDCTlut;
   // 83 - DCDCModlut1
-  DCDCModlut1.initReg(m_cfg, RW, 0, 32, 0, 83, "DCDCModlut1"); regMap["DCDCModlut1"] = &AMACv2Reg::DCDCModlut1;
+  DCDCModlut1.initReg(m_cfg, RW, 0, 32, 0, 83, "DCDCModlut1"); m_fieldMap["DCDCModlut1"] = &AMACv2Reg::DCDCModlut1;
   // 84 - DCDCModlut2
-  DCDCModlut2.initReg(m_cfg, RW, 0, 32, 0, 84, "DCDCModlut2"); regMap["DCDCModlut2"] = &AMACv2Reg::DCDCModlut2;
+  DCDCModlut2.initReg(m_cfg, RW, 0, 32, 0, 84, "DCDCModlut2"); m_fieldMap["DCDCModlut2"] = &AMACv2Reg::DCDCModlut2;
   // 85 - WRNTlut
-  WRNTlut.initReg(m_cfg, RW, 0, 8, 0, 85, "WRNTlut"); regMap["WRNTlut"] = &AMACv2Reg::WRNTlut;
+  WRNTlut.initReg(m_cfg, RW, 0, 8, 0, 85, "WRNTlut"); m_fieldMap["WRNTlut"] = &AMACv2Reg::WRNTlut;
   // 86 - WRNModlut1
-  WRNModlut1.initReg(m_cfg, RW, 0, 32, 0, 86, "WRNModlut1"); regMap["WRNModlut1"] = &AMACv2Reg::WRNModlut1;
+  WRNModlut1.initReg(m_cfg, RW, 0, 32, 0, 86, "WRNModlut1"); m_fieldMap["WRNModlut1"] = &AMACv2Reg::WRNModlut1;
   // 87 - WRNModlut2
-  WRNModlut2.initReg(m_cfg, RW, 0, 32, 0, 87, "WRNModlut2"); regMap["WRNModlut2"] = &AMACv2Reg::WRNModlut2;
+  WRNModlut2.initReg(m_cfg, RW, 0, 32, 0, 87, "WRNModlut2"); m_fieldMap["WRNModlut2"] = &AMACv2Reg::WRNModlut2;
   // 90 - HxFlagEn
-  HxFlagsEnHi.initReg(m_cfg, RW, 0, 16, 16, 90, "HxFlagsEnHi"); regMap["HxFlagsEnHi"] = &AMACv2Reg::HxFlagsEnHi;
-  HxFlagsEnLo.initReg(m_cfg, RW, 0, 16, 16, 90, "HxFlagsEnLo"); regMap["HxFlagsEnLo"] = &AMACv2Reg::HxFlagsEnLo;
+  HxFlagsEnHi.initReg(m_cfg, RW, 0, 16, 16, 90, "HxFlagsEnHi"); m_fieldMap["HxFlagsEnHi"] = &AMACv2Reg::HxFlagsEnHi;
+  HxFlagsEnLo.initReg(m_cfg, RW, 0, 16, 16, 90, "HxFlagsEnLo"); m_fieldMap["HxFlagsEnLo"] = &AMACv2Reg::HxFlagsEnLo;
   // 91 - HyFlagEn
-  HyFlagsEnHi.initReg(m_cfg, RW, 0, 16, 16, 91, "HyFlagsEnHi"); regMap["HyFlagsEnHi"] = &AMACv2Reg::HyFlagsEnHi;
-  HyFlagsEnLo.initReg(m_cfg, RW, 0, 16, 16, 91, "HyFlagsEnLo"); regMap["HyFlagsEnLo"] = &AMACv2Reg::HyFlagsEnLo;
+  HyFlagsEnHi.initReg(m_cfg, RW, 0, 16, 16, 91, "HyFlagsEnHi"); m_fieldMap["HyFlagsEnHi"] = &AMACv2Reg::HyFlagsEnHi;
+  HyFlagsEnLo.initReg(m_cfg, RW, 0, 16, 16, 91, "HyFlagsEnLo"); m_fieldMap["HyFlagsEnLo"] = &AMACv2Reg::HyFlagsEnLo;
   // 92 - HV0FlagEn
-  HV0FlagsEnHi.initReg(m_cfg, RW, 0, 16, 16, 92, "HV0FlagsEnHi"); regMap["HV0FlagsEnHi"] = &AMACv2Reg::HV0FlagsEnHi;
-  HV0FlagsEnLo.initReg(m_cfg, RW, 0, 16, 16, 92, "HV0FlagsEnLo"); regMap["HV0FlagsEnLo"] = &AMACv2Reg::HV0FlagsEnLo;
+  HV0FlagsEnHi.initReg(m_cfg, RW, 0, 16, 16, 92, "HV0FlagsEnHi"); m_fieldMap["HV0FlagsEnHi"] = &AMACv2Reg::HV0FlagsEnHi;
+  HV0FlagsEnLo.initReg(m_cfg, RW, 0, 16, 16, 92, "HV0FlagsEnLo"); m_fieldMap["HV0FlagsEnLo"] = &AMACv2Reg::HV0FlagsEnLo;
   // 93 - HV2FlagEn
-  HV2FlagsEnHi.initReg(m_cfg, RW, 0, 16, 16, 93, "HxFlagsEnHi"); regMap["HxFlagsEnHi"] = &AMACv2Reg::HxFlagsEnHi;
-  HV2FlagsEnLo.initReg(m_cfg, RW, 0, 16, 16, 93, "HxFlagsEnLo"); regMap["HxFlagsEnLo"] = &AMACv2Reg::HxFlagsEnLo;
+  HV2FlagsEnHi.initReg(m_cfg, RW, 0, 16, 16, 93, "HxFlagsEnHi"); m_fieldMap["HxFlagsEnHi"] = &AMACv2Reg::HxFlagsEnHi;
+  HV2FlagsEnLo.initReg(m_cfg, RW, 0, 16, 16, 93, "HxFlagsEnLo"); m_fieldMap["HxFlagsEnLo"] = &AMACv2Reg::HxFlagsEnLo;
   // 94 - DCDCFlagEn
-  DCDCFlagsEnHi.initReg(m_cfg, RW, 0, 16, 16, 94, "DCDCFlagsEnHi"); regMap["DCDCFlagsEnHi"] = &AMACv2Reg::DCDCFlagsEnHi;
-  DCDCFlagsEnLo.initReg(m_cfg, RW, 0, 16, 16, 94, "DCDCFlagsEnLo"); regMap["DCDCFlagsEnLo"] = &AMACv2Reg::DCDCFlagsEnLo;
+  DCDCFlagsEnHi.initReg(m_cfg, RW, 0, 16, 16, 94, "DCDCFlagsEnHi"); m_fieldMap["DCDCFlagsEnHi"] = &AMACv2Reg::DCDCFlagsEnHi;
+  DCDCFlagsEnLo.initReg(m_cfg, RW, 0, 16, 16, 94, "DCDCFlagsEnLo"); m_fieldMap["DCDCFlagsEnLo"] = &AMACv2Reg::DCDCFlagsEnLo;
   // 94 - WRNFlagEn
-  WRNFlagsEnHi.initReg(m_cfg, RW, 0, 16, 16, 95, "WRNFlagsEnHi"); regMap["WRNFlagsEnHi"] = &AMACv2Reg::WRNFlagsEnHi;
-  WRNFlagsEnLo.initReg(m_cfg, RW, 0, 16, 16, 95, "WRNFlagsEnLo"); regMap["WRNFlagsEnLo"] = &AMACv2Reg::WRNFlagsEnLo;
+  WRNFlagsEnHi.initReg(m_cfg, RW, 0, 16, 16, 95, "WRNFlagsEnHi"); m_fieldMap["WRNFlagsEnHi"] = &AMACv2Reg::WRNFlagsEnHi;
+  WRNFlagsEnLo.initReg(m_cfg, RW, 0, 16, 16, 95, "WRNFlagsEnLo"); m_fieldMap["WRNFlagsEnLo"] = &AMACv2Reg::WRNFlagsEnLo;
   // 95 - SynFlagEn
-  WRNsynFlagEnHi.initReg(m_cfg, RW, 0, 1, 21, 95, "WRNsynFlagEnHi"); regMap["WRNsynFlagEnHi"] = &AMACv2Reg::WRNsynFlagEnHi;
-  WRNsynFlagEnLo.initReg(m_cfg, RW, 0, 1, 20, 95, "WRNsynFlagEnLo"); regMap["WRNsynFlagEnLo"] = &AMACv2Reg::WRNsynFlagEnLo;
-  DCDCsynFlagEnHi.initReg(m_cfg, RW, 0, 1, 17, 95, "DCDCsynFlagEnHi"); regMap["DCDCsynFlagEnHi"] = &AMACv2Reg::DCDCsynFlagEnHi;
-  DCDCsynFlagEnLo.initReg(m_cfg, RW, 0, 1, 16, 95, "DCDCsynFlagEnLo"); regMap["DCDCsynFlagEnLo"] = &AMACv2Reg::DCDCsynFlagEnLo;
-  HV2synFlagEnHi.initReg(m_cfg, RW, 0, 1, 13, 95, "HV2synFlagEnHi"); regMap["HV2synFlagEnHi"] = &AMACv2Reg::HV2synFlagEnHi;
-  HV2synFlagEnLo.initReg(m_cfg, RW, 0, 1, 12, 95, "HV2synFlagEnLo"); regMap["HV2synFlagEnLo"] = &AMACv2Reg::HV2synFlagEnLo;
-  HV0synFlagEnHi.initReg(m_cfg, RW, 0, 1, 9, 95, "HV0synFlagEnHi"); regMap["HV0synFlagEnHi"] = &AMACv2Reg::HV0synFlagEnHi;
-  HV0synFlagEnLo.initReg(m_cfg, RW, 0, 1, 8, 95, "HV0synFlagEnLo"); regMap["HV0synFlagEnLo"] = &AMACv2Reg::HV0synFlagEnLo;
-  HysynFlagEnHi.initReg(m_cfg, RW, 0, 1, 5, 95, "HysynFlagEnHi"); regMap["HysynFlagEnHi"] = &AMACv2Reg::HysynFlagEnHi;
-  HysynFlagEnLo.initReg(m_cfg, RW, 0, 1, 4, 95, "HysynFlagEnLo"); regMap["HysynFlagEnLo"] = &AMACv2Reg::HysynFlagEnLo;
-  HxsynFlagEnHi.initReg(m_cfg, RW, 0, 1, 1, 95, "HxsynFlagEnHi"); regMap["HxsynFlagEnHi"] = &AMACv2Reg::HxsynFlagEnHi;
-  HxsynFlagEnLo.initReg(m_cfg, RW, 0, 1, 0, 95, "HxsynFlagEnLo"); regMap["HxsynFlagEnLo"] = &AMACv2Reg::HxsynFlagEnLo;
+  WRNsynFlagEnHi.initReg(m_cfg, RW, 0, 1, 21, 95, "WRNsynFlagEnHi"); m_fieldMap["WRNsynFlagEnHi"] = &AMACv2Reg::WRNsynFlagEnHi;
+  WRNsynFlagEnLo.initReg(m_cfg, RW, 0, 1, 20, 95, "WRNsynFlagEnLo"); m_fieldMap["WRNsynFlagEnLo"] = &AMACv2Reg::WRNsynFlagEnLo;
+  DCDCsynFlagEnHi.initReg(m_cfg, RW, 0, 1, 17, 95, "DCDCsynFlagEnHi"); m_fieldMap["DCDCsynFlagEnHi"] = &AMACv2Reg::DCDCsynFlagEnHi;
+  DCDCsynFlagEnLo.initReg(m_cfg, RW, 0, 1, 16, 95, "DCDCsynFlagEnLo"); m_fieldMap["DCDCsynFlagEnLo"] = &AMACv2Reg::DCDCsynFlagEnLo;
+  HV2synFlagEnHi.initReg(m_cfg, RW, 0, 1, 13, 95, "HV2synFlagEnHi"); m_fieldMap["HV2synFlagEnHi"] = &AMACv2Reg::HV2synFlagEnHi;
+  HV2synFlagEnLo.initReg(m_cfg, RW, 0, 1, 12, 95, "HV2synFlagEnLo"); m_fieldMap["HV2synFlagEnLo"] = &AMACv2Reg::HV2synFlagEnLo;
+  HV0synFlagEnHi.initReg(m_cfg, RW, 0, 1, 9, 95, "HV0synFlagEnHi"); m_fieldMap["HV0synFlagEnHi"] = &AMACv2Reg::HV0synFlagEnHi;
+  HV0synFlagEnLo.initReg(m_cfg, RW, 0, 1, 8, 95, "HV0synFlagEnLo"); m_fieldMap["HV0synFlagEnLo"] = &AMACv2Reg::HV0synFlagEnLo;
+  HysynFlagEnHi.initReg(m_cfg, RW, 0, 1, 5, 95, "HysynFlagEnHi"); m_fieldMap["HysynFlagEnHi"] = &AMACv2Reg::HysynFlagEnHi;
+  HysynFlagEnLo.initReg(m_cfg, RW, 0, 1, 4, 95, "HysynFlagEnLo"); m_fieldMap["HysynFlagEnLo"] = &AMACv2Reg::HysynFlagEnLo;
+  HxsynFlagEnHi.initReg(m_cfg, RW, 0, 1, 1, 95, "HxsynFlagEnHi"); m_fieldMap["HxsynFlagEnHi"] = &AMACv2Reg::HxsynFlagEnHi;
+  HxsynFlagEnLo.initReg(m_cfg, RW, 0, 1, 0, 95, "HxsynFlagEnLo"); m_fieldMap["HxsynFlagEnLo"] = &AMACv2Reg::HxsynFlagEnLo;
   // 100 - HxLoTh0
-  HxLoThCh0.initReg(m_cfg, RW, 0, 10, 0, 100, "HxLoThCh0"); regMap["HxLoThCh0"] = &AMACv2Reg::HxLoThCh0;
-  HxLoThCh1.initReg(m_cfg, RW, 0, 10, 10, 100, "HxLoThCh1"); regMap["HxLoThCh1"] = &AMACv2Reg::HxLoThCh1;
-  HxLoThCh2.initReg(m_cfg, RW, 0, 10, 20, 100, "HxLoThCh2"); regMap["HxLoThCh2"] = &AMACv2Reg::HxLoThCh2;
+  HxLoThCh0.initReg(m_cfg, RW, 0, 10, 0, 100, "HxLoThCh0"); m_fieldMap["HxLoThCh0"] = &AMACv2Reg::HxLoThCh0;
+  HxLoThCh1.initReg(m_cfg, RW, 0, 10, 10, 100, "HxLoThCh1"); m_fieldMap["HxLoThCh1"] = &AMACv2Reg::HxLoThCh1;
+  HxLoThCh2.initReg(m_cfg, RW, 0, 10, 20, 100, "HxLoThCh2"); m_fieldMap["HxLoThCh2"] = &AMACv2Reg::HxLoThCh2;
   // 101 - HxLoTh1
-  HxLoThCh3.initReg(m_cfg, RW, 0, 10, 0, 101, "HxLoThCh3"); regMap["HxLoThCh3"] = &AMACv2Reg::HxLoThCh3;
-  HxLoThCh4.initReg(m_cfg, RW, 0, 10, 10, 101, "HxLoThCh4"); regMap["HxLoThCh4"] = &AMACv2Reg::HxLoThCh4;
-  HxLoThCh5.initReg(m_cfg, RW, 0, 10, 20, 101, "HxLoThCh5"); regMap["HxLoThCh5"] = &AMACv2Reg::HxLoThCh5;
+  HxLoThCh3.initReg(m_cfg, RW, 0, 10, 0, 101, "HxLoThCh3"); m_fieldMap["HxLoThCh3"] = &AMACv2Reg::HxLoThCh3;
+  HxLoThCh4.initReg(m_cfg, RW, 0, 10, 10, 101, "HxLoThCh4"); m_fieldMap["HxLoThCh4"] = &AMACv2Reg::HxLoThCh4;
+  HxLoThCh5.initReg(m_cfg, RW, 0, 10, 20, 101, "HxLoThCh5"); m_fieldMap["HxLoThCh5"] = &AMACv2Reg::HxLoThCh5;
   // 102 - HxLoTh2
-  HxLoThCh6.initReg(m_cfg, RW, 0, 10, 0, 102, "HxLoThCh6"); regMap["HxLoThCh6"] = &AMACv2Reg::HxLoThCh6;
-  HxLoThCh7.initReg(m_cfg, RW, 0, 10, 10, 102, "HxLoThCh7"); regMap["HxLoThCh7"] = &AMACv2Reg::HxLoThCh7;
-  HxLoThCh8.initReg(m_cfg, RW, 0, 10, 20, 102, "HxLoThCh8"); regMap["HxLoThCh8"] = &AMACv2Reg::HxLoThCh8;
+  HxLoThCh6.initReg(m_cfg, RW, 0, 10, 0, 102, "HxLoThCh6"); m_fieldMap["HxLoThCh6"] = &AMACv2Reg::HxLoThCh6;
+  HxLoThCh7.initReg(m_cfg, RW, 0, 10, 10, 102, "HxLoThCh7"); m_fieldMap["HxLoThCh7"] = &AMACv2Reg::HxLoThCh7;
+  HxLoThCh8.initReg(m_cfg, RW, 0, 10, 20, 102, "HxLoThCh8"); m_fieldMap["HxLoThCh8"] = &AMACv2Reg::HxLoThCh8;
   // 103 - HxLoTh3
-  HxLoThCh9.initReg(m_cfg, RW, 0, 10, 0, 103, "HxLoThCh9"); regMap["HxLoThCh9"] = &AMACv2Reg::HxLoThCh9;
-  HxLoThCh10.initReg(m_cfg, RW, 0, 10, 10, 103, "HxLoThCh10"); regMap["HxLoThCh10"] = &AMACv2Reg::HxLoThCh10;
-  HxLoThCh11.initReg(m_cfg, RW, 0, 10, 20, 103, "HxLoThCh11"); regMap["HxLoThCh11"] = &AMACv2Reg::HxLoThCh11;
+  HxLoThCh9.initReg(m_cfg, RW, 0, 10, 0, 103, "HxLoThCh9"); m_fieldMap["HxLoThCh9"] = &AMACv2Reg::HxLoThCh9;
+  HxLoThCh10.initReg(m_cfg, RW, 0, 10, 10, 103, "HxLoThCh10"); m_fieldMap["HxLoThCh10"] = &AMACv2Reg::HxLoThCh10;
+  HxLoThCh11.initReg(m_cfg, RW, 0, 10, 20, 103, "HxLoThCh11"); m_fieldMap["HxLoThCh11"] = &AMACv2Reg::HxLoThCh11;
   // 104 - HxLoTh4
-  HxLoThCh12.initReg(m_cfg, RW, 0, 10, 0, 104, "HxLoThCh12"); regMap["HxLoThCh12"] = &AMACv2Reg::HxLoThCh12;
-  HxLoThCh13.initReg(m_cfg, RW, 0, 10, 10, 104, "HxLoThCh13"); regMap["HxLoThCh13"] = &AMACv2Reg::HxLoThCh13;
-  HxLoThCh14.initReg(m_cfg, RW, 0, 10, 20, 104, "HxLoThCh14"); regMap["HxLoThCh14"] = &AMACv2Reg::HxLoThCh14;
+  HxLoThCh12.initReg(m_cfg, RW, 0, 10, 0, 104, "HxLoThCh12"); m_fieldMap["HxLoThCh12"] = &AMACv2Reg::HxLoThCh12;
+  HxLoThCh13.initReg(m_cfg, RW, 0, 10, 10, 104, "HxLoThCh13"); m_fieldMap["HxLoThCh13"] = &AMACv2Reg::HxLoThCh13;
+  HxLoThCh14.initReg(m_cfg, RW, 0, 10, 20, 104, "HxLoThCh14"); m_fieldMap["HxLoThCh14"] = &AMACv2Reg::HxLoThCh14;
   // 105 - HxLoTh5
-  HxLoThCh15.initReg(m_cfg, RW, 0, 10, 0, 105, "HxLoThCh15"); regMap["HxLoThCh15"] = &AMACv2Reg::HxLoThCh15;
+  HxLoThCh15.initReg(m_cfg, RW, 0, 10, 0, 105, "HxLoThCh15"); m_fieldMap["HxLoThCh15"] = &AMACv2Reg::HxLoThCh15;
   // 106 - HxHiTh0
-  HxHiThCh0.initReg(m_cfg, RW, 0x3FF, 10, 0, 106, "HxLoThCh0"); regMap["HxLoThCh0"] = &AMACv2Reg::HxLoThCh0;
-  HxHiThCh1.initReg(m_cfg, RW, 0x3FF, 10, 10, 106, "HxLoThCh1"); regMap["HxLoThCh1"] = &AMACv2Reg::HxLoThCh1;
-  HxHiThCh2.initReg(m_cfg, RW, 0x3FF, 10, 20, 106, "HxLoThCh2"); regMap["HxLoThCh2"] = &AMACv2Reg::HxLoThCh2;
+  HxHiThCh0.initReg(m_cfg, RW, 0x3FF, 10, 0, 106, "HxLoThCh0"); m_fieldMap["HxLoThCh0"] = &AMACv2Reg::HxLoThCh0;
+  HxHiThCh1.initReg(m_cfg, RW, 0x3FF, 10, 10, 106, "HxLoThCh1"); m_fieldMap["HxLoThCh1"] = &AMACv2Reg::HxLoThCh1;
+  HxHiThCh2.initReg(m_cfg, RW, 0x3FF, 10, 20, 106, "HxLoThCh2"); m_fieldMap["HxLoThCh2"] = &AMACv2Reg::HxLoThCh2;
   // 107 - HxHiTh1
-  HxHiThCh3.initReg(m_cfg, RW, 0x3FF, 10, 0, 107, "HxHiThCh3"); regMap["HxHiThCh3"] = &AMACv2Reg::HxHiThCh3;
-  HxHiThCh4.initReg(m_cfg, RW, 0x3FF, 10, 10, 107, "HxHiThCh4"); regMap["HxHiThCh4"] = &AMACv2Reg::HxHiThCh4;
-  HxHiThCh5.initReg(m_cfg, RW, 0x3FF, 10, 20, 107, "HxHiThCh5"); regMap["HxHiThCh5"] = &AMACv2Reg::HxHiThCh5;
+  HxHiThCh3.initReg(m_cfg, RW, 0x3FF, 10, 0, 107, "HxHiThCh3"); m_fieldMap["HxHiThCh3"] = &AMACv2Reg::HxHiThCh3;
+  HxHiThCh4.initReg(m_cfg, RW, 0x3FF, 10, 10, 107, "HxHiThCh4"); m_fieldMap["HxHiThCh4"] = &AMACv2Reg::HxHiThCh4;
+  HxHiThCh5.initReg(m_cfg, RW, 0x3FF, 10, 20, 107, "HxHiThCh5"); m_fieldMap["HxHiThCh5"] = &AMACv2Reg::HxHiThCh5;
   // 108 - HxHiTh2
-  HxHiThCh6.initReg(m_cfg, RW, 0x3FF, 10, 0, 108, "HxHiThCh6"); regMap["HxHiThCh6"] = &AMACv2Reg::HxHiThCh6;
-  HxHiThCh7.initReg(m_cfg, RW, 0x3FF, 10, 10, 108, "HxHiThCh7"); regMap["HxHiThCh7"] = &AMACv2Reg::HxHiThCh7;
-  HxHiThCh8.initReg(m_cfg, RW, 0x3FF, 10, 20, 108, "HxHiThCh8"); regMap["HxHiThCh8"] = &AMACv2Reg::HxHiThCh8;
+  HxHiThCh6.initReg(m_cfg, RW, 0x3FF, 10, 0, 108, "HxHiThCh6"); m_fieldMap["HxHiThCh6"] = &AMACv2Reg::HxHiThCh6;
+  HxHiThCh7.initReg(m_cfg, RW, 0x3FF, 10, 10, 108, "HxHiThCh7"); m_fieldMap["HxHiThCh7"] = &AMACv2Reg::HxHiThCh7;
+  HxHiThCh8.initReg(m_cfg, RW, 0x3FF, 10, 20, 108, "HxHiThCh8"); m_fieldMap["HxHiThCh8"] = &AMACv2Reg::HxHiThCh8;
   // 109 - HxHiTh3
-  HxHiThCh9.initReg(m_cfg, RW, 0x3FF, 10, 0, 109, "HxHiThCh9"); regMap["HxHiThCh9"] = &AMACv2Reg::HxHiThCh9;
-  HxHiThCh10.initReg(m_cfg, RW, 0x3FF, 10, 10, 109, "HxHiThCh10"); regMap["HxHiThCh10"] = &AMACv2Reg::HxHiThCh10;
-  HxHiThCh11.initReg(m_cfg, RW, 0x3FF, 10, 20, 109, "HxHiThCh11"); regMap["HxHiThCh11"] = &AMACv2Reg::HxHiThCh11;
+  HxHiThCh9.initReg(m_cfg, RW, 0x3FF, 10, 0, 109, "HxHiThCh9"); m_fieldMap["HxHiThCh9"] = &AMACv2Reg::HxHiThCh9;
+  HxHiThCh10.initReg(m_cfg, RW, 0x3FF, 10, 10, 109, "HxHiThCh10"); m_fieldMap["HxHiThCh10"] = &AMACv2Reg::HxHiThCh10;
+  HxHiThCh11.initReg(m_cfg, RW, 0x3FF, 10, 20, 109, "HxHiThCh11"); m_fieldMap["HxHiThCh11"] = &AMACv2Reg::HxHiThCh11;
   // 110 - HxHiTh4
-  HxHiThCh12.initReg(m_cfg, RW, 0x3FF, 10, 0, 110, "HxHiThCh12"); regMap["HxHiThCh12"] = &AMACv2Reg::HxHiThCh12;
-  HxHiThCh13.initReg(m_cfg, RW, 0x3FF, 10, 10, 110, "HxHiThCh13"); regMap["HxHiThCh13"] = &AMACv2Reg::HxHiThCh13;
-  HxHiThCh14.initReg(m_cfg, RW, 0x3FF, 10, 20, 110, "HxHiThCh14"); regMap["HxHiThCh14"] = &AMACv2Reg::HxHiThCh14;
+  HxHiThCh12.initReg(m_cfg, RW, 0x3FF, 10, 0, 110, "HxHiThCh12"); m_fieldMap["HxHiThCh12"] = &AMACv2Reg::HxHiThCh12;
+  HxHiThCh13.initReg(m_cfg, RW, 0x3FF, 10, 10, 110, "HxHiThCh13"); m_fieldMap["HxHiThCh13"] = &AMACv2Reg::HxHiThCh13;
+  HxHiThCh14.initReg(m_cfg, RW, 0x3FF, 10, 20, 110, "HxHiThCh14"); m_fieldMap["HxHiThCh14"] = &AMACv2Reg::HxHiThCh14;
   // 111 - HxHiTh5
-  HxHiThCh15.initReg(m_cfg, RW, 0x3FF, 10, 0, 111, "HxHiThCh15"); regMap["HxHiThCh15"] = &AMACv2Reg::HxHiThCh15;
+  HxHiThCh15.initReg(m_cfg, RW, 0x3FF, 10, 0, 111, "HxHiThCh15"); m_fieldMap["HxHiThCh15"] = &AMACv2Reg::HxHiThCh15;
   // 112 - HyLoTh0
-  HyLoThCh0.initReg(m_cfg, RW, 0, 10, 0, 112, "HyLoThCh0"); regMap["HyLoThCh0"] = &AMACv2Reg::HyLoThCh0;
-  HyLoThCh1.initReg(m_cfg, RW, 0, 10, 10, 112, "HyLoThCh1"); regMap["HyLoThCh1"] = &AMACv2Reg::HyLoThCh1;
-  HyLoThCh2.initReg(m_cfg, RW, 0, 10, 20, 112, "HyLoThCh2"); regMap["HyLoThCh2"] = &AMACv2Reg::HyLoThCh2;
+  HyLoThCh0.initReg(m_cfg, RW, 0, 10, 0, 112, "HyLoThCh0"); m_fieldMap["HyLoThCh0"] = &AMACv2Reg::HyLoThCh0;
+  HyLoThCh1.initReg(m_cfg, RW, 0, 10, 10, 112, "HyLoThCh1"); m_fieldMap["HyLoThCh1"] = &AMACv2Reg::HyLoThCh1;
+  HyLoThCh2.initReg(m_cfg, RW, 0, 10, 20, 112, "HyLoThCh2"); m_fieldMap["HyLoThCh2"] = &AMACv2Reg::HyLoThCh2;
   // 113 - HyLoTh1
-  HyLoThCh3.initReg(m_cfg, RW, 0, 10, 0, 113, "HyLoThCh3"); regMap["HyLoThCh3"] = &AMACv2Reg::HyLoThCh3;
-  HyLoThCh4.initReg(m_cfg, RW, 0, 10, 10, 113, "HyLoThCh4"); regMap["HyLoThCh4"] = &AMACv2Reg::HyLoThCh4;
-  HyLoThCh5.initReg(m_cfg, RW, 0, 10, 20, 113, "HyLoThCh5"); regMap["HyLoThCh5"] = &AMACv2Reg::HyLoThCh5;
+  HyLoThCh3.initReg(m_cfg, RW, 0, 10, 0, 113, "HyLoThCh3"); m_fieldMap["HyLoThCh3"] = &AMACv2Reg::HyLoThCh3;
+  HyLoThCh4.initReg(m_cfg, RW, 0, 10, 10, 113, "HyLoThCh4"); m_fieldMap["HyLoThCh4"] = &AMACv2Reg::HyLoThCh4;
+  HyLoThCh5.initReg(m_cfg, RW, 0, 10, 20, 113, "HyLoThCh5"); m_fieldMap["HyLoThCh5"] = &AMACv2Reg::HyLoThCh5;
   // 114 - HyLoTh2
-  HyLoThCh6.initReg(m_cfg, RW, 0, 10, 0, 114, "HyLoThCh6"); regMap["HyLoThCh6"] = &AMACv2Reg::HyLoThCh6;
-  HyLoThCh7.initReg(m_cfg, RW, 0, 10, 10, 114, "HyLoThCh7"); regMap["HyLoThCh7"] = &AMACv2Reg::HyLoThCh7;
-  HyLoThCh8.initReg(m_cfg, RW, 0, 10, 20, 114, "HyLoThCh8"); regMap["HyLoThCh8"] = &AMACv2Reg::HyLoThCh8;
+  HyLoThCh6.initReg(m_cfg, RW, 0, 10, 0, 114, "HyLoThCh6"); m_fieldMap["HyLoThCh6"] = &AMACv2Reg::HyLoThCh6;
+  HyLoThCh7.initReg(m_cfg, RW, 0, 10, 10, 114, "HyLoThCh7"); m_fieldMap["HyLoThCh7"] = &AMACv2Reg::HyLoThCh7;
+  HyLoThCh8.initReg(m_cfg, RW, 0, 10, 20, 114, "HyLoThCh8"); m_fieldMap["HyLoThCh8"] = &AMACv2Reg::HyLoThCh8;
   // 115 - HyLoTh3
-  HyLoThCh9.initReg(m_cfg, RW, 0, 10, 0, 115, "HyLoThCh9"); regMap["HyLoThCh9"] = &AMACv2Reg::HyLoThCh9;
-  HyLoThCh10.initReg(m_cfg, RW, 0, 10, 10, 115, "HyLoThCh10"); regMap["HyLoThCh10"] = &AMACv2Reg::HyLoThCh10;
-  HyLoThCh11.initReg(m_cfg, RW, 0, 10, 20, 115, "HyLoThCh11"); regMap["HyLoThCh11"] = &AMACv2Reg::HyLoThCh11;
+  HyLoThCh9.initReg(m_cfg, RW, 0, 10, 0, 115, "HyLoThCh9"); m_fieldMap["HyLoThCh9"] = &AMACv2Reg::HyLoThCh9;
+  HyLoThCh10.initReg(m_cfg, RW, 0, 10, 10, 115, "HyLoThCh10"); m_fieldMap["HyLoThCh10"] = &AMACv2Reg::HyLoThCh10;
+  HyLoThCh11.initReg(m_cfg, RW, 0, 10, 20, 115, "HyLoThCh11"); m_fieldMap["HyLoThCh11"] = &AMACv2Reg::HyLoThCh11;
   // 116 - HyLoTh4
-  HyLoThCh12.initReg(m_cfg, RW, 0, 10, 0, 116, "HyLoThCh12"); regMap["HyLoThCh12"] = &AMACv2Reg::HyLoThCh12;
-  HyLoThCh13.initReg(m_cfg, RW, 0, 10, 10, 116, "HyLoThCh13"); regMap["HyLoThCh13"] = &AMACv2Reg::HyLoThCh13;
-  HyLoThCh14.initReg(m_cfg, RW, 0, 10, 20, 116, "HyLoThCh14"); regMap["HyLoThCh14"] = &AMACv2Reg::HyLoThCh14;
+  HyLoThCh12.initReg(m_cfg, RW, 0, 10, 0, 116, "HyLoThCh12"); m_fieldMap["HyLoThCh12"] = &AMACv2Reg::HyLoThCh12;
+  HyLoThCh13.initReg(m_cfg, RW, 0, 10, 10, 116, "HyLoThCh13"); m_fieldMap["HyLoThCh13"] = &AMACv2Reg::HyLoThCh13;
+  HyLoThCh14.initReg(m_cfg, RW, 0, 10, 20, 116, "HyLoThCh14"); m_fieldMap["HyLoThCh14"] = &AMACv2Reg::HyLoThCh14;
   // 117 - HyLoTh5
-  HyLoThCh15.initReg(m_cfg, RW, 0, 10, 0, 117, "HyLoThCh15"); regMap["HyLoThCh15"] = &AMACv2Reg::HyLoThCh15;
+  HyLoThCh15.initReg(m_cfg, RW, 0, 10, 0, 117, "HyLoThCh15"); m_fieldMap["HyLoThCh15"] = &AMACv2Reg::HyLoThCh15;
   // 118 - HyHiTh0
-  HyHiThCh0.initReg(m_cfg, RW, 0x3FF, 10, 0, 118, "HyLoThCh0"); regMap["HyLoThCh0"] = &AMACv2Reg::HyLoThCh0;
-  HyHiThCh1.initReg(m_cfg, RW, 0x3FF, 10, 10, 118, "HyLoThCh1"); regMap["HyLoThCh1"] = &AMACv2Reg::HyLoThCh1;
-  HyHiThCh2.initReg(m_cfg, RW, 0x3FF, 10, 20, 118, "HyLoThCh2"); regMap["HyLoThCh2"] = &AMACv2Reg::HyLoThCh2;
+  HyHiThCh0.initReg(m_cfg, RW, 0x3FF, 10, 0, 118, "HyLoThCh0"); m_fieldMap["HyLoThCh0"] = &AMACv2Reg::HyLoThCh0;
+  HyHiThCh1.initReg(m_cfg, RW, 0x3FF, 10, 10, 118, "HyLoThCh1"); m_fieldMap["HyLoThCh1"] = &AMACv2Reg::HyLoThCh1;
+  HyHiThCh2.initReg(m_cfg, RW, 0x3FF, 10, 20, 118, "HyLoThCh2"); m_fieldMap["HyLoThCh2"] = &AMACv2Reg::HyLoThCh2;
   // 119 - HyHiTh1
-  HyHiThCh3.initReg(m_cfg, RW, 0x3FF, 10, 0, 119, "HyHiThCh3"); regMap["HyHiThCh3"] = &AMACv2Reg::HyHiThCh3;
-  HyHiThCh4.initReg(m_cfg, RW, 0x3FF, 10, 10, 119, "HyHiThCh4"); regMap["HyHiThCh4"] = &AMACv2Reg::HyHiThCh4;
-  HyHiThCh5.initReg(m_cfg, RW, 0x3FF, 10, 20, 119, "HyHiThCh5"); regMap["HyHiThCh5"] = &AMACv2Reg::HyHiThCh5;
+  HyHiThCh3.initReg(m_cfg, RW, 0x3FF, 10, 0, 119, "HyHiThCh3"); m_fieldMap["HyHiThCh3"] = &AMACv2Reg::HyHiThCh3;
+  HyHiThCh4.initReg(m_cfg, RW, 0x3FF, 10, 10, 119, "HyHiThCh4"); m_fieldMap["HyHiThCh4"] = &AMACv2Reg::HyHiThCh4;
+  HyHiThCh5.initReg(m_cfg, RW, 0x3FF, 10, 20, 119, "HyHiThCh5"); m_fieldMap["HyHiThCh5"] = &AMACv2Reg::HyHiThCh5;
   // 120 - HyHiTh2
-  HyHiThCh6.initReg(m_cfg, RW, 0x3FF, 10, 0, 120, "HyHiThCh6"); regMap["HyHiThCh6"] = &AMACv2Reg::HyHiThCh6;
-  HyHiThCh7.initReg(m_cfg, RW, 0x3FF, 10, 10, 120, "HyHiThCh7"); regMap["HyHiThCh7"] = &AMACv2Reg::HyHiThCh7;
-  HyHiThCh8.initReg(m_cfg, RW, 0x3FF, 10, 20, 120, "HyHiThCh8"); regMap["HyHiThCh8"] = &AMACv2Reg::HyHiThCh8;
+  HyHiThCh6.initReg(m_cfg, RW, 0x3FF, 10, 0, 120, "HyHiThCh6"); m_fieldMap["HyHiThCh6"] = &AMACv2Reg::HyHiThCh6;
+  HyHiThCh7.initReg(m_cfg, RW, 0x3FF, 10, 10, 120, "HyHiThCh7"); m_fieldMap["HyHiThCh7"] = &AMACv2Reg::HyHiThCh7;
+  HyHiThCh8.initReg(m_cfg, RW, 0x3FF, 10, 20, 120, "HyHiThCh8"); m_fieldMap["HyHiThCh8"] = &AMACv2Reg::HyHiThCh8;
   // 121 - HyHiTh3
-  HyHiThCh9.initReg(m_cfg, RW, 0x3FF, 10, 0, 121, "HyHiThCh9"); regMap["HyHiThCh9"] = &AMACv2Reg::HyHiThCh9;
-  HyHiThCh10.initReg(m_cfg, RW, 0x3FF, 10, 10, 121, "HyHiThCh10"); regMap["HyHiThCh10"] = &AMACv2Reg::HyHiThCh10;
-  HyHiThCh11.initReg(m_cfg, RW, 0x3FF, 10, 20, 121, "HyHiThCh11"); regMap["HyHiThCh11"] = &AMACv2Reg::HyHiThCh11;
+  HyHiThCh9.initReg(m_cfg, RW, 0x3FF, 10, 0, 121, "HyHiThCh9"); m_fieldMap["HyHiThCh9"] = &AMACv2Reg::HyHiThCh9;
+  HyHiThCh10.initReg(m_cfg, RW, 0x3FF, 10, 10, 121, "HyHiThCh10"); m_fieldMap["HyHiThCh10"] = &AMACv2Reg::HyHiThCh10;
+  HyHiThCh11.initReg(m_cfg, RW, 0x3FF, 10, 20, 121, "HyHiThCh11"); m_fieldMap["HyHiThCh11"] = &AMACv2Reg::HyHiThCh11;
   // 122 - HyHiTh4
-  HyHiThCh12.initReg(m_cfg, RW, 0x3FF, 10, 0, 122, "HyHiThCh12"); regMap["HyHiThCh12"] = &AMACv2Reg::HyHiThCh12;
-  HyHiThCh13.initReg(m_cfg, RW, 0x3FF, 10, 10, 122, "HyHiThCh13"); regMap["HyHiThCh13"] = &AMACv2Reg::HyHiThCh13;
-  HyHiThCh14.initReg(m_cfg, RW, 0x3FF, 10, 20, 122, "HyHiThCh14"); regMap["HyHiThCh14"] = &AMACv2Reg::HyHiThCh14;
+  HyHiThCh12.initReg(m_cfg, RW, 0x3FF, 10, 0, 122, "HyHiThCh12"); m_fieldMap["HyHiThCh12"] = &AMACv2Reg::HyHiThCh12;
+  HyHiThCh13.initReg(m_cfg, RW, 0x3FF, 10, 10, 122, "HyHiThCh13"); m_fieldMap["HyHiThCh13"] = &AMACv2Reg::HyHiThCh13;
+  HyHiThCh14.initReg(m_cfg, RW, 0x3FF, 10, 20, 122, "HyHiThCh14"); m_fieldMap["HyHiThCh14"] = &AMACv2Reg::HyHiThCh14;
   // 123 - HyHiTh5
-  HyHiThCh15.initReg(m_cfg, RW, 0x3FF, 10, 0, 123, "HyHiThCh15"); regMap["HyHiThCh15"] = &AMACv2Reg::HyHiThCh15;
+  HyHiThCh15.initReg(m_cfg, RW, 0x3FF, 10, 0, 123, "HyHiThCh15"); m_fieldMap["HyHiThCh15"] = &AMACv2Reg::HyHiThCh15;
   // 124 - HV0LoTh0
-  HV0LoThCh0.initReg(m_cfg, RW, 0, 10, 0, 124, "HV0LoThCh0"); regMap["HV0LoThCh0"] = &AMACv2Reg::HV0LoThCh0;
-  HV0LoThCh1.initReg(m_cfg, RW, 0, 10, 10, 124, "HV0LoThCh1"); regMap["HV0LoThCh1"] = &AMACv2Reg::HV0LoThCh1;
-  HV0LoThCh2.initReg(m_cfg, RW, 0, 10, 20, 124, "HV0LoThCh2"); regMap["HV0LoThCh2"] = &AMACv2Reg::HV0LoThCh2;
+  HV0LoThCh0.initReg(m_cfg, RW, 0, 10, 0, 124, "HV0LoThCh0"); m_fieldMap["HV0LoThCh0"] = &AMACv2Reg::HV0LoThCh0;
+  HV0LoThCh1.initReg(m_cfg, RW, 0, 10, 10, 124, "HV0LoThCh1"); m_fieldMap["HV0LoThCh1"] = &AMACv2Reg::HV0LoThCh1;
+  HV0LoThCh2.initReg(m_cfg, RW, 0, 10, 20, 124, "HV0LoThCh2"); m_fieldMap["HV0LoThCh2"] = &AMACv2Reg::HV0LoThCh2;
   // 125 - HV0LoTh1
-  HV0LoThCh3.initReg(m_cfg, RW, 0, 10, 0, 125, "HV0LoThCh3"); regMap["HV0LoThCh3"] = &AMACv2Reg::HV0LoThCh3;
-  HV0LoThCh4.initReg(m_cfg, RW, 0, 10, 10, 125, "HV0LoThCh4"); regMap["HV0LoThCh4"] = &AMACv2Reg::HV0LoThCh4;
-  HV0LoThCh5.initReg(m_cfg, RW, 0, 10, 20, 125, "HV0LoThCh5"); regMap["HV0LoThCh5"] = &AMACv2Reg::HV0LoThCh5;
+  HV0LoThCh3.initReg(m_cfg, RW, 0, 10, 0, 125, "HV0LoThCh3"); m_fieldMap["HV0LoThCh3"] = &AMACv2Reg::HV0LoThCh3;
+  HV0LoThCh4.initReg(m_cfg, RW, 0, 10, 10, 125, "HV0LoThCh4"); m_fieldMap["HV0LoThCh4"] = &AMACv2Reg::HV0LoThCh4;
+  HV0LoThCh5.initReg(m_cfg, RW, 0, 10, 20, 125, "HV0LoThCh5"); m_fieldMap["HV0LoThCh5"] = &AMACv2Reg::HV0LoThCh5;
   // 126 - HV0LoTh2
-  HV0LoThCh6.initReg(m_cfg, RW, 0, 10, 0, 126, "HV0LoThCh6"); regMap["HV0LoThCh6"] = &AMACv2Reg::HV0LoThCh6;
-  HV0LoThCh7.initReg(m_cfg, RW, 0, 10, 10, 126, "HV0LoThCh7"); regMap["HV0LoThCh7"] = &AMACv2Reg::HV0LoThCh7;
-  HV0LoThCh8.initReg(m_cfg, RW, 0, 10, 20, 126, "HV0LoThCh8"); regMap["HV0LoThCh8"] = &AMACv2Reg::HV0LoThCh8;
+  HV0LoThCh6.initReg(m_cfg, RW, 0, 10, 0, 126, "HV0LoThCh6"); m_fieldMap["HV0LoThCh6"] = &AMACv2Reg::HV0LoThCh6;
+  HV0LoThCh7.initReg(m_cfg, RW, 0, 10, 10, 126, "HV0LoThCh7"); m_fieldMap["HV0LoThCh7"] = &AMACv2Reg::HV0LoThCh7;
+  HV0LoThCh8.initReg(m_cfg, RW, 0, 10, 20, 126, "HV0LoThCh8"); m_fieldMap["HV0LoThCh8"] = &AMACv2Reg::HV0LoThCh8;
   // 127 - HV0LoTh3
-  HV0LoThCh9.initReg(m_cfg, RW, 0, 10, 0, 127, "HV0LoThCh9"); regMap["HV0LoThCh9"] = &AMACv2Reg::HV0LoThCh9;
-  HV0LoThCh10.initReg(m_cfg, RW, 0, 10, 10, 127, "HV0LoThCh10"); regMap["HV0LoThCh10"] = &AMACv2Reg::HV0LoThCh10;
-  HV0LoThCh11.initReg(m_cfg, RW, 0, 10, 20, 127, "HV0LoThCh11"); regMap["HV0LoThCh11"] = &AMACv2Reg::HV0LoThCh11;
+  HV0LoThCh9.initReg(m_cfg, RW, 0, 10, 0, 127, "HV0LoThCh9"); m_fieldMap["HV0LoThCh9"] = &AMACv2Reg::HV0LoThCh9;
+  HV0LoThCh10.initReg(m_cfg, RW, 0, 10, 10, 127, "HV0LoThCh10"); m_fieldMap["HV0LoThCh10"] = &AMACv2Reg::HV0LoThCh10;
+  HV0LoThCh11.initReg(m_cfg, RW, 0, 10, 20, 127, "HV0LoThCh11"); m_fieldMap["HV0LoThCh11"] = &AMACv2Reg::HV0LoThCh11;
   // 128 - HV0LoTh4
-  HV0LoThCh12.initReg(m_cfg, RW, 0, 10, 0, 128, "HV0LoThCh12"); regMap["HV0LoThCh12"] = &AMACv2Reg::HV0LoThCh12;
-  HV0LoThCh13.initReg(m_cfg, RW, 0, 10, 10, 128, "HV0LoThCh13"); regMap["HV0LoThCh13"] = &AMACv2Reg::HV0LoThCh13;
-  HV0LoThCh14.initReg(m_cfg, RW, 0, 10, 20, 128, "HV0LoThCh14"); regMap["HV0LoThCh14"] = &AMACv2Reg::HV0LoThCh14;
+  HV0LoThCh12.initReg(m_cfg, RW, 0, 10, 0, 128, "HV0LoThCh12"); m_fieldMap["HV0LoThCh12"] = &AMACv2Reg::HV0LoThCh12;
+  HV0LoThCh13.initReg(m_cfg, RW, 0, 10, 10, 128, "HV0LoThCh13"); m_fieldMap["HV0LoThCh13"] = &AMACv2Reg::HV0LoThCh13;
+  HV0LoThCh14.initReg(m_cfg, RW, 0, 10, 20, 128, "HV0LoThCh14"); m_fieldMap["HV0LoThCh14"] = &AMACv2Reg::HV0LoThCh14;
   // 129 - HV0LoTh5
-  HV0LoThCh15.initReg(m_cfg, RW, 0, 10, 0, 129, "HV0LoThCh15"); regMap["HV0LoThCh15"] = &AMACv2Reg::HV0LoThCh15;
+  HV0LoThCh15.initReg(m_cfg, RW, 0, 10, 0, 129, "HV0LoThCh15"); m_fieldMap["HV0LoThCh15"] = &AMACv2Reg::HV0LoThCh15;
   // 130 - HV0HiTh0
-  HV0HiThCh0.initReg(m_cfg, RW, 0x3FF, 10, 0, 130, "HV0LoThCh0"); regMap["HV0LoThCh0"] = &AMACv2Reg::HV0LoThCh0;
-  HV0HiThCh1.initReg(m_cfg, RW, 0x3FF, 10, 10, 130, "HV0LoThCh1"); regMap["HV0LoThCh1"] = &AMACv2Reg::HV0LoThCh1;
-  HV0HiThCh2.initReg(m_cfg, RW, 0x3FF, 10, 20, 130, "HV0LoThCh2"); regMap["HV0LoThCh2"] = &AMACv2Reg::HV0LoThCh2;
+  HV0HiThCh0.initReg(m_cfg, RW, 0x3FF, 10, 0, 130, "HV0LoThCh0"); m_fieldMap["HV0LoThCh0"] = &AMACv2Reg::HV0LoThCh0;
+  HV0HiThCh1.initReg(m_cfg, RW, 0x3FF, 10, 10, 130, "HV0LoThCh1"); m_fieldMap["HV0LoThCh1"] = &AMACv2Reg::HV0LoThCh1;
+  HV0HiThCh2.initReg(m_cfg, RW, 0x3FF, 10, 20, 130, "HV0LoThCh2"); m_fieldMap["HV0LoThCh2"] = &AMACv2Reg::HV0LoThCh2;
   // 131 - HV0HiTh1
-  HV0HiThCh3.initReg(m_cfg, RW, 0x3FF, 10, 0, 131, "HV0HiThCh3"); regMap["HV0HiThCh3"] = &AMACv2Reg::HV0HiThCh3;
-  HV0HiThCh4.initReg(m_cfg, RW, 0x3FF, 10, 10, 131, "HV0HiThCh4"); regMap["HV0HiThCh4"] = &AMACv2Reg::HV0HiThCh4;
-  HV0HiThCh5.initReg(m_cfg, RW, 0x3FF, 10, 20, 131, "HV0HiThCh5"); regMap["HV0HiThCh5"] = &AMACv2Reg::HV0HiThCh5;
+  HV0HiThCh3.initReg(m_cfg, RW, 0x3FF, 10, 0, 131, "HV0HiThCh3"); m_fieldMap["HV0HiThCh3"] = &AMACv2Reg::HV0HiThCh3;
+  HV0HiThCh4.initReg(m_cfg, RW, 0x3FF, 10, 10, 131, "HV0HiThCh4"); m_fieldMap["HV0HiThCh4"] = &AMACv2Reg::HV0HiThCh4;
+  HV0HiThCh5.initReg(m_cfg, RW, 0x3FF, 10, 20, 131, "HV0HiThCh5"); m_fieldMap["HV0HiThCh5"] = &AMACv2Reg::HV0HiThCh5;
   // 132 - HV0HiTh2
-  HV0HiThCh6.initReg(m_cfg, RW, 0x3FF, 10, 0, 132, "HV0HiThCh6"); regMap["HV0HiThCh6"] = &AMACv2Reg::HV0HiThCh6;
-  HV0HiThCh7.initReg(m_cfg, RW, 0x3FF, 10, 10, 132, "HV0HiThCh7"); regMap["HV0HiThCh7"] = &AMACv2Reg::HV0HiThCh7;
-  HV0HiThCh8.initReg(m_cfg, RW, 0x3FF, 10, 20, 132, "HV0HiThCh8"); regMap["HV0HiThCh8"] = &AMACv2Reg::HV0HiThCh8;
+  HV0HiThCh6.initReg(m_cfg, RW, 0x3FF, 10, 0, 132, "HV0HiThCh6"); m_fieldMap["HV0HiThCh6"] = &AMACv2Reg::HV0HiThCh6;
+  HV0HiThCh7.initReg(m_cfg, RW, 0x3FF, 10, 10, 132, "HV0HiThCh7"); m_fieldMap["HV0HiThCh7"] = &AMACv2Reg::HV0HiThCh7;
+  HV0HiThCh8.initReg(m_cfg, RW, 0x3FF, 10, 20, 132, "HV0HiThCh8"); m_fieldMap["HV0HiThCh8"] = &AMACv2Reg::HV0HiThCh8;
   // 133 - HV0HiTh3
-  HV0HiThCh9.initReg(m_cfg, RW, 0x3FF, 10, 0, 133, "HV0HiThCh9"); regMap["HV0HiThCh9"] = &AMACv2Reg::HV0HiThCh9;
-  HV0HiThCh10.initReg(m_cfg, RW, 0x3FF, 10, 10, 133, "HV0HiThCh10"); regMap["HV0HiThCh10"] = &AMACv2Reg::HV0HiThCh10;
-  HV0HiThCh11.initReg(m_cfg, RW, 0x3FF, 10, 20, 133, "HV0HiThCh11"); regMap["HV0HiThCh11"] = &AMACv2Reg::HV0HiThCh11;
+  HV0HiThCh9.initReg(m_cfg, RW, 0x3FF, 10, 0, 133, "HV0HiThCh9"); m_fieldMap["HV0HiThCh9"] = &AMACv2Reg::HV0HiThCh9;
+  HV0HiThCh10.initReg(m_cfg, RW, 0x3FF, 10, 10, 133, "HV0HiThCh10"); m_fieldMap["HV0HiThCh10"] = &AMACv2Reg::HV0HiThCh10;
+  HV0HiThCh11.initReg(m_cfg, RW, 0x3FF, 10, 20, 133, "HV0HiThCh11"); m_fieldMap["HV0HiThCh11"] = &AMACv2Reg::HV0HiThCh11;
   // 134 - HV0HiTh4
-  HV0HiThCh12.initReg(m_cfg, RW, 0x3FF, 10, 0, 134, "HV0HiThCh12"); regMap["HV0HiThCh12"] = &AMACv2Reg::HV0HiThCh12;
-  HV0HiThCh13.initReg(m_cfg, RW, 0x3FF, 10, 10, 134, "HV0HiThCh13"); regMap["HV0HiThCh13"] = &AMACv2Reg::HV0HiThCh13;
-  HV0HiThCh14.initReg(m_cfg, RW, 0x3FF, 10, 20, 134, "HV0HiThCh14"); regMap["HV0HiThCh14"] = &AMACv2Reg::HV0HiThCh14;
+  HV0HiThCh12.initReg(m_cfg, RW, 0x3FF, 10, 0, 134, "HV0HiThCh12"); m_fieldMap["HV0HiThCh12"] = &AMACv2Reg::HV0HiThCh12;
+  HV0HiThCh13.initReg(m_cfg, RW, 0x3FF, 10, 10, 134, "HV0HiThCh13"); m_fieldMap["HV0HiThCh13"] = &AMACv2Reg::HV0HiThCh13;
+  HV0HiThCh14.initReg(m_cfg, RW, 0x3FF, 10, 20, 134, "HV0HiThCh14"); m_fieldMap["HV0HiThCh14"] = &AMACv2Reg::HV0HiThCh14;
   // 135 - HV0HiTh5
-  HV0HiThCh15.initReg(m_cfg, RW, 0x3FF, 10, 0, 135, "HV0HiThCh15"); regMap["HV0HiThCh15"] = &AMACv2Reg::HV0HiThCh15;
+  HV0HiThCh15.initReg(m_cfg, RW, 0x3FF, 10, 0, 135, "HV0HiThCh15"); m_fieldMap["HV0HiThCh15"] = &AMACv2Reg::HV0HiThCh15;
   // 136 - HV2LoTh0
-  HV2LoThCh0.initReg(m_cfg, RW, 0, 10, 0, 136, "HV2LoThCh0"); regMap["HV2LoThCh0"] = &AMACv2Reg::HV2LoThCh0;
-  HV2LoThCh1.initReg(m_cfg, RW, 0, 10, 10, 136, "HV2LoThCh1"); regMap["HV2LoThCh1"] = &AMACv2Reg::HV2LoThCh1;
-  HV2LoThCh2.initReg(m_cfg, RW, 0, 10, 20, 136, "HV2LoThCh2"); regMap["HV2LoThCh2"] = &AMACv2Reg::HV2LoThCh2;
+  HV2LoThCh0.initReg(m_cfg, RW, 0, 10, 0, 136, "HV2LoThCh0"); m_fieldMap["HV2LoThCh0"] = &AMACv2Reg::HV2LoThCh0;
+  HV2LoThCh1.initReg(m_cfg, RW, 0, 10, 10, 136, "HV2LoThCh1"); m_fieldMap["HV2LoThCh1"] = &AMACv2Reg::HV2LoThCh1;
+  HV2LoThCh2.initReg(m_cfg, RW, 0, 10, 20, 136, "HV2LoThCh2"); m_fieldMap["HV2LoThCh2"] = &AMACv2Reg::HV2LoThCh2;
   // 137 - HV2LoTh1
-  HV2LoThCh3.initReg(m_cfg, RW, 0, 10, 0, 137, "HV2LoThCh3"); regMap["HV2LoThCh3"] = &AMACv2Reg::HV2LoThCh3;
-  HV2LoThCh4.initReg(m_cfg, RW, 0, 10, 10, 137, "HV2LoThCh4"); regMap["HV2LoThCh4"] = &AMACv2Reg::HV2LoThCh4;
-  HV2LoThCh5.initReg(m_cfg, RW, 0, 10, 20, 137, "HV2LoThCh5"); regMap["HV2LoThCh5"] = &AMACv2Reg::HV2LoThCh5;
+  HV2LoThCh3.initReg(m_cfg, RW, 0, 10, 0, 137, "HV2LoThCh3"); m_fieldMap["HV2LoThCh3"] = &AMACv2Reg::HV2LoThCh3;
+  HV2LoThCh4.initReg(m_cfg, RW, 0, 10, 10, 137, "HV2LoThCh4"); m_fieldMap["HV2LoThCh4"] = &AMACv2Reg::HV2LoThCh4;
+  HV2LoThCh5.initReg(m_cfg, RW, 0, 10, 20, 137, "HV2LoThCh5"); m_fieldMap["HV2LoThCh5"] = &AMACv2Reg::HV2LoThCh5;
   // 138 - HV2LoTh2
-  HV2LoThCh6.initReg(m_cfg, RW, 0, 10, 0, 138, "HV2LoThCh6"); regMap["HV2LoThCh6"] = &AMACv2Reg::HV2LoThCh6;
-  HV2LoThCh7.initReg(m_cfg, RW, 0, 10, 10, 138, "HV2LoThCh7"); regMap["HV2LoThCh7"] = &AMACv2Reg::HV2LoThCh7;
-  HV2LoThCh8.initReg(m_cfg, RW, 0, 10, 20, 138, "HV2LoThCh8"); regMap["HV2LoThCh8"] = &AMACv2Reg::HV2LoThCh8;
+  HV2LoThCh6.initReg(m_cfg, RW, 0, 10, 0, 138, "HV2LoThCh6"); m_fieldMap["HV2LoThCh6"] = &AMACv2Reg::HV2LoThCh6;
+  HV2LoThCh7.initReg(m_cfg, RW, 0, 10, 10, 138, "HV2LoThCh7"); m_fieldMap["HV2LoThCh7"] = &AMACv2Reg::HV2LoThCh7;
+  HV2LoThCh8.initReg(m_cfg, RW, 0, 10, 20, 138, "HV2LoThCh8"); m_fieldMap["HV2LoThCh8"] = &AMACv2Reg::HV2LoThCh8;
   // 139 - HV2LoTh3
-  HV2LoThCh9.initReg(m_cfg, RW, 0, 10, 0, 139, "HV2LoThCh9"); regMap["HV2LoThCh9"] = &AMACv2Reg::HV2LoThCh9;
-  HV2LoThCh10.initReg(m_cfg, RW, 0, 10, 10, 139, "HV2LoThCh10"); regMap["HV2LoThCh10"] = &AMACv2Reg::HV2LoThCh10;
-  HV2LoThCh11.initReg(m_cfg, RW, 0, 10, 20, 139, "HV2LoThCh11"); regMap["HV2LoThCh11"] = &AMACv2Reg::HV2LoThCh11;
+  HV2LoThCh9.initReg(m_cfg, RW, 0, 10, 0, 139, "HV2LoThCh9"); m_fieldMap["HV2LoThCh9"] = &AMACv2Reg::HV2LoThCh9;
+  HV2LoThCh10.initReg(m_cfg, RW, 0, 10, 10, 139, "HV2LoThCh10"); m_fieldMap["HV2LoThCh10"] = &AMACv2Reg::HV2LoThCh10;
+  HV2LoThCh11.initReg(m_cfg, RW, 0, 10, 20, 139, "HV2LoThCh11"); m_fieldMap["HV2LoThCh11"] = &AMACv2Reg::HV2LoThCh11;
   // 140 - HV2LoTh4
-  HV2LoThCh12.initReg(m_cfg, RW, 0, 10, 0, 140, "HV2LoThCh12"); regMap["HV2LoThCh12"] = &AMACv2Reg::HV2LoThCh12;
-  HV2LoThCh13.initReg(m_cfg, RW, 0, 10, 10, 140, "HV2LoThCh13"); regMap["HV2LoThCh13"] = &AMACv2Reg::HV2LoThCh13;
-  HV2LoThCh14.initReg(m_cfg, RW, 0, 10, 20, 140, "HV2LoThCh14"); regMap["HV2LoThCh14"] = &AMACv2Reg::HV2LoThCh14;
+  HV2LoThCh12.initReg(m_cfg, RW, 0, 10, 0, 140, "HV2LoThCh12"); m_fieldMap["HV2LoThCh12"] = &AMACv2Reg::HV2LoThCh12;
+  HV2LoThCh13.initReg(m_cfg, RW, 0, 10, 10, 140, "HV2LoThCh13"); m_fieldMap["HV2LoThCh13"] = &AMACv2Reg::HV2LoThCh13;
+  HV2LoThCh14.initReg(m_cfg, RW, 0, 10, 20, 140, "HV2LoThCh14"); m_fieldMap["HV2LoThCh14"] = &AMACv2Reg::HV2LoThCh14;
   // 141 - HV2LoTh5
-  HV2LoThCh15.initReg(m_cfg, RW, 0, 10, 0, 141, "HV2LoThCh15"); regMap["HV2LoThCh15"] = &AMACv2Reg::HV2LoThCh15;
+  HV2LoThCh15.initReg(m_cfg, RW, 0, 10, 0, 141, "HV2LoThCh15"); m_fieldMap["HV2LoThCh15"] = &AMACv2Reg::HV2LoThCh15;
   // 142 - HV2HiTh0
-  HV2HiThCh0.initReg(m_cfg, RW, 0x3FF, 10, 0, 142, "HV2LoThCh0"); regMap["HV2LoThCh0"] = &AMACv2Reg::HV2LoThCh0;
-  HV2HiThCh1.initReg(m_cfg, RW, 0x3FF, 10, 10, 142, "HV2LoThCh1"); regMap["HV2LoThCh1"] = &AMACv2Reg::HV2LoThCh1;
-  HV2HiThCh2.initReg(m_cfg, RW, 0x3FF, 10, 20, 142, "HV2LoThCh2"); regMap["HV2LoThCh2"] = &AMACv2Reg::HV2LoThCh2;
+  HV2HiThCh0.initReg(m_cfg, RW, 0x3FF, 10, 0, 142, "HV2LoThCh0"); m_fieldMap["HV2LoThCh0"] = &AMACv2Reg::HV2LoThCh0;
+  HV2HiThCh1.initReg(m_cfg, RW, 0x3FF, 10, 10, 142, "HV2LoThCh1"); m_fieldMap["HV2LoThCh1"] = &AMACv2Reg::HV2LoThCh1;
+  HV2HiThCh2.initReg(m_cfg, RW, 0x3FF, 10, 20, 142, "HV2LoThCh2"); m_fieldMap["HV2LoThCh2"] = &AMACv2Reg::HV2LoThCh2;
   // 143 - HV2HiTh1
-  HV2HiThCh3.initReg(m_cfg, RW, 0x3FF, 10, 0, 143, "HV2HiThCh3"); regMap["HV2HiThCh3"] = &AMACv2Reg::HV2HiThCh3;
-  HV2HiThCh4.initReg(m_cfg, RW, 0x3FF, 10, 10, 143, "HV2HiThCh4"); regMap["HV2HiThCh4"] = &AMACv2Reg::HV2HiThCh4;
-  HV2HiThCh5.initReg(m_cfg, RW, 0x3FF, 10, 20, 143, "HV2HiThCh5"); regMap["HV2HiThCh5"] = &AMACv2Reg::HV2HiThCh5;
+  HV2HiThCh3.initReg(m_cfg, RW, 0x3FF, 10, 0, 143, "HV2HiThCh3"); m_fieldMap["HV2HiThCh3"] = &AMACv2Reg::HV2HiThCh3;
+  HV2HiThCh4.initReg(m_cfg, RW, 0x3FF, 10, 10, 143, "HV2HiThCh4"); m_fieldMap["HV2HiThCh4"] = &AMACv2Reg::HV2HiThCh4;
+  HV2HiThCh5.initReg(m_cfg, RW, 0x3FF, 10, 20, 143, "HV2HiThCh5"); m_fieldMap["HV2HiThCh5"] = &AMACv2Reg::HV2HiThCh5;
   // 144 - HV2HiTh2
-  HV2HiThCh6.initReg(m_cfg, RW, 0x3FF, 10, 0, 144, "HV2HiThCh6"); regMap["HV2HiThCh6"] = &AMACv2Reg::HV2HiThCh6;
-  HV2HiThCh7.initReg(m_cfg, RW, 0x3FF, 10, 10, 144, "HV2HiThCh7"); regMap["HV2HiThCh7"] = &AMACv2Reg::HV2HiThCh7;
-  HV2HiThCh8.initReg(m_cfg, RW, 0x3FF, 10, 20, 144, "HV2HiThCh8"); regMap["HV2HiThCh8"] = &AMACv2Reg::HV2HiThCh8;
+  HV2HiThCh6.initReg(m_cfg, RW, 0x3FF, 10, 0, 144, "HV2HiThCh6"); m_fieldMap["HV2HiThCh6"] = &AMACv2Reg::HV2HiThCh6;
+  HV2HiThCh7.initReg(m_cfg, RW, 0x3FF, 10, 10, 144, "HV2HiThCh7"); m_fieldMap["HV2HiThCh7"] = &AMACv2Reg::HV2HiThCh7;
+  HV2HiThCh8.initReg(m_cfg, RW, 0x3FF, 10, 20, 144, "HV2HiThCh8"); m_fieldMap["HV2HiThCh8"] = &AMACv2Reg::HV2HiThCh8;
   // 145 - HV2HiTh3
-  HV2HiThCh9.initReg(m_cfg, RW, 0x3FF, 10, 0, 145, "HV2HiThCh9"); regMap["HV2HiThCh9"] = &AMACv2Reg::HV2HiThCh9;
-  HV2HiThCh10.initReg(m_cfg, RW, 0x3FF, 10, 10, 145, "HV2HiThCh10"); regMap["HV2HiThCh10"] = &AMACv2Reg::HV2HiThCh10;
-  HV2HiThCh11.initReg(m_cfg, RW, 0x3FF, 10, 20, 145, "HV2HiThCh11"); regMap["HV2HiThCh11"] = &AMACv2Reg::HV2HiThCh11;
+  HV2HiThCh9.initReg(m_cfg, RW, 0x3FF, 10, 0, 145, "HV2HiThCh9"); m_fieldMap["HV2HiThCh9"] = &AMACv2Reg::HV2HiThCh9;
+  HV2HiThCh10.initReg(m_cfg, RW, 0x3FF, 10, 10, 145, "HV2HiThCh10"); m_fieldMap["HV2HiThCh10"] = &AMACv2Reg::HV2HiThCh10;
+  HV2HiThCh11.initReg(m_cfg, RW, 0x3FF, 10, 20, 145, "HV2HiThCh11"); m_fieldMap["HV2HiThCh11"] = &AMACv2Reg::HV2HiThCh11;
   // 146 - HV2HiTh4
-  HV2HiThCh12.initReg(m_cfg, RW, 0x3FF, 10, 0, 146, "HV2HiThCh12"); regMap["HV2HiThCh12"] = &AMACv2Reg::HV2HiThCh12;
-  HV2HiThCh13.initReg(m_cfg, RW, 0x3FF, 10, 10, 146, "HV2HiThCh13"); regMap["HV2HiThCh13"] = &AMACv2Reg::HV2HiThCh13;
-  HV2HiThCh14.initReg(m_cfg, RW, 0x3FF, 10, 20, 146, "HV2HiThCh14"); regMap["HV2HiThCh14"] = &AMACv2Reg::HV2HiThCh14;
+  HV2HiThCh12.initReg(m_cfg, RW, 0x3FF, 10, 0, 146, "HV2HiThCh12"); m_fieldMap["HV2HiThCh12"] = &AMACv2Reg::HV2HiThCh12;
+  HV2HiThCh13.initReg(m_cfg, RW, 0x3FF, 10, 10, 146, "HV2HiThCh13"); m_fieldMap["HV2HiThCh13"] = &AMACv2Reg::HV2HiThCh13;
+  HV2HiThCh14.initReg(m_cfg, RW, 0x3FF, 10, 20, 146, "HV2HiThCh14"); m_fieldMap["HV2HiThCh14"] = &AMACv2Reg::HV2HiThCh14;
   // 147 - HV2HiTh5
-  HV2HiThCh15.initReg(m_cfg, RW, 0x3FF, 10, 0, 147, "HV2HiThCh15"); regMap["HV2HiThCh15"] = &AMACv2Reg::HV2HiThCh15;
+  HV2HiThCh15.initReg(m_cfg, RW, 0x3FF, 10, 0, 147, "HV2HiThCh15"); m_fieldMap["HV2HiThCh15"] = &AMACv2Reg::HV2HiThCh15;
   // 148 - DCDCLoTh0
-  DCDCLoThCh0.initReg(m_cfg, RW, 0, 10, 0, 148, "DCDCLoThCh0"); regMap["DCDCLoThCh0"] = &AMACv2Reg::DCDCLoThCh0;
-  DCDCLoThCh1.initReg(m_cfg, RW, 0, 10, 10, 148, "DCDCLoThCh1"); regMap["DCDCLoThCh1"] = &AMACv2Reg::DCDCLoThCh1;
-  DCDCLoThCh2.initReg(m_cfg, RW, 0, 10, 20, 148, "DCDCLoThCh2"); regMap["DCDCLoThCh2"] = &AMACv2Reg::DCDCLoThCh2;
+  DCDCLoThCh0.initReg(m_cfg, RW, 0, 10, 0, 148, "DCDCLoThCh0"); m_fieldMap["DCDCLoThCh0"] = &AMACv2Reg::DCDCLoThCh0;
+  DCDCLoThCh1.initReg(m_cfg, RW, 0, 10, 10, 148, "DCDCLoThCh1"); m_fieldMap["DCDCLoThCh1"] = &AMACv2Reg::DCDCLoThCh1;
+  DCDCLoThCh2.initReg(m_cfg, RW, 0, 10, 20, 148, "DCDCLoThCh2"); m_fieldMap["DCDCLoThCh2"] = &AMACv2Reg::DCDCLoThCh2;
   // 149 - DCDCLoTh1
-  DCDCLoThCh3.initReg(m_cfg, RW, 0, 10, 0, 149, "DCDCLoThCh3"); regMap["DCDCLoThCh3"] = &AMACv2Reg::DCDCLoThCh3;
-  DCDCLoThCh4.initReg(m_cfg, RW, 0, 10, 10, 149, "DCDCLoThCh4"); regMap["DCDCLoThCh4"] = &AMACv2Reg::DCDCLoThCh4;
-  DCDCLoThCh5.initReg(m_cfg, RW, 0, 10, 20, 149, "DCDCLoThCh5"); regMap["DCDCLoThCh5"] = &AMACv2Reg::DCDCLoThCh5;
+  DCDCLoThCh3.initReg(m_cfg, RW, 0, 10, 0, 149, "DCDCLoThCh3"); m_fieldMap["DCDCLoThCh3"] = &AMACv2Reg::DCDCLoThCh3;
+  DCDCLoThCh4.initReg(m_cfg, RW, 0, 10, 10, 149, "DCDCLoThCh4"); m_fieldMap["DCDCLoThCh4"] = &AMACv2Reg::DCDCLoThCh4;
+  DCDCLoThCh5.initReg(m_cfg, RW, 0, 10, 20, 149, "DCDCLoThCh5"); m_fieldMap["DCDCLoThCh5"] = &AMACv2Reg::DCDCLoThCh5;
   // 150 - DCDCLoTh2
-  DCDCLoThCh6.initReg(m_cfg, RW, 0, 10, 0, 150, "DCDCLoThCh6"); regMap["DCDCLoThCh6"] = &AMACv2Reg::DCDCLoThCh6;
-  DCDCLoThCh7.initReg(m_cfg, RW, 0, 10, 10, 150, "DCDCLoThCh7"); regMap["DCDCLoThCh7"] = &AMACv2Reg::DCDCLoThCh7;
-  DCDCLoThCh8.initReg(m_cfg, RW, 0, 10, 20, 150, "DCDCLoThCh8"); regMap["DCDCLoThCh8"] = &AMACv2Reg::DCDCLoThCh8;
+  DCDCLoThCh6.initReg(m_cfg, RW, 0, 10, 0, 150, "DCDCLoThCh6"); m_fieldMap["DCDCLoThCh6"] = &AMACv2Reg::DCDCLoThCh6;
+  DCDCLoThCh7.initReg(m_cfg, RW, 0, 10, 10, 150, "DCDCLoThCh7"); m_fieldMap["DCDCLoThCh7"] = &AMACv2Reg::DCDCLoThCh7;
+  DCDCLoThCh8.initReg(m_cfg, RW, 0, 10, 20, 150, "DCDCLoThCh8"); m_fieldMap["DCDCLoThCh8"] = &AMACv2Reg::DCDCLoThCh8;
   // 151 - DCDCLoTh3
-  DCDCLoThCh9.initReg(m_cfg, RW, 0, 10, 0, 151, "DCDCLoThCh9"); regMap["DCDCLoThCh9"] = &AMACv2Reg::DCDCLoThCh9;
-  DCDCLoThCh10.initReg(m_cfg, RW, 0, 10, 10, 151, "DCDCLoThCh10"); regMap["DCDCLoThCh10"] = &AMACv2Reg::DCDCLoThCh10;
-  DCDCLoThCh11.initReg(m_cfg, RW, 0, 10, 20, 151, "DCDCLoThCh11"); regMap["DCDCLoThCh11"] = &AMACv2Reg::DCDCLoThCh11;
+  DCDCLoThCh9.initReg(m_cfg, RW, 0, 10, 0, 151, "DCDCLoThCh9"); m_fieldMap["DCDCLoThCh9"] = &AMACv2Reg::DCDCLoThCh9;
+  DCDCLoThCh10.initReg(m_cfg, RW, 0, 10, 10, 151, "DCDCLoThCh10"); m_fieldMap["DCDCLoThCh10"] = &AMACv2Reg::DCDCLoThCh10;
+  DCDCLoThCh11.initReg(m_cfg, RW, 0, 10, 20, 151, "DCDCLoThCh11"); m_fieldMap["DCDCLoThCh11"] = &AMACv2Reg::DCDCLoThCh11;
   // 152 - DCDCLoTh4
-  DCDCLoThCh12.initReg(m_cfg, RW, 0, 10, 0, 152, "DCDCLoThCh12"); regMap["DCDCLoThCh12"] = &AMACv2Reg::DCDCLoThCh12;
-  DCDCLoThCh13.initReg(m_cfg, RW, 0, 10, 10, 152, "DCDCLoThCh13"); regMap["DCDCLoThCh13"] = &AMACv2Reg::DCDCLoThCh13;
-  DCDCLoThCh14.initReg(m_cfg, RW, 0, 10, 20, 152, "DCDCLoThCh14"); regMap["DCDCLoThCh14"] = &AMACv2Reg::DCDCLoThCh14;
+  DCDCLoThCh12.initReg(m_cfg, RW, 0, 10, 0, 152, "DCDCLoThCh12"); m_fieldMap["DCDCLoThCh12"] = &AMACv2Reg::DCDCLoThCh12;
+  DCDCLoThCh13.initReg(m_cfg, RW, 0, 10, 10, 152, "DCDCLoThCh13"); m_fieldMap["DCDCLoThCh13"] = &AMACv2Reg::DCDCLoThCh13;
+  DCDCLoThCh14.initReg(m_cfg, RW, 0, 10, 20, 152, "DCDCLoThCh14"); m_fieldMap["DCDCLoThCh14"] = &AMACv2Reg::DCDCLoThCh14;
   // 153 - DCDCLoTh5
-  DCDCLoThCh15.initReg(m_cfg, RW, 0, 10, 0, 153, "DCDCLoThCh15"); regMap["DCDCLoThCh15"] = &AMACv2Reg::DCDCLoThCh15;
+  DCDCLoThCh15.initReg(m_cfg, RW, 0, 10, 0, 153, "DCDCLoThCh15"); m_fieldMap["DCDCLoThCh15"] = &AMACv2Reg::DCDCLoThCh15;
   // 154 - DCDCHiTh0
-  DCDCHiThCh0.initReg(m_cfg, RW, 0x3FF, 10, 0, 154, "DCDCLoThCh0"); regMap["DCDCLoThCh0"] = &AMACv2Reg::DCDCLoThCh0;
-  DCDCHiThCh1.initReg(m_cfg, RW, 0x3FF, 10, 10, 154, "DCDCLoThCh1"); regMap["DCDCLoThCh1"] = &AMACv2Reg::DCDCLoThCh1;
-  DCDCHiThCh2.initReg(m_cfg, RW, 0x3FF, 10, 20, 154, "DCDCLoThCh2"); regMap["DCDCLoThCh2"] = &AMACv2Reg::DCDCLoThCh2;
+  DCDCHiThCh0.initReg(m_cfg, RW, 0x3FF, 10, 0, 154, "DCDCLoThCh0"); m_fieldMap["DCDCLoThCh0"] = &AMACv2Reg::DCDCLoThCh0;
+  DCDCHiThCh1.initReg(m_cfg, RW, 0x3FF, 10, 10, 154, "DCDCLoThCh1"); m_fieldMap["DCDCLoThCh1"] = &AMACv2Reg::DCDCLoThCh1;
+  DCDCHiThCh2.initReg(m_cfg, RW, 0x3FF, 10, 20, 154, "DCDCLoThCh2"); m_fieldMap["DCDCLoThCh2"] = &AMACv2Reg::DCDCLoThCh2;
   // 155 - DCDCHiTh1
-  DCDCHiThCh3.initReg(m_cfg, RW, 0x3FF, 10, 0, 155, "DCDCHiThCh3"); regMap["DCDCHiThCh3"] = &AMACv2Reg::DCDCHiThCh3;
-  DCDCHiThCh4.initReg(m_cfg, RW, 0x3FF, 10, 10, 155, "DCDCHiThCh4"); regMap["DCDCHiThCh4"] = &AMACv2Reg::DCDCHiThCh4;
-  DCDCHiThCh5.initReg(m_cfg, RW, 0x3FF, 10, 20, 155, "DCDCHiThCh5"); regMap["DCDCHiThCh5"] = &AMACv2Reg::DCDCHiThCh5;
+  DCDCHiThCh3.initReg(m_cfg, RW, 0x3FF, 10, 0, 155, "DCDCHiThCh3"); m_fieldMap["DCDCHiThCh3"] = &AMACv2Reg::DCDCHiThCh3;
+  DCDCHiThCh4.initReg(m_cfg, RW, 0x3FF, 10, 10, 155, "DCDCHiThCh4"); m_fieldMap["DCDCHiThCh4"] = &AMACv2Reg::DCDCHiThCh4;
+  DCDCHiThCh5.initReg(m_cfg, RW, 0x3FF, 10, 20, 155, "DCDCHiThCh5"); m_fieldMap["DCDCHiThCh5"] = &AMACv2Reg::DCDCHiThCh5;
   // 156 - DCDCHiTh2
-  DCDCHiThCh6.initReg(m_cfg, RW, 0x3FF, 10, 0, 156, "DCDCHiThCh6"); regMap["DCDCHiThCh6"] = &AMACv2Reg::DCDCHiThCh6;
-  DCDCHiThCh7.initReg(m_cfg, RW, 0x3FF, 10, 10, 156, "DCDCHiThCh7"); regMap["DCDCHiThCh7"] = &AMACv2Reg::DCDCHiThCh7;
-  DCDCHiThCh8.initReg(m_cfg, RW, 0x3FF, 10, 20, 156, "DCDCHiThCh8"); regMap["DCDCHiThCh8"] = &AMACv2Reg::DCDCHiThCh8;
+  DCDCHiThCh6.initReg(m_cfg, RW, 0x3FF, 10, 0, 156, "DCDCHiThCh6"); m_fieldMap["DCDCHiThCh6"] = &AMACv2Reg::DCDCHiThCh6;
+  DCDCHiThCh7.initReg(m_cfg, RW, 0x3FF, 10, 10, 156, "DCDCHiThCh7"); m_fieldMap["DCDCHiThCh7"] = &AMACv2Reg::DCDCHiThCh7;
+  DCDCHiThCh8.initReg(m_cfg, RW, 0x3FF, 10, 20, 156, "DCDCHiThCh8"); m_fieldMap["DCDCHiThCh8"] = &AMACv2Reg::DCDCHiThCh8;
   // 157 - DCDCHiTh3
-  DCDCHiThCh9.initReg(m_cfg, RW, 0x3FF, 10, 0, 157, "DCDCHiThCh9"); regMap["DCDCHiThCh9"] = &AMACv2Reg::DCDCHiThCh9;
-  DCDCHiThCh10.initReg(m_cfg, RW, 0x3FF, 10, 10, 157, "DCDCHiThCh10"); regMap["DCDCHiThCh10"] = &AMACv2Reg::DCDCHiThCh10;
-  DCDCHiThCh11.initReg(m_cfg, RW, 0x3FF, 10, 20, 157, "DCDCHiThCh11"); regMap["DCDCHiThCh11"] = &AMACv2Reg::DCDCHiThCh11;
+  DCDCHiThCh9.initReg(m_cfg, RW, 0x3FF, 10, 0, 157, "DCDCHiThCh9"); m_fieldMap["DCDCHiThCh9"] = &AMACv2Reg::DCDCHiThCh9;
+  DCDCHiThCh10.initReg(m_cfg, RW, 0x3FF, 10, 10, 157, "DCDCHiThCh10"); m_fieldMap["DCDCHiThCh10"] = &AMACv2Reg::DCDCHiThCh10;
+  DCDCHiThCh11.initReg(m_cfg, RW, 0x3FF, 10, 20, 157, "DCDCHiThCh11"); m_fieldMap["DCDCHiThCh11"] = &AMACv2Reg::DCDCHiThCh11;
   // 158 - DCDCHiTh4
-  DCDCHiThCh12.initReg(m_cfg, RW, 0x3FF, 10, 0, 158, "DCDCHiThCh12"); regMap["DCDCHiThCh12"] = &AMACv2Reg::DCDCHiThCh12;
-  DCDCHiThCh13.initReg(m_cfg, RW, 0x3FF, 10, 10, 158, "DCDCHiThCh13"); regMap["DCDCHiThCh13"] = &AMACv2Reg::DCDCHiThCh13;
-  DCDCHiThCh14.initReg(m_cfg, RW, 0x3FF, 10, 20, 158, "DCDCHiThCh14"); regMap["DCDCHiThCh14"] = &AMACv2Reg::DCDCHiThCh14;
+  DCDCHiThCh12.initReg(m_cfg, RW, 0x3FF, 10, 0, 158, "DCDCHiThCh12"); m_fieldMap["DCDCHiThCh12"] = &AMACv2Reg::DCDCHiThCh12;
+  DCDCHiThCh13.initReg(m_cfg, RW, 0x3FF, 10, 10, 158, "DCDCHiThCh13"); m_fieldMap["DCDCHiThCh13"] = &AMACv2Reg::DCDCHiThCh13;
+  DCDCHiThCh14.initReg(m_cfg, RW, 0x3FF, 10, 20, 158, "DCDCHiThCh14"); m_fieldMap["DCDCHiThCh14"] = &AMACv2Reg::DCDCHiThCh14;
   // 159 - DCDCHiTh5
-  DCDCHiThCh15.initReg(m_cfg, RW, 0x3FF, 10, 0, 159, "DCDCHiThCh15"); regMap["DCDCHiThCh15"] = &AMACv2Reg::DCDCHiThCh15;
+  DCDCHiThCh15.initReg(m_cfg, RW, 0x3FF, 10, 0, 159, "DCDCHiThCh15"); m_fieldMap["DCDCHiThCh15"] = &AMACv2Reg::DCDCHiThCh15;
   // 160 - WRNLoTh0
-  WRNLoThCh0.initReg(m_cfg, RW, 0, 10, 0, 160, "WRNLoThCh0"); regMap["WRNLoThCh0"] = &AMACv2Reg::WRNLoThCh0;
-  WRNLoThCh1.initReg(m_cfg, RW, 0, 10, 10, 160, "WRNLoThCh1"); regMap["WRNLoThCh1"] = &AMACv2Reg::WRNLoThCh1;
-  WRNLoThCh2.initReg(m_cfg, RW, 0, 10, 20, 160, "WRNLoThCh2"); regMap["WRNLoThCh2"] = &AMACv2Reg::WRNLoThCh2;
+  WRNLoThCh0.initReg(m_cfg, RW, 0, 10, 0, 160, "WRNLoThCh0"); m_fieldMap["WRNLoThCh0"] = &AMACv2Reg::WRNLoThCh0;
+  WRNLoThCh1.initReg(m_cfg, RW, 0, 10, 10, 160, "WRNLoThCh1"); m_fieldMap["WRNLoThCh1"] = &AMACv2Reg::WRNLoThCh1;
+  WRNLoThCh2.initReg(m_cfg, RW, 0, 10, 20, 160, "WRNLoThCh2"); m_fieldMap["WRNLoThCh2"] = &AMACv2Reg::WRNLoThCh2;
   // 161 - WRNLoTh1
-  WRNLoThCh3.initReg(m_cfg, RW, 0, 10, 0, 161, "WRNLoThCh3"); regMap["WRNLoThCh3"] = &AMACv2Reg::WRNLoThCh3;
-  WRNLoThCh4.initReg(m_cfg, RW, 0, 10, 10, 161, "WRNLoThCh4"); regMap["WRNLoThCh4"] = &AMACv2Reg::WRNLoThCh4;
-  WRNLoThCh5.initReg(m_cfg, RW, 0, 10, 20, 161, "WRNLoThCh5"); regMap["WRNLoThCh5"] = &AMACv2Reg::WRNLoThCh5;
+  WRNLoThCh3.initReg(m_cfg, RW, 0, 10, 0, 161, "WRNLoThCh3"); m_fieldMap["WRNLoThCh3"] = &AMACv2Reg::WRNLoThCh3;
+  WRNLoThCh4.initReg(m_cfg, RW, 0, 10, 10, 161, "WRNLoThCh4"); m_fieldMap["WRNLoThCh4"] = &AMACv2Reg::WRNLoThCh4;
+  WRNLoThCh5.initReg(m_cfg, RW, 0, 10, 20, 161, "WRNLoThCh5"); m_fieldMap["WRNLoThCh5"] = &AMACv2Reg::WRNLoThCh5;
   // 162 - WRNLoTh2
-  WRNLoThCh6.initReg(m_cfg, RW, 0, 10, 0, 162, "WRNLoThCh6"); regMap["WRNLoThCh6"] = &AMACv2Reg::WRNLoThCh6;
-  WRNLoThCh7.initReg(m_cfg, RW, 0, 10, 10, 162, "WRNLoThCh7"); regMap["WRNLoThCh7"] = &AMACv2Reg::WRNLoThCh7;
-  WRNLoThCh8.initReg(m_cfg, RW, 0, 10, 20, 162, "WRNLoThCh8"); regMap["WRNLoThCh8"] = &AMACv2Reg::WRNLoThCh8;
+  WRNLoThCh6.initReg(m_cfg, RW, 0, 10, 0, 162, "WRNLoThCh6"); m_fieldMap["WRNLoThCh6"] = &AMACv2Reg::WRNLoThCh6;
+  WRNLoThCh7.initReg(m_cfg, RW, 0, 10, 10, 162, "WRNLoThCh7"); m_fieldMap["WRNLoThCh7"] = &AMACv2Reg::WRNLoThCh7;
+  WRNLoThCh8.initReg(m_cfg, RW, 0, 10, 20, 162, "WRNLoThCh8"); m_fieldMap["WRNLoThCh8"] = &AMACv2Reg::WRNLoThCh8;
   // 163 - WRNLoTh3
-  WRNLoThCh9.initReg(m_cfg, RW, 0, 10, 0, 163, "WRNLoThCh9"); regMap["WRNLoThCh9"] = &AMACv2Reg::WRNLoThCh9;
-  WRNLoThCh10.initReg(m_cfg, RW, 0, 10, 10, 163, "WRNLoThCh10"); regMap["WRNLoThCh10"] = &AMACv2Reg::WRNLoThCh10;
-  WRNLoThCh11.initReg(m_cfg, RW, 0, 10, 20, 163, "WRNLoThCh11"); regMap["WRNLoThCh11"] = &AMACv2Reg::WRNLoThCh11;
+  WRNLoThCh9.initReg(m_cfg, RW, 0, 10, 0, 163, "WRNLoThCh9"); m_fieldMap["WRNLoThCh9"] = &AMACv2Reg::WRNLoThCh9;
+  WRNLoThCh10.initReg(m_cfg, RW, 0, 10, 10, 163, "WRNLoThCh10"); m_fieldMap["WRNLoThCh10"] = &AMACv2Reg::WRNLoThCh10;
+  WRNLoThCh11.initReg(m_cfg, RW, 0, 10, 20, 163, "WRNLoThCh11"); m_fieldMap["WRNLoThCh11"] = &AMACv2Reg::WRNLoThCh11;
   // 164 - WRNLoTh4
-  WRNLoThCh12.initReg(m_cfg, RW, 0, 10, 0, 164, "WRNLoThCh12"); regMap["WRNLoThCh12"] = &AMACv2Reg::WRNLoThCh12;
-  WRNLoThCh13.initReg(m_cfg, RW, 0, 10, 10, 164, "WRNLoThCh13"); regMap["WRNLoThCh13"] = &AMACv2Reg::WRNLoThCh13;
-  WRNLoThCh14.initReg(m_cfg, RW, 0, 10, 20, 164, "WRNLoThCh14"); regMap["WRNLoThCh14"] = &AMACv2Reg::WRNLoThCh14;
+  WRNLoThCh12.initReg(m_cfg, RW, 0, 10, 0, 164, "WRNLoThCh12"); m_fieldMap["WRNLoThCh12"] = &AMACv2Reg::WRNLoThCh12;
+  WRNLoThCh13.initReg(m_cfg, RW, 0, 10, 10, 164, "WRNLoThCh13"); m_fieldMap["WRNLoThCh13"] = &AMACv2Reg::WRNLoThCh13;
+  WRNLoThCh14.initReg(m_cfg, RW, 0, 10, 20, 164, "WRNLoThCh14"); m_fieldMap["WRNLoThCh14"] = &AMACv2Reg::WRNLoThCh14;
   // 165 - WRNLoTh5
-  WRNLoThCh15.initReg(m_cfg, RW, 0, 10, 0, 165, "WRNLoThCh15"); regMap["WRNLoThCh15"] = &AMACv2Reg::WRNLoThCh15;
+  WRNLoThCh15.initReg(m_cfg, RW, 0, 10, 0, 165, "WRNLoThCh15"); m_fieldMap["WRNLoThCh15"] = &AMACv2Reg::WRNLoThCh15;
   // 166 - WRNHiTh0
-  WRNHiThCh0.initReg(m_cfg, RW, 0x3FF, 10, 0, 166, "WRNLoThCh0"); regMap["WRNLoThCh0"] = &AMACv2Reg::WRNLoThCh0;
-  WRNHiThCh1.initReg(m_cfg, RW, 0x3FF, 10, 10, 166, "WRNLoThCh1"); regMap["WRNLoThCh1"] = &AMACv2Reg::WRNLoThCh1;
-  WRNHiThCh2.initReg(m_cfg, RW, 0x3FF, 10, 20, 166, "WRNLoThCh2"); regMap["WRNLoThCh2"] = &AMACv2Reg::WRNLoThCh2;
+  WRNHiThCh0.initReg(m_cfg, RW, 0x3FF, 10, 0, 166, "WRNLoThCh0"); m_fieldMap["WRNLoThCh0"] = &AMACv2Reg::WRNLoThCh0;
+  WRNHiThCh1.initReg(m_cfg, RW, 0x3FF, 10, 10, 166, "WRNLoThCh1"); m_fieldMap["WRNLoThCh1"] = &AMACv2Reg::WRNLoThCh1;
+  WRNHiThCh2.initReg(m_cfg, RW, 0x3FF, 10, 20, 166, "WRNLoThCh2"); m_fieldMap["WRNLoThCh2"] = &AMACv2Reg::WRNLoThCh2;
   // 167 - WRNHiTh1
-  WRNHiThCh3.initReg(m_cfg, RW, 0x3FF, 10, 0, 167, "WRNHiThCh3"); regMap["WRNHiThCh3"] = &AMACv2Reg::WRNHiThCh3;
-  WRNHiThCh4.initReg(m_cfg, RW, 0x3FF, 10, 10, 167, "WRNHiThCh4"); regMap["WRNHiThCh4"] = &AMACv2Reg::WRNHiThCh4;
-  WRNHiThCh5.initReg(m_cfg, RW, 0x3FF, 10, 20, 167, "WRNHiThCh5"); regMap["WRNHiThCh5"] = &AMACv2Reg::WRNHiThCh5;
+  WRNHiThCh3.initReg(m_cfg, RW, 0x3FF, 10, 0, 167, "WRNHiThCh3"); m_fieldMap["WRNHiThCh3"] = &AMACv2Reg::WRNHiThCh3;
+  WRNHiThCh4.initReg(m_cfg, RW, 0x3FF, 10, 10, 167, "WRNHiThCh4"); m_fieldMap["WRNHiThCh4"] = &AMACv2Reg::WRNHiThCh4;
+  WRNHiThCh5.initReg(m_cfg, RW, 0x3FF, 10, 20, 167, "WRNHiThCh5"); m_fieldMap["WRNHiThCh5"] = &AMACv2Reg::WRNHiThCh5;
   // 168 - WRNHiTh2
-  WRNHiThCh6.initReg(m_cfg, RW, 0x3FF, 10, 0, 168, "WRNHiThCh6"); regMap["WRNHiThCh6"] = &AMACv2Reg::WRNHiThCh6;
-  WRNHiThCh7.initReg(m_cfg, RW, 0x3FF, 10, 10, 168, "WRNHiThCh7"); regMap["WRNHiThCh7"] = &AMACv2Reg::WRNHiThCh7;
-  WRNHiThCh8.initReg(m_cfg, RW, 0x3FF, 10, 20, 168, "WRNHiThCh8"); regMap["WRNHiThCh8"] = &AMACv2Reg::WRNHiThCh8;
+  WRNHiThCh6.initReg(m_cfg, RW, 0x3FF, 10, 0, 168, "WRNHiThCh6"); m_fieldMap["WRNHiThCh6"] = &AMACv2Reg::WRNHiThCh6;
+  WRNHiThCh7.initReg(m_cfg, RW, 0x3FF, 10, 10, 168, "WRNHiThCh7"); m_fieldMap["WRNHiThCh7"] = &AMACv2Reg::WRNHiThCh7;
+  WRNHiThCh8.initReg(m_cfg, RW, 0x3FF, 10, 20, 168, "WRNHiThCh8"); m_fieldMap["WRNHiThCh8"] = &AMACv2Reg::WRNHiThCh8;
   // 169 - WRNHiTh3
-  WRNHiThCh9.initReg(m_cfg, RW, 0x3FF, 10, 0, 169, "WRNHiThCh9"); regMap["WRNHiThCh9"] = &AMACv2Reg::WRNHiThCh9;
-  WRNHiThCh10.initReg(m_cfg, RW, 0x3FF, 10, 10, 169, "WRNHiThCh10"); regMap["WRNHiThCh10"] = &AMACv2Reg::WRNHiThCh10;
-  WRNHiThCh11.initReg(m_cfg, RW, 0x3FF, 10, 20, 169, "WRNHiThCh11"); regMap["WRNHiThCh11"] = &AMACv2Reg::WRNHiThCh11;
+  WRNHiThCh9.initReg(m_cfg, RW, 0x3FF, 10, 0, 169, "WRNHiThCh9"); m_fieldMap["WRNHiThCh9"] = &AMACv2Reg::WRNHiThCh9;
+  WRNHiThCh10.initReg(m_cfg, RW, 0x3FF, 10, 10, 169, "WRNHiThCh10"); m_fieldMap["WRNHiThCh10"] = &AMACv2Reg::WRNHiThCh10;
+  WRNHiThCh11.initReg(m_cfg, RW, 0x3FF, 10, 20, 169, "WRNHiThCh11"); m_fieldMap["WRNHiThCh11"] = &AMACv2Reg::WRNHiThCh11;
   // 170 - WRNHiTh4
-  WRNHiThCh12.initReg(m_cfg, RW, 0x3FF, 10, 0, 170, "WRNHiThCh12"); regMap["WRNHiThCh12"] = &AMACv2Reg::WRNHiThCh12;
-  WRNHiThCh13.initReg(m_cfg, RW, 0x3FF, 10, 10, 170, "WRNHiThCh13"); regMap["WRNHiThCh13"] = &AMACv2Reg::WRNHiThCh13;
-  WRNHiThCh14.initReg(m_cfg, RW, 0x3FF, 10, 20, 170, "WRNHiThCh14"); regMap["WRNHiThCh14"] = &AMACv2Reg::WRNHiThCh14;
+  WRNHiThCh12.initReg(m_cfg, RW, 0x3FF, 10, 0, 170, "WRNHiThCh12"); m_fieldMap["WRNHiThCh12"] = &AMACv2Reg::WRNHiThCh12;
+  WRNHiThCh13.initReg(m_cfg, RW, 0x3FF, 10, 10, 170, "WRNHiThCh13"); m_fieldMap["WRNHiThCh13"] = &AMACv2Reg::WRNHiThCh13;
+  WRNHiThCh14.initReg(m_cfg, RW, 0x3FF, 10, 20, 170, "WRNHiThCh14"); m_fieldMap["WRNHiThCh14"] = &AMACv2Reg::WRNHiThCh14;
   // 171 - WRNHiTh5
-  WRNHiThCh15.initReg(m_cfg, RW, 0x3FF, 10, 0, 171, "WRNHiThCh15"); regMap["WRNHiThCh15"] = &AMACv2Reg::WRNHiThCh15;
+  WRNHiThCh15.initReg(m_cfg, RW, 0x3FF, 10, 0, 171, "WRNHiThCh15"); m_fieldMap["WRNHiThCh15"] = &AMACv2Reg::WRNHiThCh15;
 }
 
 std::vector<const AMACv2Field*> AMACv2Reg::getFields() const
 {
   std::vector<const AMACv2Field*> fields;
-  fields.reserve(regMap.size());
-  for(const auto kv : regMap) fields.push_back(&(this->*kv.second));
+  fields.reserve(m_fieldMap.size());
+  for(const auto kv : m_fieldMap) fields.push_back(&(this->*kv.second));
   return fields;
 }
 
@@ -688,8 +838,8 @@ AMACv2Field* AMACv2Reg::findField(AMACv2Field AMACv2Reg::* ref)
 
 AMACv2Field* AMACv2Reg::findField(const std::string& fieldName)
 {
-  if(regMap.find(fieldName) != regMap.end())
-    return &(this->*regMap[fieldName]);
+  if(m_fieldMap.find(fieldName) != m_fieldMap.end())
+    return &(this->*m_fieldMap[fieldName]);
 
   return nullptr;
 }
@@ -701,8 +851,8 @@ uint32_t AMACv2Reg::getField(AMACv2Field AMACv2Reg::* ref)
 
 uint32_t AMACv2Reg::getField(const std::string& fieldName)
 {
-  if(regMap.find(fieldName) != regMap.end())
-    return(this->*regMap[fieldName]).read();
+  if(m_fieldMap.find(fieldName) != m_fieldMap.end())
+    return(this->*m_fieldMap[fieldName]).read();
   else
     std::cerr << " --> Error: Could not find register \""<< fieldName << "\"" << std::endl;
   return 0;
@@ -723,8 +873,8 @@ uint32_t AMACv2Reg::getReg(AMACv2Field AMACv2Reg::* ref)
 
 uint32_t AMACv2Reg::getReg(const std::string& fieldName)
 {
-  if(regMap.find(fieldName) != regMap.end())
-    return(this->*regMap[fieldName]).readRaw();
+  if(m_fieldMap.find(fieldName) != m_fieldMap.end())
+    return(this->*m_fieldMap[fieldName]).readRaw();
   else
     std::cerr << " --> Error: Could not find register \""<< fieldName << "\"" << std::endl;
   return 0;
@@ -737,8 +887,8 @@ void AMACv2Reg::setField(AMACv2Field AMACv2Reg::* ref, uint32_t value)
 
 void AMACv2Reg::setField(const std::string& fieldName, uint32_t value)
 {
-  if(regMap.find(fieldName) != regMap.end())
-    return(this->*regMap[fieldName]).write(value);
+  if(m_fieldMap.find(fieldName) != m_fieldMap.end())
+    return(this->*m_fieldMap[fieldName]).write(value);
   else
     std::cerr << " --> Error: Could not find register \""<< fieldName << "\"" << std::endl;
   return;
@@ -761,8 +911,8 @@ uint8_t AMACv2Reg::getAddr(AMACv2Field AMACv2Reg::* ref)
 
 uint8_t AMACv2Reg::getAddr(const std::string& fieldName)
 {
-  if(regMap.find(fieldName) != regMap.end())
-    return (this->*regMap[fieldName]).addr();
+  if(m_fieldMap.find(fieldName) != m_fieldMap.end())
+    return (this->*m_fieldMap[fieldName]).addr();
   else
     std::cerr << " --> Error: Could not find register \""<< fieldName << "\"" << std::endl;
   return 0;
diff --git a/pbv3/AMACv2Reg.h b/pbv3/AMACv2Reg.h
index 7805c8ea..87e4e7bb 100644
--- a/pbv3/AMACv2Reg.h
+++ b/pbv3/AMACv2Reg.h
@@ -59,7 +59,10 @@ private:
   void init();
 
 public:
-  static const unsigned numRegs = 171;
+  //! Map of register address to RW status
+  static const std::unordered_map<uint32_t, rw_t> Registers;
+
+
   uint32_t m_cfg[numRegs];
 
   AMACv2Reg();
@@ -659,6 +662,6 @@ public:
   AMACv2Field WRNHiThCh15;
 
 protected:
-  std::unordered_map<std::string, AMACv2Field AMACv2Reg::*> regMap;
+  std::unordered_map<std::string, AMACv2Field AMACv2Reg::*> m_fieldMap;
 };
 #endif //AMACREG_H
-- 
GitLab


From d6f9a2f602c8809d2597c8130d023f976952c75e Mon Sep 17 00:00:00 2001
From: Karol Krizka <kkrizka@gmail.com>
Date: Mon, 24 Aug 2020 16:21:37 -0700
Subject: [PATCH 16/29] Add checkSEU test.

---
 pbv3/PBv3TestTools.cpp     |  50 ++++++++++
 pbv3/PBv3TestTools.h       |  24 +++++
 pbv3/tools/pbv3_betsee.cpp | 198 +++++++++++++++++++++++++++++++++++++
 3 files changed, 272 insertions(+)
 create mode 100644 pbv3/tools/pbv3_betsee.cpp

diff --git a/pbv3/PBv3TestTools.cpp b/pbv3/PBv3TestTools.cpp
index f7f02727..374420d5 100644
--- a/pbv3/PBv3TestTools.cpp
+++ b/pbv3/PBv3TestTools.cpp
@@ -8,6 +8,7 @@
 #endif
 
 #include <memory>
+#include <sstream>
 
 namespace PBv3TestTools 
 {
@@ -1339,4 +1340,53 @@ namespace PBv3TestTools
     return testSum;
   }
 
+  json checkSEUs(std::shared_ptr<AMACv2> amac)
+  {
+    logger(logINFO) << "## Check for SEU's ##";
+    json testSum;
+    testSum["testType"] = "SEUCHECK";
+    testSum["results"]["TIMESTART"] = PBv3Utils::getTimeAsString(std::chrono::system_clock::now());
+    testSum["passed"] = true;
+
+    uint32_t nSEU=0;
+    for(const std::pair<uint32_t, rw_t>& reg : AMACv2Reg::Registers)
+      {
+	if(reg.second!=RW)
+	  continue;
+
+	uint32_t expval=amac->getReg(reg.first);
+	uint32_t curval=amac->read_reg(reg.first);
+
+	testSum["results"]["reg"+std::to_string(reg.first)+"value"]=curval;
+	testSum["results"]["reg"+std::to_string(reg.first)+"expec"]=expval;
+
+	if(expval!=curval)
+	  { // There was an SEU
+	    ++nSEU;
+
+	    std::stringstream ss;
+	    ss << "SEU in register " << reg.first << ": ";
+	    ss << "0x" << std::hex << std::setw(8) << std::setfill('0') << curval << std::dec;
+	    ss << " (expected 0x" << std::hex << std::setw(8) << std::setfill('0') << expval << std::dec << ")";
+	    logger(logINFO) << ss.str();
+
+	    // Correct
+	    amac->write_reg(reg.first, expval);
+	    uint32_t curval2=amac->read_reg(reg.first);
+	    if(curval2==expval)
+	      {
+		std::stringstream ss;
+		ss << "Found an unrecoverable SEU in register " << reg.first << ": ";
+		ss << "0x" << std::hex << std::setw(8) << std::setfill('0') << curval << std::dec;
+		ss << " (expected 0x" << std::hex << std::setw(8) << std::setfill('0') << expval << std::dec << ")";
+		throw std::runtime_error(ss.str());
+	      }
+	  }
+      }
+    testSum["passed"] = (nSEU==0);
+
+    testSum["results"]["TIMEEND"] = PBv3Utils::getTimeAsString(std::chrono::system_clock::now());
+
+    return testSum;
+  }
 }
diff --git a/pbv3/PBv3TestTools.h b/pbv3/PBv3TestTools.h
index 37fbe1e0..57dd715b 100644
--- a/pbv3/PBv3TestTools.h
+++ b/pbv3/PBv3TestTools.h
@@ -454,6 +454,30 @@ namespace PBv3TestTools
    * \return JSON object with test results
    */
   json temperature(std::shared_ptr<AMACv2> amac, bool scanSettings=true);
+
+  //
+  // Run Tests
+
+  /*
+   * \brief Read out all registers, check for SEU's and correct them.
+   *
+   * An SEU is defined as a register value being different from what 
+   * is currently loaded in the AMACv2 object.
+   *
+   * The recovery procedure is to write the correct value and then read
+   * the register again to make sure that it is good now. If not, an
+   * exception is raised.
+   *
+   * Pass: If no SEU's are detected
+   *
+   * Modifies the following registers
+   *  - All registers
+   *
+   * \param amac AMAC communication object
+   *
+   * \return JSON object with test results
+   */
+  json checkSEUs(std::shared_ptr<AMACv2> amac);
 }
 
 #endif
diff --git a/pbv3/tools/pbv3_betsee.cpp b/pbv3/tools/pbv3_betsee.cpp
new file mode 100644
index 00000000..03ecb494
--- /dev/null
+++ b/pbv3/tools/pbv3_betsee.cpp
@@ -0,0 +1,198 @@
+#include <unistd.h>
+#include <string.h>
+#include <getopt.h>
+
+#include <chrono>
+#include <fstream>
+#include <iomanip>
+#include <iostream>
+#include <thread>
+
+#include <nlohmann/json.hpp>
+
+#include "Logger.h"
+
+#include "AMACv2.h"
+
+#include "PBv3TBConf.h"
+#include "PBv3TBSingle.h"
+#include "PBv3TestTools.h"
+#include "PBv3ConfigTools.h"
+#include "PBv3Utils.h"
+
+//------ SETTINGS
+std::string configfile0 = "config0.json";
+std::string configfile1 = "config1.json";
+std::string equipConfigFile = "config/equip_testbench.json";
+//---------------
+
+#define PERIOD_LONG 60 // number of seconds of monitoring between calibrations
+#define PERIOD_MONITOR 1 // number of seconds to wait between readings
+void usage(char* argv[])
+{
+  std::cerr << "Usage: " << argv[0] << " [options] betsee0.json betsee1.json datadir" << std::endl;
+  std::cerr << std::endl;
+  std::cerr << "List of options:" << std::endl;
+  std::cerr << " -e, --equip config.json Equipment configuration file (default: " << equipConfigFile << ")" << std::endl;
+  std::cerr << " -d, --debug             Enable more verbose printout"  << std::endl;
+  std::cerr << std::endl;
+  std::cerr << std::endl;
+}
+
+int main(int argc, char* argv[])
+{
+  int c;
+  while (1)
+    {
+      int option_index = 0;
+      static struct option long_options[] =
+	{
+	  {"equip"    , required_argument, 0,  'e' },
+	  {"debug"    , no_argument      , 0,  'd' },
+	  {0          , 0                , 0,  0 }
+	};
+
+      c = getopt_long(argc, argv, "e:d", long_options, &option_index);
+      if (c == -1)
+	break;
+
+      switch (c)
+	{
+	case 'e':
+	  equipConfigFile = optarg;
+	  break;
+	case 'd':
+	  logIt::incrDebug();
+	  break;
+	default:
+	  std::cerr << "Invalid option supplied. Aborting." << std::endl;
+	  std::cerr << std::endl;
+	  usage(argv);
+	}
+    }
+
+  if (argc-optind < 3)
+    {
+      std::cerr << "Required arguments missing." << std::endl;
+      std::cerr << std::endl;
+      usage(argv);
+      return 1;
+    }
+
+  configfile0 = argv[optind++];
+  configfile1 = argv[optind++];
+  std::string outDir = argv[optind++];
+
+  logger(logDEBUG) << "Settings";
+  logger(logDEBUG) << " outDir: " << outDir;
+  logger(logDEBUG) << " configfile0: " << configfile0;
+  logger(logDEBUG) << " configfile1: " << configfile1;
+
+  // Get default config
+  json defconfig0;
+  if(!configfile0.empty())
+    {
+      std::ifstream fh_in(configfile0);
+      if(fh_in.is_open())
+	fh_in >> defconfig0;
+    }
+  json defconfig1;
+  if(!configfile1.empty())
+    {
+      std::ifstream fh_in(configfile1);
+      if(fh_in.is_open())
+	fh_in >> defconfig1;
+    }
+
+
+  // Create and initialize the testbench
+  PBv3TBConf factory_pbv3tb(equipConfigFile);
+  std::shared_ptr<PBv3TB> tb=factory_pbv3tb.getPBv3TB("default");
+  if(tb==nullptr)
+    return 1;
+
+  std::shared_ptr<AMACv2> amac0=tb->getPB(1);
+  std::shared_ptr<AMACv2> amac1=tb->getPB(2);
+  amac0->init();
+  amac1->init();
+
+  // 
+  // Start running tests in a loop forever!
+  //
+  while(true)
+    {
+      //
+      // Rerun the calibration
+
+      //Run all calibrations
+      json config0=defconfig0;
+      config0.merge_patch(PBv3ConfigTools::tuneNTC             (amac0));
+      config0.merge_patch(PBv3ConfigTools::calibrateSlope      (amac0, tb->getCalDAC()));
+      config0.merge_patch(PBv3ConfigTools::calibrateOffset     (amac0));
+      config0.merge_patch(PBv3ConfigTools::calibrateNTC        (amac0));
+      PBv3ConfigTools::saveConfigAMAC(amac0, config0);
+
+      json config1=defconfig1;
+      config1.merge_patch(PBv3ConfigTools::tuneNTC             (amac1));
+      config1.merge_patch(PBv3ConfigTools::calibrateSlope      (amac1, tb->getCalDAC()));
+      config1.merge_patch(PBv3ConfigTools::calibrateOffset     (amac1));
+      config1.merge_patch(PBv3ConfigTools::calibrateNTC        (amac1));
+      PBv3ConfigTools::saveConfigAMAC(amac1, config1);
+
+      // Prepare the output structures
+      std::string time_start = PBv3Utils::getTimeAsString(std::chrono::system_clock::now()); 
+
+      json testSum0;
+      testSum0["program"] = argv[0];
+      testSum0["config"] = config0;
+      testSum0["time"]["start"] = time_start;
+
+      json testSum1;
+      testSum1["program"] = argv[0];
+      testSum1["config"] = config1;
+      testSum1["time"]["start"] = time_start;
+
+      uint32_t test=0;
+
+      // Start monitoring in a loop
+      for(uint32_t monIdx=0; monIdx<PERIOD_LONG/PERIOD_MONITOR; monIdx++)
+	{
+	  if(std::dynamic_pointer_cast<PBv3TBSingle>(tb))
+	    {
+	      testSum0["tests"][test] = PBv3TestTools::readStatus(amac0, tb->getLVPS(), std::dynamic_pointer_cast<PBv3TBSingle>(tb)->getLoadPtr(), tb->getHVPS());
+	      testSum1["tests"][test] = PBv3TestTools::readStatus(amac1, tb->getLVPS(), std::dynamic_pointer_cast<PBv3TBSingle>(tb)->getLoadPtr(), tb->getHVPS());
+	    }
+	  else
+	    {
+	      testSum0["tests"][test] = PBv3TestTools::readStatus(amac0, tb->getLVPS(), nullptr, tb->getHVPS());
+	      testSum1["tests"][test] = PBv3TestTools::readStatus(amac1, tb->getLVPS(), nullptr, tb->getHVPS());
+	    }
+	  ++test;
+	  std::this_thread::sleep_for(std::chrono::seconds(PERIOD_MONITOR));
+	}
+
+      testSum0["tests"][test] = PBv3TestTools::checkSEUs(amac0);
+      testSum1["tests"][test] = PBv3TestTools::checkSEUs(amac1);
+      ++test;
+
+      // cleanup the file
+      std::string time_end = PBv3Utils::getTimeAsString(std::chrono::system_clock::now()); 
+      testSum0["time"]["end"] = time_end;
+      testSum1["time"]["end"] = time_end;
+
+      // Output file
+      std::string fileName0 = outDir + "/" + PBv3Utils::getTimeAsString(std::chrono::system_clock::now()) + "_pbv3-pb0.json";
+      std::fstream outfile0(fileName0, std::ios::out);
+      outfile0 << std::setw(4) << testSum0 << std::endl;
+      outfile0.close();
+
+      std::string fileName1 = outDir + "/" + PBv3Utils::getTimeAsString(std::chrono::system_clock::now()) + "_pbv3-pb1.json";
+      std::fstream outfile1(fileName1, std::ios::out);
+      outfile1 << std::setw(4) << testSum1 << std::endl;
+      outfile1.close();
+
+      logger(logINFO) << "Results stored in " << fileName0 << " and " << fileName1;
+    }
+
+  return 0;
+}
-- 
GitLab


From 784abdf6ce68272f11d28149342dff7ca8c90db6 Mon Sep 17 00:00:00 2001
From: Karol Krizka <kkrizka@gmail.com>
Date: Mon, 24 Aug 2020 16:39:51 -0700
Subject: [PATCH 17/29] Start on adding AMACv2Register.

---
 pbv3/AMACv2.cpp                          |  48 +-
 pbv3/AMACv2.h                            |  10 +-
 pbv3/AMACv2Field.cpp                     |  94 +++
 pbv3/AMACv2Field.h                       |  62 ++
 pbv3/{AMACv2Reg.cpp => AMACv2RegMap.cpp} | 989 ++++++++++-------------
 pbv3/{AMACv2Reg.h => AMACv2RegMap.h}     |  84 +-
 pbv3/AMACv2Register.cpp                  |   0
 pbv3/AMACv2Register.h                    |  22 +
 pbv3/CMakeLists.txt                      |   4 +-
 9 files changed, 679 insertions(+), 634 deletions(-)
 create mode 100644 pbv3/AMACv2Field.cpp
 create mode 100644 pbv3/AMACv2Field.h
 rename pbv3/{AMACv2Reg.cpp => AMACv2RegMap.cpp} (56%)
 rename pbv3/{AMACv2Reg.h => AMACv2RegMap.h} (86%)
 create mode 100644 pbv3/AMACv2Register.cpp
 create mode 100644 pbv3/AMACv2Register.h

diff --git a/pbv3/AMACv2.cpp b/pbv3/AMACv2.cpp
index d78d4a53..bf00dcb6 100644
--- a/pbv3/AMACv2.cpp
+++ b/pbv3/AMACv2.cpp
@@ -5,7 +5,7 @@
 #include "EndeavourComException.h"
 
 AMACv2::AMACv2(unsigned short amacid, std::unique_ptr<EndeavourRaw> raw)
-  : EndeavourCom(amacid, std::move(raw)), AMACv2Reg()
+  : EndeavourCom(amacid, std::move(raw)), AMACv2RegMap()
 { }
 
 AMACv2::~AMACv2(){}
@@ -33,7 +33,7 @@ void AMACv2::initRegisters()
     }
 
   // Write AMAC registers into the chip
-  for(const std::pair<uint32_t, rw_t>& reg : AMACv2Reg::Registers)
+  for(const std::pair<uint32_t, rw_t>& reg : AMACv2RegMap::Registers)
     {
       if(reg.second!=RW)
 	continue;
@@ -45,7 +45,7 @@ void AMACv2::initRegisters()
 void AMACv2::loadRegisters()
 { 
   // Load register map with current values
-  for(const std::pair<uint32_t, rw_t>& reg : AMACv2Reg::Registers)
+  for(const std::pair<uint32_t, rw_t>& reg : AMACv2RegMap::Registers)
     {
       if(reg.second!=RW && reg.second!=RO)
 	continue;
@@ -64,12 +64,12 @@ bool AMACv2::isCommIDSet()
   return true;
 }
 
-void AMACv2::syncReg(AMACv2Field AMACv2Reg::* ref)
+void AMACv2::syncReg(AMACv2Field AMACv2RegMap::* ref)
 {
   EndeavourCom::write_reg(getAddr(ref), (this->*ref).readRaw());
 }
 
-void AMACv2::wrField(AMACv2Field AMACv2Reg::* ref, uint32_t data)
+void AMACv2::wrField(AMACv2Field AMACv2RegMap::* ref, uint32_t data)
 {
   setField(ref, data);
   EndeavourCom::write_reg(getAddr(ref), (this->*ref).readRaw());
@@ -83,7 +83,7 @@ void AMACv2::wrField(const std::string& fieldName, uint32_t data)
   usleep(1e4);
 }
 
-uint32_t AMACv2::rdField(AMACv2Field AMACv2Reg::* ref)
+uint32_t AMACv2::rdField(AMACv2Field AMACv2RegMap::* ref)
 {
   uint32_t ret = EndeavourCom::read_reg(getAddr(ref));  
   setReg(getAddr(ref), ret);
@@ -168,66 +168,66 @@ double AMACv2::getADC(uint8_t ch)
 
 double AMACv2::getVDDREG()
 {
-  wrField(&AMACv2Reg::Ch3Mux, 0);
-  uint32_t counts=rdField(&AMACv2Reg::Ch3Value);
+  wrField(&AMACv2RegMap::Ch3Mux, 0);
+  uint32_t counts=rdField(&AMACv2RegMap::Ch3Value);
   return calibrateCounts(3, counts)*3/2;
 }
 
 double AMACv2::getAM()
 {
-  wrField(&AMACv2Reg::Ch4Mux, 0);
-  uint32_t counts=rdField(&AMACv2Reg::Ch4Value);
+  wrField(&AMACv2RegMap::Ch4Mux, 0);
+  uint32_t counts=rdField(&AMACv2RegMap::Ch4Value);
   return calibrateCounts(4, counts);
 }
 
 double AMACv2::getAM900()
 {
-  wrField(&AMACv2Reg::Ch3Mux, 2);
-  uint32_t counts=rdField(&AMACv2Reg::Ch3Value);
+  wrField(&AMACv2RegMap::Ch3Mux, 2);
+  uint32_t counts=rdField(&AMACv2RegMap::Ch3Value);
   return calibrateCounts(3, counts);
 }
 
 double AMACv2::getNTCx()
 {
-  uint32_t counts=rdField(&AMACv2Reg::Ch7Value);
+  uint32_t counts=rdField(&AMACv2RegMap::Ch7Value);
   return calibrateCounts(7, counts);
 }
 
 double AMACv2::getNTCy()
 {
-  uint32_t counts=rdField(&AMACv2Reg::Ch8Value);
+  uint32_t counts=rdField(&AMACv2RegMap::Ch8Value);
   return calibrateCounts(8, counts);
 }
 
 double AMACv2::getNTCpb()
 {
-  uint32_t counts=rdField(&AMACv2Reg::Ch9Value);
+  uint32_t counts=rdField(&AMACv2RegMap::Ch9Value);
   return calibrateCounts(9, counts);
 }
 
 double AMACv2::getPTAT()
 {
-  uint32_t counts=rdField(&AMACv2Reg::Ch15Value);
+  uint32_t counts=rdField(&AMACv2RegMap::Ch15Value);
   return calibrateCounts(15, counts);
 }
 
 double AMACv2::getCTAT()
 {
-  uint32_t counts=rdField(&AMACv2Reg::Ch6Value);
+  uint32_t counts=rdField(&AMACv2RegMap::Ch6Value);
   return calibrateCounts(6, counts);
 }
 
 double AMACv2::getCur10V()
 {
-  wrField(&AMACv2Reg::Ch12Mux , 0); // Read the out difference
-  uint32_t counts=rdField(&AMACv2Reg::Ch12Value);
+  wrField(&AMACv2RegMap::Ch12Mux , 0); // Read the out difference
+  uint32_t counts=rdField(&AMACv2RegMap::Ch12Value);
   return calibrateCounts(12, counts)/10.4;
 }
 
 double AMACv2::getCur1V()
 {
-  wrField(&AMACv2Reg::Ch13Mux , 0); // Read the out difference
-  uint32_t counts=rdField(&AMACv2Reg::Ch13Value);
+  wrField(&AMACv2RegMap::Ch13Mux , 0); // Read the out difference
+  uint32_t counts=rdField(&AMACv2RegMap::Ch13Value);
   return calibrateCounts(13, counts)/30.;
 }
 
@@ -240,7 +240,7 @@ double AMACv2::temperatureY()
 double AMACv2::temperaturePB()
 {
   // Determine the settings
-  uint32_t SR=rdField(&AMACv2Reg::NTCpbSenseRange);
+  uint32_t SR=rdField(&AMACv2RegMap::NTCpbSenseRange);
   bool NTCS0=(SR>>0)&1;
   bool NTCS1=(SR>>1)&1;
   bool NTCS2=(SR>>2)&1;
@@ -276,11 +276,11 @@ double AMACv2::temperaturePTAT()
 
 double AMACv2::temperatureCTAT()
 {
-  uint32_t CTAToffset=rdField(&AMACv2Reg::CTAToffset);
+  uint32_t CTAToffset=rdField(&AMACv2RegMap::CTAToffset);
   return (getCTAT()-m_CTAT0[CTAToffset])/(-1.5);
 }
 
 uint32_t AMACv2::readEFuse()
 {
-  return rdField(&AMACv2Reg::SerNum);
+  return rdField(&AMACv2RegMap::SerNum);
 }
diff --git a/pbv3/AMACv2.h b/pbv3/AMACv2.h
index 423b3714..cabca336 100644
--- a/pbv3/AMACv2.h
+++ b/pbv3/AMACv2.h
@@ -1,11 +1,11 @@
 #ifndef AMACv2_H_
 #define AMACv2_H_
 
-#include "AMACv2Reg.h"
+#include "AMACv2RegMap.h"
 #include "EndeavourCom.h"
 #include "EndeavourRaw.h"
 
-class AMACv2 : public EndeavourCom, public AMACv2Reg
+class AMACv2 : public EndeavourCom, public AMACv2RegMap
 {
 public:
   AMACv2(unsigned short amacid, std::unique_ptr<EndeavourRaw> raw); // with hardware	
@@ -25,10 +25,10 @@ public:
   virtual void write_reg(unsigned int address, unsigned int data);
   virtual unsigned int read_reg(unsigned int address);
 
-  void wrField(AMACv2Field AMACv2Reg::* ref, uint32_t data);
+  void wrField(AMACv2Field AMACv2RegMap::* ref, uint32_t data);
   void wrField(const std::string& fieldName, uint32_t data);
 
-  uint32_t rdField(AMACv2Field AMACv2Reg::* ref);
+  uint32_t rdField(AMACv2Field AMACv2RegMap::* ref);
   uint32_t rdField(const std::string& fieldName);
 
   //
@@ -159,7 +159,7 @@ public:
 private:
   double calibrateCounts(uint8_t ch, uint32_t counts);
 
-  void syncReg(AMACv2Field AMACv2Reg::* ref);
+  void syncReg(AMACv2Field AMACv2RegMap::* ref);
 
   double   m_ADCslope      =1.;
   uint32_t m_ADCoffset[16] ={0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
diff --git a/pbv3/AMACv2Field.cpp b/pbv3/AMACv2Field.cpp
new file mode 100644
index 00000000..2bf5c8df
--- /dev/null
+++ b/pbv3/AMACv2Field.cpp
@@ -0,0 +1,94 @@
+#include "AMACv2Field.h"
+
+AMACv2Field::AMACv2Field()
+{ }
+
+bool AMACv2Field::canBeWrittenField() const
+{ return (m_rw != RO); }
+
+bool AMACv2Field::canBeReadField() const
+{ return (m_rw != WO); }
+
+bool AMACv2Field::isReadWrite() const
+{ return (m_rw == RW); }
+
+std::string AMACv2Field::getFieldName() const
+{ return m_fieldName; }
+
+uint8_t AMACv2Field::getWidth() const
+{ return m_width; }
+
+void AMACv2Field::initReg(uint32_t* cfg, rw_t rw, uint32_t defaultVal, uint8_t width, uint8_t offset, uint8_t regNbr, const std::string& fieldName)
+{
+  m_cfg = cfg;
+  m_rw = rw;
+  m_defaultVal = defaultVal;
+  m_width = width;
+  m_offset = offset;
+  m_regNbr = regNbr;
+  m_mask = (uint32_t) (((1 << m_width) - 1) << m_offset);
+  m_fieldName = fieldName;
+  if(m_rw != RO)
+    this->write(m_defaultVal);
+}
+
+void AMACv2Field::setDefaultVal(uint32_t defaultVal)
+{
+  m_defaultVal=defaultVal;
+}
+
+void AMACv2Field::writeDefaultVal()
+{
+  if(m_rw == RO)
+    {
+      std::cerr << " --> Error: Read-only register \"" << m_fieldName <<"\""<< std::endl;
+      return;
+    }
+  write(m_defaultVal);
+}
+
+
+void AMACv2Field::write(const uint32_t& cfgBits)
+{
+  if(m_rw == RO)
+    {
+      std::cerr << " --> Error: Read-only register \"" << m_fieldName <<"\""<< std::endl;
+      return;
+    }
+  m_cfg[m_regNbr] = (m_cfg[m_regNbr]&~m_mask) | ((cfgBits << m_offset) & m_mask);
+}
+
+uint32_t AMACv2Field::read() const
+{
+  if(m_rw == WO)
+    {
+      std::cerr << " --> Error: Write-only register \"" << m_fieldName <<"\""<< std::endl;
+      return 0;
+    }
+  return ((m_cfg[m_regNbr] & m_mask) >> m_offset);
+}
+
+uint32_t AMACv2Field::readRaw() const
+{
+  if(m_rw == WO)
+    {
+      std::cerr << " --> Error: Write-only register \"" << m_fieldName <<"\""<< std::endl;
+      return 0;
+    }
+  return m_cfg[m_regNbr];
+}
+
+void AMACv2Field::writeRaw(const uint32_t& cfgBits)
+{
+  if(m_rw == RO)
+    {
+      std::cerr << " --> Error: Read-only register \"" << m_fieldName <<"\""<< std::endl;
+      return;
+    }
+  m_cfg[m_regNbr] = cfgBits;
+}
+
+uint8_t AMACv2Field::addr() const
+{ return m_regNbr; }
+
+
diff --git a/pbv3/AMACv2Field.h b/pbv3/AMACv2Field.h
new file mode 100644
index 00000000..973cccea
--- /dev/null
+++ b/pbv3/AMACv2Field.h
@@ -0,0 +1,62 @@
+#ifndef AMACV2_FIELD_H
+#define AMACV2_FIELD_H
+
+#include "AMACv2Register.h"
+
+//! \brief Definition and manipulation of an AMACv2 register field
+/**
+ * A register field is a set of bits inside a register that
+ * control a specific setting.
+ */
+class AMACv2Field
+{
+private:
+  //! The whole register
+  std::shared_ptr<AMACv2Register> m_register;
+
+  //! Default field value
+  uint32_t m_defaultVal = 0;
+
+  //! Number of bits
+  uint8_t m_width = 0;
+
+  //! Position of the LSB
+  uint8_t m_offset = 0;
+  uint8_t m_regNbr = 0;
+  uint32_t m_mask = 0;
+
+  //! Name of field
+  std::string m_fieldName = "";
+public:
+  AMACv2Field();
+
+  bool canBeWrittenField() const;
+  bool canBeReadField() const;
+  bool isReadWrite() const;
+
+  /** Get field name
+   * \return name of the field
+   */
+  std::string getFieldName() const;
+
+  /** Get field width
+   * \return width of field in bytes
+   */
+  uint8_t getWidth() const;
+		
+  void initField(std::shared_ptr<AMACv2Register> reg, uint32_t defaultVal, uint8_t width, uint8_t offset, const std::string& fieldName);
+
+  void setDefaultVal(uint32_t defaultVal);
+  void writeDefaultVal();
+
+  uint32_t read() const;
+  uint32_t readRaw() const;
+
+  void write(const uint32_t& cfgBits);		
+  void writeRaw(const uint32_t& cfgBits);
+
+  uint8_t addr() const;
+};
+
+
+#endif // AMACV2_FIELD_H
diff --git a/pbv3/AMACv2Reg.cpp b/pbv3/AMACv2RegMap.cpp
similarity index 56%
rename from pbv3/AMACv2Reg.cpp
rename to pbv3/AMACv2RegMap.cpp
index fef6aa4d..e3ced869 100644
--- a/pbv3/AMACv2Reg.cpp
+++ b/pbv3/AMACv2RegMap.cpp
@@ -1,97 +1,6 @@
-#include "AMACv2Reg.h"
+#include "AMACv2RegMap.h"
 
-AMACv2Field::AMACv2Field()
-{ }
-
-bool AMACv2Field::canBeWrittenField() const
-{ return (m_rw != RO); }
-
-bool AMACv2Field::canBeReadField() const
-{ return (m_rw != WO); }
-
-bool AMACv2Field::isReadWrite() const
-{ return (m_rw == RW); }
-
-std::string AMACv2Field::getFieldName() const
-{ return m_fieldName; }
-
-uint8_t AMACv2Field::getWidth() const
-{ return m_width; }
-
-void AMACv2Field::initReg(uint32_t* cfg, rw_t rw, uint32_t defaultVal, uint8_t width, uint8_t offset, uint8_t regNbr, const std::string& fieldName)
-{
-  m_cfg = cfg;
-  m_rw = rw;
-  m_defaultVal = defaultVal;
-  m_width = width;
-  m_offset = offset;
-  m_regNbr = regNbr;
-  m_mask = (uint32_t) (((1 << m_width) - 1) << m_offset);
-  m_fieldName = fieldName;
-  if(m_rw != RO)
-    this->write(m_defaultVal);
-}
-
-void AMACv2Field::setDefaultVal(uint32_t defaultVal)
-{
-  m_defaultVal=defaultVal;
-}
-
-void AMACv2Field::writeDefaultVal()
-{
-  if(m_rw == RO)
-    {
-      std::cerr << " --> Error: Read-only register \"" << m_fieldName <<"\""<< std::endl;
-      return;
-    }
-  write(m_defaultVal);
-}
-
-
-void AMACv2Field::write(const uint32_t& cfgBits)
-{
-  if(m_rw == RO)
-    {
-      std::cerr << " --> Error: Read-only register \"" << m_fieldName <<"\""<< std::endl;
-      return;
-    }
-  m_cfg[m_regNbr] = (m_cfg[m_regNbr]&~m_mask) | ((cfgBits << m_offset) & m_mask);
-}
-
-uint32_t AMACv2Field::read() const
-{
-  if(m_rw == WO)
-    {
-      std::cerr << " --> Error: Write-only register \"" << m_fieldName <<"\""<< std::endl;
-      return 0;
-    }
-  return ((m_cfg[m_regNbr] & m_mask) >> m_offset);
-}
-
-uint32_t AMACv2Field::readRaw() const
-{
-  if(m_rw == WO)
-    {
-      std::cerr << " --> Error: Write-only register \"" << m_fieldName <<"\""<< std::endl;
-      return 0;
-    }
-  return m_cfg[m_regNbr];
-}
-
-void AMACv2Field::writeRaw(const uint32_t& cfgBits)
-{
-  if(m_rw == RO)
-    {
-      std::cerr << " --> Error: Read-only register \"" << m_fieldName <<"\""<< std::endl;
-      return;
-    }
-  m_cfg[m_regNbr] = cfgBits;
-}
-
-uint8_t AMACv2Field::addr() const
-{ return m_regNbr; }
-
-const std::unordered_map<uint32_t, rw_t> AMACv2Reg::Registers =
+const std::unordered_map<uint32_t, rw_t> AMACv2RegMap::Registers =
   {
     {  0, RO},
     {  1, RO},
@@ -242,588 +151,588 @@ const std::unordered_map<uint32_t, rw_t> AMACv2Reg::Registers =
     {171, RW}
   };
 
-AMACv2Reg::AMACv2Reg()
+AMACv2RegMap::AMACv2RegMap()
 {
   init();
 }
 
-void AMACv2Reg::init()
+void AMACv2RegMap::init()
 {
 	
   for (unsigned int i=0; i<numRegs; i++) m_cfg[i] = 0;
 	
-  StatusAM  .initReg(m_cfg, RO, 0, 1, 31, 0, "StatusAM"  ); m_fieldMap["StatusAM"  ] = &AMACv2Reg::StatusAM;
-  StatusWARN.initReg(m_cfg, RO, 0, 1, 29, 0, "StatusWARN"); m_fieldMap["StatusWARN"] = &AMACv2Reg::StatusWARN;
-  StatusDCDC.initReg(m_cfg, RO, 0, 1, 28, 0, "StatusDCDC"); m_fieldMap["StatusDCDC"] = &AMACv2Reg::StatusDCDC;
-  StatusHV3.initReg(m_cfg, RO, 0, 1, 27, 0, "StatusHV3"); m_fieldMap["StatusHV3"] = &AMACv2Reg::StatusHV3;
-  StatusHV2.initReg(m_cfg, RO, 0, 1, 26, 0, "StatusHV2"); m_fieldMap["StatusHV2"] = &AMACv2Reg::StatusHV2;
-  StatusHV1.initReg(m_cfg, RO, 0, 1, 25, 0, "StatusHV1"); m_fieldMap["StatusHV1"] = &AMACv2Reg::StatusHV1;
-  StatusHV0.initReg(m_cfg, RO, 0, 1, 24, 0, "StatusHV0"); m_fieldMap["StatusHV0"] = &AMACv2Reg::StatusHV0;
-  StatusY2LDO.initReg(m_cfg, RO, 0, 1, 22, 0, "StatusY2LDO"); m_fieldMap["StatusY2LDO"] = &AMACv2Reg::StatusY2LDO;
-  StatusY1LDO.initReg(m_cfg, RO, 0, 1, 21, 0, "StatusY1LDO"); m_fieldMap["StatusY1LDO"] = &AMACv2Reg::StatusY1LDO;
-  StatusY0LDO.initReg(m_cfg, RO, 0, 1, 20, 0, "StatusY0LDO"); m_fieldMap["StatusY0LDO"] = &AMACv2Reg::StatusY0LDO;
-  StatusX2LDO.initReg(m_cfg, RO, 0, 1, 18, 0, "StatusX2LDO"); m_fieldMap["StatusX2LDO"] = &AMACv2Reg::StatusX2LDO;
-  StatusX1LDO.initReg(m_cfg, RO, 0, 1, 17, 0, "StatusX1LDO"); m_fieldMap["StatusX1LDO"] = &AMACv2Reg::StatusX1LDO;
-  StatusX0LDO.initReg(m_cfg, RO, 0, 1, 16, 0, "StatusX0LDO"); m_fieldMap["StatusX0LDO"] = &AMACv2Reg::StatusX0LDO;
-  StatusGPI.initReg(m_cfg, RO, 0, 1, 12, 0, "StatusGPI"); m_fieldMap["StatusGPI"] = &AMACv2Reg::StatusGPI;
-  StatusPGOOD.initReg(m_cfg, RO, 0, 1, 8, 0, "StatusPGOOD"); m_fieldMap["StatusPGOOD"] = &AMACv2Reg::StatusPGOOD;
-  StatusILockWARN.initReg(m_cfg, RO, 0, 1, 5, 0, "StatusILockWARN"); m_fieldMap["StatusILockWARN"] = &AMACv2Reg::StatusILockWARN;
-  StatusILockDCDC.initReg(m_cfg, RO, 0, 1, 4, 0, "StatusILockDCDC"); m_fieldMap["StatusILockDCDC"] = &AMACv2Reg::StatusILockDCDC;
-  StatusILockHV2.initReg(m_cfg, RO, 0, 1, 3, 0, "StatusILockHV2"); m_fieldMap["StatusILockHV2"] = &AMACv2Reg::StatusILockHV2;
-  StatusILockHV2.initReg(m_cfg, RO, 0, 1, 2, 0, "StatusILockHV2"); m_fieldMap["StatusILockHV2"] = &AMACv2Reg::StatusILockHV2;
-  StatusILockYLDO.initReg(m_cfg, RO, 0, 1, 1, 0, "StatusILockYLDO"); m_fieldMap["StatusILockYLDO"] = &AMACv2Reg::StatusILockYLDO;
-  StatusILockxLDO.initReg(m_cfg, RO, 0, 1, 0, 0, "StatusILockxLDO"); m_fieldMap["StatusILockxLDO"] = &AMACv2Reg::StatusILockxLDO;
+  StatusAM  .initReg(m_cfg, RO, 0, 1, 31, 0, "StatusAM"  ); m_fieldMap["StatusAM"  ] = &AMACv2RegMap::StatusAM;
+  StatusWARN.initReg(m_cfg, RO, 0, 1, 29, 0, "StatusWARN"); m_fieldMap["StatusWARN"] = &AMACv2RegMap::StatusWARN;
+  StatusDCDC.initReg(m_cfg, RO, 0, 1, 28, 0, "StatusDCDC"); m_fieldMap["StatusDCDC"] = &AMACv2RegMap::StatusDCDC;
+  StatusHV3.initReg(m_cfg, RO, 0, 1, 27, 0, "StatusHV3"); m_fieldMap["StatusHV3"] = &AMACv2RegMap::StatusHV3;
+  StatusHV2.initReg(m_cfg, RO, 0, 1, 26, 0, "StatusHV2"); m_fieldMap["StatusHV2"] = &AMACv2RegMap::StatusHV2;
+  StatusHV1.initReg(m_cfg, RO, 0, 1, 25, 0, "StatusHV1"); m_fieldMap["StatusHV1"] = &AMACv2RegMap::StatusHV1;
+  StatusHV0.initReg(m_cfg, RO, 0, 1, 24, 0, "StatusHV0"); m_fieldMap["StatusHV0"] = &AMACv2RegMap::StatusHV0;
+  StatusY2LDO.initReg(m_cfg, RO, 0, 1, 22, 0, "StatusY2LDO"); m_fieldMap["StatusY2LDO"] = &AMACv2RegMap::StatusY2LDO;
+  StatusY1LDO.initReg(m_cfg, RO, 0, 1, 21, 0, "StatusY1LDO"); m_fieldMap["StatusY1LDO"] = &AMACv2RegMap::StatusY1LDO;
+  StatusY0LDO.initReg(m_cfg, RO, 0, 1, 20, 0, "StatusY0LDO"); m_fieldMap["StatusY0LDO"] = &AMACv2RegMap::StatusY0LDO;
+  StatusX2LDO.initReg(m_cfg, RO, 0, 1, 18, 0, "StatusX2LDO"); m_fieldMap["StatusX2LDO"] = &AMACv2RegMap::StatusX2LDO;
+  StatusX1LDO.initReg(m_cfg, RO, 0, 1, 17, 0, "StatusX1LDO"); m_fieldMap["StatusX1LDO"] = &AMACv2RegMap::StatusX1LDO;
+  StatusX0LDO.initReg(m_cfg, RO, 0, 1, 16, 0, "StatusX0LDO"); m_fieldMap["StatusX0LDO"] = &AMACv2RegMap::StatusX0LDO;
+  StatusGPI.initReg(m_cfg, RO, 0, 1, 12, 0, "StatusGPI"); m_fieldMap["StatusGPI"] = &AMACv2RegMap::StatusGPI;
+  StatusPGOOD.initReg(m_cfg, RO, 0, 1, 8, 0, "StatusPGOOD"); m_fieldMap["StatusPGOOD"] = &AMACv2RegMap::StatusPGOOD;
+  StatusILockWARN.initReg(m_cfg, RO, 0, 1, 5, 0, "StatusILockWARN"); m_fieldMap["StatusILockWARN"] = &AMACv2RegMap::StatusILockWARN;
+  StatusILockDCDC.initReg(m_cfg, RO, 0, 1, 4, 0, "StatusILockDCDC"); m_fieldMap["StatusILockDCDC"] = &AMACv2RegMap::StatusILockDCDC;
+  StatusILockHV2.initReg(m_cfg, RO, 0, 1, 3, 0, "StatusILockHV2"); m_fieldMap["StatusILockHV2"] = &AMACv2RegMap::StatusILockHV2;
+  StatusILockHV2.initReg(m_cfg, RO, 0, 1, 2, 0, "StatusILockHV2"); m_fieldMap["StatusILockHV2"] = &AMACv2RegMap::StatusILockHV2;
+  StatusILockYLDO.initReg(m_cfg, RO, 0, 1, 1, 0, "StatusILockYLDO"); m_fieldMap["StatusILockYLDO"] = &AMACv2RegMap::StatusILockYLDO;
+  StatusILockxLDO.initReg(m_cfg, RO, 0, 1, 0, 0, "StatusILockxLDO"); m_fieldMap["StatusILockxLDO"] = &AMACv2RegMap::StatusILockxLDO;
   // 1 - HxFlags
-  HxFlagsHi.initReg(m_cfg, RO, 0, 16, 16, 1, "HxFlagsHi"); m_fieldMap["HxFlagsHi"] = &AMACv2Reg::HxFlagsHi;
-  HxFlagsLo.initReg(m_cfg, RO, 0, 16, 0, 1, "HxFlagsLo"); m_fieldMap["HxFlagsLo"] = &AMACv2Reg::HxFlagsLo;
+  HxFlagsHi.initReg(m_cfg, RO, 0, 16, 16, 1, "HxFlagsHi"); m_fieldMap["HxFlagsHi"] = &AMACv2RegMap::HxFlagsHi;
+  HxFlagsLo.initReg(m_cfg, RO, 0, 16, 0, 1, "HxFlagsLo"); m_fieldMap["HxFlagsLo"] = &AMACv2RegMap::HxFlagsLo;
   // 2 - HyFlags
-  HyFlagsHi.initReg(m_cfg, RO, 0, 16, 16, 2, "HyFlagsHi"); m_fieldMap["HyFlagsHi"] = &AMACv2Reg::HyFlagsHi;
-  HyFlagsLo.initReg(m_cfg, RO, 0, 16, 0, 2, "HyFlagsLo"); m_fieldMap["HyFlagsLo"] = &AMACv2Reg::HyFlagsLo;
+  HyFlagsHi.initReg(m_cfg, RO, 0, 16, 16, 2, "HyFlagsHi"); m_fieldMap["HyFlagsHi"] = &AMACv2RegMap::HyFlagsHi;
+  HyFlagsLo.initReg(m_cfg, RO, 0, 16, 0, 2, "HyFlagsLo"); m_fieldMap["HyFlagsLo"] = &AMACv2RegMap::HyFlagsLo;
   // 3 - HV0Flags
-  HV0FlagsHi.initReg(m_cfg, RO, 0, 16, 16, 3, "HV0FlagsHi"); m_fieldMap["HV0FlagsHi"] = &AMACv2Reg::HV0FlagsHi;
-  HV0FlagsLo.initReg(m_cfg, RO, 0, 16, 0, 3, "HV0FlagsLo"); m_fieldMap["HV0FlagsLo"] = &AMACv2Reg::HV0FlagsLo;
+  HV0FlagsHi.initReg(m_cfg, RO, 0, 16, 16, 3, "HV0FlagsHi"); m_fieldMap["HV0FlagsHi"] = &AMACv2RegMap::HV0FlagsHi;
+  HV0FlagsLo.initReg(m_cfg, RO, 0, 16, 0, 3, "HV0FlagsLo"); m_fieldMap["HV0FlagsLo"] = &AMACv2RegMap::HV0FlagsLo;
   // 4 - HV2Flags
-  HV2FlagsHi.initReg(m_cfg, RO, 0, 16, 16, 4, "HV2FlagsHi"); m_fieldMap["HV2FlagsHi"] = &AMACv2Reg::HV2FlagsHi;
-  HV2FlagsLo.initReg(m_cfg, RO, 0, 16, 0, 4, "HV2FlagsLo"); m_fieldMap["HV2FlagsLo"] = &AMACv2Reg::HV2FlagsLo;
+  HV2FlagsHi.initReg(m_cfg, RO, 0, 16, 16, 4, "HV2FlagsHi"); m_fieldMap["HV2FlagsHi"] = &AMACv2RegMap::HV2FlagsHi;
+  HV2FlagsLo.initReg(m_cfg, RO, 0, 16, 0, 4, "HV2FlagsLo"); m_fieldMap["HV2FlagsLo"] = &AMACv2RegMap::HV2FlagsLo;
   // 5 - DCDCflags
-  DCDCflagsHi.initReg(m_cfg, RO, 0, 16, 16, 5, "DCDCflagsHi"); m_fieldMap["DCDCflagsHi"] = &AMACv2Reg::DCDCflagsHi;
-  DCDCflagsLo.initReg(m_cfg, RO, 0, 16, 0, 5, "DCDCflagsLo"); m_fieldMap["DCDCflagsLo"] = &AMACv2Reg::DCDCflagsLo;
+  DCDCflagsHi.initReg(m_cfg, RO, 0, 16, 16, 5, "DCDCflagsHi"); m_fieldMap["DCDCflagsHi"] = &AMACv2RegMap::DCDCflagsHi;
+  DCDCflagsLo.initReg(m_cfg, RO, 0, 16, 0, 5, "DCDCflagsLo"); m_fieldMap["DCDCflagsLo"] = &AMACv2RegMap::DCDCflagsLo;
   // 6 - WRNflags
-  WRNflagsHi.initReg(m_cfg, RO, 0, 16, 16, 6, "WRNflagsHi"); m_fieldMap["WRNflagsHi"] = &AMACv2Reg::WRNflagsHi;
-  WRNflagsLo.initReg(m_cfg, RO, 0, 16, 0, 6, "WRNflagsLo"); m_fieldMap["WRNflagsLo"] = &AMACv2Reg::WRNflagsLo;
+  WRNflagsHi.initReg(m_cfg, RO, 0, 16, 16, 6, "WRNflagsHi"); m_fieldMap["WRNflagsHi"] = &AMACv2RegMap::WRNflagsHi;
+  WRNflagsLo.initReg(m_cfg, RO, 0, 16, 0, 6, "WRNflagsLo"); m_fieldMap["WRNflagsLo"] = &AMACv2RegMap::WRNflagsLo;
   // 7 - SynFlags
-  SynFlagsWRN.initReg(m_cfg, RO, 0, 2, 20, 7, "SynFlagsWRN"); m_fieldMap["SynFlagsWRN"] = &AMACv2Reg::SynFlagsWRN;
-  SynFlagsDCDC.initReg(m_cfg, RO, 0, 2, 16, 7, "SynFlagsDCDC"); m_fieldMap["SynFlagsDCDC"] = &AMACv2Reg::SynFlagsDCDC;
-  SynFlagsHV2.initReg(m_cfg, RO, 0, 2, 12, 7, "SynFlagsHV2"); m_fieldMap["SynFlagsHV2"] = &AMACv2Reg::SynFlagsHV2;
-  SynFlagsHV2.initReg(m_cfg, RO, 0, 2, 8, 7, "SynFlagsHV2"); m_fieldMap["SynFlagsHV2"] = &AMACv2Reg::SynFlagsHV2;
-  SynFlagsHy.initReg(m_cfg, RO, 0, 2, 4, 7, "SynFlagsHy"); m_fieldMap["SynFlagsHy"] = &AMACv2Reg::SynFlagsHy;
-  SynFlagsHx.initReg(m_cfg, RO, 0, 2, 0, 7, "SynFlagsHx"); m_fieldMap["SynFlagsHx"] = &AMACv2Reg::SynFlagsHx;
+  SynFlagsWRN.initReg(m_cfg, RO, 0, 2, 20, 7, "SynFlagsWRN"); m_fieldMap["SynFlagsWRN"] = &AMACv2RegMap::SynFlagsWRN;
+  SynFlagsDCDC.initReg(m_cfg, RO, 0, 2, 16, 7, "SynFlagsDCDC"); m_fieldMap["SynFlagsDCDC"] = &AMACv2RegMap::SynFlagsDCDC;
+  SynFlagsHV2.initReg(m_cfg, RO, 0, 2, 12, 7, "SynFlagsHV2"); m_fieldMap["SynFlagsHV2"] = &AMACv2RegMap::SynFlagsHV2;
+  SynFlagsHV2.initReg(m_cfg, RO, 0, 2, 8, 7, "SynFlagsHV2"); m_fieldMap["SynFlagsHV2"] = &AMACv2RegMap::SynFlagsHV2;
+  SynFlagsHy.initReg(m_cfg, RO, 0, 2, 4, 7, "SynFlagsHy"); m_fieldMap["SynFlagsHy"] = &AMACv2RegMap::SynFlagsHy;
+  SynFlagsHx.initReg(m_cfg, RO, 0, 2, 0, 7, "SynFlagsHx"); m_fieldMap["SynFlagsHx"] = &AMACv2RegMap::SynFlagsHx;
   // 10 - Value0
-  Value0AMen.initReg(m_cfg, RO, 0, 1, 31, 10, "Value0AMen"); m_fieldMap["Value0AMen"] = &AMACv2Reg::Value0AMen;
-  Ch0Value.initReg(m_cfg, RO, 0, 10, 0, 10, "Ch0Value"); m_fieldMap["Ch0Value"] = &AMACv2Reg::Ch0Value;
-  Ch1Value.initReg(m_cfg, RO, 0, 10, 10, 10, "Ch1Value"); m_fieldMap["Ch1Value"] = &AMACv2Reg::Ch1Value;
-  Ch2Value.initReg(m_cfg, RO, 0, 10, 20, 10, "Ch2Value"); m_fieldMap["Ch2Value"] = &AMACv2Reg::Ch2Value;
+  Value0AMen.initReg(m_cfg, RO, 0, 1, 31, 10, "Value0AMen"); m_fieldMap["Value0AMen"] = &AMACv2RegMap::Value0AMen;
+  Ch0Value.initReg(m_cfg, RO, 0, 10, 0, 10, "Ch0Value"); m_fieldMap["Ch0Value"] = &AMACv2RegMap::Ch0Value;
+  Ch1Value.initReg(m_cfg, RO, 0, 10, 10, 10, "Ch1Value"); m_fieldMap["Ch1Value"] = &AMACv2RegMap::Ch1Value;
+  Ch2Value.initReg(m_cfg, RO, 0, 10, 20, 10, "Ch2Value"); m_fieldMap["Ch2Value"] = &AMACv2RegMap::Ch2Value;
   // 11 - Value1
-  Value1AMen.initReg(m_cfg, RO, 0, 1, 31, 11, "Value1AMen"); m_fieldMap["Value1AMen"] = &AMACv2Reg::Value1AMen;
-  Ch3Value.initReg(m_cfg, RO, 0, 10, 0, 11, "Ch3Value"); m_fieldMap["Ch3Value"] = &AMACv2Reg::Ch3Value;
-  Ch4Value.initReg(m_cfg, RO, 0, 10, 10, 11, "Ch4Value"); m_fieldMap["Ch4Value"] = &AMACv2Reg::Ch4Value;
-  Ch5Value.initReg(m_cfg, RO, 0, 10, 20, 11, "Ch5Value"); m_fieldMap["Ch5Value"] = &AMACv2Reg::Ch5Value;
+  Value1AMen.initReg(m_cfg, RO, 0, 1, 31, 11, "Value1AMen"); m_fieldMap["Value1AMen"] = &AMACv2RegMap::Value1AMen;
+  Ch3Value.initReg(m_cfg, RO, 0, 10, 0, 11, "Ch3Value"); m_fieldMap["Ch3Value"] = &AMACv2RegMap::Ch3Value;
+  Ch4Value.initReg(m_cfg, RO, 0, 10, 10, 11, "Ch4Value"); m_fieldMap["Ch4Value"] = &AMACv2RegMap::Ch4Value;
+  Ch5Value.initReg(m_cfg, RO, 0, 10, 20, 11, "Ch5Value"); m_fieldMap["Ch5Value"] = &AMACv2RegMap::Ch5Value;
   // 12 - Value2
-  Value2AMen.initReg(m_cfg, RO, 0, 1, 31, 12, "Value2AMen"); m_fieldMap["Value2AMen"] = &AMACv2Reg::Value2AMen;
-  Ch6Value.initReg(m_cfg, RO, 0, 10, 0, 12, "Ch6Value"); m_fieldMap["Ch6Value"] = &AMACv2Reg::Ch6Value;
-  Ch7Value.initReg(m_cfg, RO, 0, 10, 10, 12, "Ch7Value"); m_fieldMap["Ch7Value"] = &AMACv2Reg::Ch7Value;
-  Ch8Value.initReg(m_cfg, RO, 0, 10, 20, 12, "Ch8Value"); m_fieldMap["Ch8Value"] = &AMACv2Reg::Ch8Value;
+  Value2AMen.initReg(m_cfg, RO, 0, 1, 31, 12, "Value2AMen"); m_fieldMap["Value2AMen"] = &AMACv2RegMap::Value2AMen;
+  Ch6Value.initReg(m_cfg, RO, 0, 10, 0, 12, "Ch6Value"); m_fieldMap["Ch6Value"] = &AMACv2RegMap::Ch6Value;
+  Ch7Value.initReg(m_cfg, RO, 0, 10, 10, 12, "Ch7Value"); m_fieldMap["Ch7Value"] = &AMACv2RegMap::Ch7Value;
+  Ch8Value.initReg(m_cfg, RO, 0, 10, 20, 12, "Ch8Value"); m_fieldMap["Ch8Value"] = &AMACv2RegMap::Ch8Value;
   // 13 - Value3
-  Value3AMen.initReg(m_cfg, RO, 0, 1, 31, 13, "Value3AMen"); m_fieldMap["Value3AMen"] = &AMACv2Reg::Value3AMen;
-  Ch9Value.initReg(m_cfg, RO, 0, 10, 0, 13, "Ch9Value"); m_fieldMap["Ch9Value"] = &AMACv2Reg::Ch9Value;
-  Ch10Value.initReg(m_cfg, RO, 0, 10, 10, 13, "Ch10Value"); m_fieldMap["Ch10Value"] = &AMACv2Reg::Ch10Value;
-  Ch11Value.initReg(m_cfg, RO, 0, 10, 20, 13, "Ch11Value"); m_fieldMap["Ch11Value"] = &AMACv2Reg::Ch11Value;
+  Value3AMen.initReg(m_cfg, RO, 0, 1, 31, 13, "Value3AMen"); m_fieldMap["Value3AMen"] = &AMACv2RegMap::Value3AMen;
+  Ch9Value.initReg(m_cfg, RO, 0, 10, 0, 13, "Ch9Value"); m_fieldMap["Ch9Value"] = &AMACv2RegMap::Ch9Value;
+  Ch10Value.initReg(m_cfg, RO, 0, 10, 10, 13, "Ch10Value"); m_fieldMap["Ch10Value"] = &AMACv2RegMap::Ch10Value;
+  Ch11Value.initReg(m_cfg, RO, 0, 10, 20, 13, "Ch11Value"); m_fieldMap["Ch11Value"] = &AMACv2RegMap::Ch11Value;
   // 14 - Value4
-  Value4AMen.initReg(m_cfg, RO, 0, 1, 31, 14, "Value4AMen"); m_fieldMap["Value4AMen"] = &AMACv2Reg::Value4AMen;
-  Ch12Value.initReg(m_cfg, RO, 0, 10, 0, 14, "Ch12Value"); m_fieldMap["Ch12Value"] = &AMACv2Reg::Ch12Value;
-  Ch13Value.initReg(m_cfg, RO, 0, 10, 10, 14, "Ch13Value"); m_fieldMap["Ch13Value"] = &AMACv2Reg::Ch13Value;
-  Ch14Value.initReg(m_cfg, RO, 0, 10, 20, 14, "Ch14Value"); m_fieldMap["Ch14Value"] = &AMACv2Reg::Ch14Value;
+  Value4AMen.initReg(m_cfg, RO, 0, 1, 31, 14, "Value4AMen"); m_fieldMap["Value4AMen"] = &AMACv2RegMap::Value4AMen;
+  Ch12Value.initReg(m_cfg, RO, 0, 10, 0, 14, "Ch12Value"); m_fieldMap["Ch12Value"] = &AMACv2RegMap::Ch12Value;
+  Ch13Value.initReg(m_cfg, RO, 0, 10, 10, 14, "Ch13Value"); m_fieldMap["Ch13Value"] = &AMACv2RegMap::Ch13Value;
+  Ch14Value.initReg(m_cfg, RO, 0, 10, 20, 14, "Ch14Value"); m_fieldMap["Ch14Value"] = &AMACv2RegMap::Ch14Value;
   // 15 - Value5
-  Value5AMen.initReg(m_cfg, RO, 0, 1, 31, 15, "Value5AMen"); m_fieldMap["Value5AMen"] = &AMACv2Reg::Value5AMen;
-  Ch15Value.initReg(m_cfg, RO, 0, 10, 0, 15, "Ch15Value"); m_fieldMap["Ch15Value"] = &AMACv2Reg::Ch15Value;
+  Value5AMen.initReg(m_cfg, RO, 0, 1, 31, 15, "Value5AMen"); m_fieldMap["Value5AMen"] = &AMACv2RegMap::Value5AMen;
+  Ch15Value.initReg(m_cfg, RO, 0, 10, 0, 15, "Ch15Value"); m_fieldMap["Ch15Value"] = &AMACv2RegMap::Ch15Value;
   // 31 - SerNum
-  PadID.initReg(m_cfg, RO, 0, 5, 24, 31, "PadID"); m_fieldMap["PadID"] = &AMACv2Reg::PadID;
-  SerNum.initReg(m_cfg, RO, 0, 16, 0, 31, "SerNum"); m_fieldMap["SerNum"] = &AMACv2Reg::SerNum;
+  PadID.initReg(m_cfg, RO, 0, 5, 24, 31, "PadID"); m_fieldMap["PadID"] = &AMACv2RegMap::PadID;
+  SerNum.initReg(m_cfg, RO, 0, 16, 0, 31, "SerNum"); m_fieldMap["SerNum"] = &AMACv2RegMap::SerNum;
   // 32 - FlagResets
-  FlagResetWRN.initReg(m_cfg, WO, 0, 1, 5, 32, "FlagResetWRN"); m_fieldMap["FlagResetWRN"] = &AMACv2Reg::FlagResetWRN;
-  FlagResetDCDC.initReg(m_cfg, WO, 0, 1, 4, 32, "FlagResetDCDC"); m_fieldMap["FlagResetDCDC"] = &AMACv2Reg::FlagResetDCDC;
-  FlagResetHV2.initReg(m_cfg, WO, 0, 1, 3, 32, "FlagResetHV2"); m_fieldMap["FlagResetHV2"] = &AMACv2Reg::FlagResetHV2;
-  FlagResetHV0.initReg(m_cfg, WO, 0, 1, 2, 32, "FlagResetHV0"); m_fieldMap["FlagResetHV0"] = &AMACv2Reg::FlagResetHV0;
-  FlagResetXLDO.initReg(m_cfg, WO, 0, 1, 1, 32, "FlagResetXLDO"); m_fieldMap["FlagResetXLDO"] = &AMACv2Reg::FlagResetXLDO;
-  FlagResetYLDO.initReg(m_cfg, WO, 0, 1, 0, 32, "FlagResetYLDO"); m_fieldMap["FlagResetYLDO"] = &AMACv2Reg::FlagResetYLDO;
+  FlagResetWRN.initReg(m_cfg, WO, 0, 1, 5, 32, "FlagResetWRN"); m_fieldMap["FlagResetWRN"] = &AMACv2RegMap::FlagResetWRN;
+  FlagResetDCDC.initReg(m_cfg, WO, 0, 1, 4, 32, "FlagResetDCDC"); m_fieldMap["FlagResetDCDC"] = &AMACv2RegMap::FlagResetDCDC;
+  FlagResetHV2.initReg(m_cfg, WO, 0, 1, 3, 32, "FlagResetHV2"); m_fieldMap["FlagResetHV2"] = &AMACv2RegMap::FlagResetHV2;
+  FlagResetHV0.initReg(m_cfg, WO, 0, 1, 2, 32, "FlagResetHV0"); m_fieldMap["FlagResetHV0"] = &AMACv2RegMap::FlagResetHV0;
+  FlagResetXLDO.initReg(m_cfg, WO, 0, 1, 1, 32, "FlagResetXLDO"); m_fieldMap["FlagResetXLDO"] = &AMACv2RegMap::FlagResetXLDO;
+  FlagResetYLDO.initReg(m_cfg, WO, 0, 1, 0, 32, "FlagResetYLDO"); m_fieldMap["FlagResetYLDO"] = &AMACv2RegMap::FlagResetYLDO;
   // 33 - LogicReset
-  LogicReset.initReg(m_cfg, WO, 0, 32, 0, 33, "LogicReset"); m_fieldMap["LogicReset"] = &AMACv2Reg::LogicReset;
+  LogicReset.initReg(m_cfg, WO, 0, 32, 0, 33, "LogicReset"); m_fieldMap["LogicReset"] = &AMACv2RegMap::LogicReset;
   // 34 - HardReset
-  HardReset.initReg(m_cfg, WO, 0, 32, 0, 34, "HardReset"); m_fieldMap["HardReset"] = &AMACv2Reg::HardReset;
+  HardReset.initReg(m_cfg, WO, 0, 32, 0, 34, "HardReset"); m_fieldMap["HardReset"] = &AMACv2RegMap::HardReset;
   // 40 - CntSet
-  CntSetHV3frq.initReg(m_cfg, RW, 3, 2, 29, 40, "CntSetHV3frq"); m_fieldMap["CntSetHV3frq"] = &AMACv2Reg::CntSetHV3frq;
-  CntSetHV3en.initReg(m_cfg, RW, 0, 1, 28, 40, "CntSetHV3en"); m_fieldMap["CntSetHV3en"] = &AMACv2Reg::CntSetHV3en;
-  CntSetHV2frq.initReg(m_cfg, RW, 3, 2, 25, 40, "CntSetHV2frq"); m_fieldMap["CntSetHV2frq"] = &AMACv2Reg::CntSetHV2frq;
-  CntSetHV2en.initReg(m_cfg, RW, 0, 1, 24, 40, "CntSetHV2en"); m_fieldMap["CntSetHV2en"] = &AMACv2Reg::CntSetHV2en;
-  CntSetHV1frq.initReg(m_cfg, RW, 3, 2, 21, 40, "CntSetHV1frq"); m_fieldMap["CntSetHV1frq"] = &AMACv2Reg::CntSetHV1frq;
-  CntSetHV1en.initReg(m_cfg, RW, 0, 1, 20, 40, "CntSetHV1en"); m_fieldMap["CntSetHV1en"] = &AMACv2Reg::CntSetHV1en;
-  CntSetHV0frq.initReg(m_cfg, RW, 3, 2, 17, 40, "CntSetHV0frq"); m_fieldMap["CntSetHV0frq"] = &AMACv2Reg::CntSetHV0frq;
-  CntSetHV0en.initReg(m_cfg, RW, 0, 1, 16, 40, "CntSetHV0en"); m_fieldMap["CntSetHV0en"] = &AMACv2Reg::CntSetHV0en;
-  CntSetHyLDO2en.initReg(m_cfg, RW, 0, 1, 14, 40, "CntSetHyLDO2en"); m_fieldMap["CntSetHyLDO2en"] = &AMACv2Reg::CntSetHyLDO2en;
-  CntSetHyLDO1en.initReg(m_cfg, RW, 0, 1, 13, 40, "CntSetHyLDO1en"); m_fieldMap["CntSetHyLDO1en"] = &AMACv2Reg::CntSetHyLDO1en;
-  CntSetHyLDO0en.initReg(m_cfg, RW, 0, 1, 12, 40, "CntSetHyLDO0en"); m_fieldMap["CntSetHyLDO0en"] = &AMACv2Reg::CntSetHyLDO0en;
-  CntSetHxLDO2en.initReg(m_cfg, RW, 0, 1, 10, 40, "CntSetHxLDO2en"); m_fieldMap["CntSetHxLDO2en"] = &AMACv2Reg::CntSetHxLDO2en;
-  CntSetHxLDO1en.initReg(m_cfg, RW, 0, 1, 9, 40, "CntSetHxLDO1en"); m_fieldMap["CntSetHxLDO1en"] = &AMACv2Reg::CntSetHxLDO1en;
-  CntSetHxLDO0en.initReg(m_cfg, RW, 0, 1, 8, 40, "CntSetHxLDO0en"); m_fieldMap["CntSetHxLDO0en"] = &AMACv2Reg::CntSetHxLDO0en;
-  CntSetWARN.initReg(m_cfg, RW, 0, 1, 4, 40, "CntSetWARN"); m_fieldMap["CntSetWARN"] = &AMACv2Reg::CntSetWARN;
+  CntSetHV3frq.initReg(m_cfg, RW, 3, 2, 29, 40, "CntSetHV3frq"); m_fieldMap["CntSetHV3frq"] = &AMACv2RegMap::CntSetHV3frq;
+  CntSetHV3en.initReg(m_cfg, RW, 0, 1, 28, 40, "CntSetHV3en"); m_fieldMap["CntSetHV3en"] = &AMACv2RegMap::CntSetHV3en;
+  CntSetHV2frq.initReg(m_cfg, RW, 3, 2, 25, 40, "CntSetHV2frq"); m_fieldMap["CntSetHV2frq"] = &AMACv2RegMap::CntSetHV2frq;
+  CntSetHV2en.initReg(m_cfg, RW, 0, 1, 24, 40, "CntSetHV2en"); m_fieldMap["CntSetHV2en"] = &AMACv2RegMap::CntSetHV2en;
+  CntSetHV1frq.initReg(m_cfg, RW, 3, 2, 21, 40, "CntSetHV1frq"); m_fieldMap["CntSetHV1frq"] = &AMACv2RegMap::CntSetHV1frq;
+  CntSetHV1en.initReg(m_cfg, RW, 0, 1, 20, 40, "CntSetHV1en"); m_fieldMap["CntSetHV1en"] = &AMACv2RegMap::CntSetHV1en;
+  CntSetHV0frq.initReg(m_cfg, RW, 3, 2, 17, 40, "CntSetHV0frq"); m_fieldMap["CntSetHV0frq"] = &AMACv2RegMap::CntSetHV0frq;
+  CntSetHV0en.initReg(m_cfg, RW, 0, 1, 16, 40, "CntSetHV0en"); m_fieldMap["CntSetHV0en"] = &AMACv2RegMap::CntSetHV0en;
+  CntSetHyLDO2en.initReg(m_cfg, RW, 0, 1, 14, 40, "CntSetHyLDO2en"); m_fieldMap["CntSetHyLDO2en"] = &AMACv2RegMap::CntSetHyLDO2en;
+  CntSetHyLDO1en.initReg(m_cfg, RW, 0, 1, 13, 40, "CntSetHyLDO1en"); m_fieldMap["CntSetHyLDO1en"] = &AMACv2RegMap::CntSetHyLDO1en;
+  CntSetHyLDO0en.initReg(m_cfg, RW, 0, 1, 12, 40, "CntSetHyLDO0en"); m_fieldMap["CntSetHyLDO0en"] = &AMACv2RegMap::CntSetHyLDO0en;
+  CntSetHxLDO2en.initReg(m_cfg, RW, 0, 1, 10, 40, "CntSetHxLDO2en"); m_fieldMap["CntSetHxLDO2en"] = &AMACv2RegMap::CntSetHxLDO2en;
+  CntSetHxLDO1en.initReg(m_cfg, RW, 0, 1, 9, 40, "CntSetHxLDO1en"); m_fieldMap["CntSetHxLDO1en"] = &AMACv2RegMap::CntSetHxLDO1en;
+  CntSetHxLDO0en.initReg(m_cfg, RW, 0, 1, 8, 40, "CntSetHxLDO0en"); m_fieldMap["CntSetHxLDO0en"] = &AMACv2RegMap::CntSetHxLDO0en;
+  CntSetWARN.initReg(m_cfg, RW, 0, 1, 4, 40, "CntSetWARN"); m_fieldMap["CntSetWARN"] = &AMACv2RegMap::CntSetWARN;
   // 41 - CntSetC
-  CntSetCHV3frq.initReg(m_cfg, RW, 3, 2, 29, 41, "CntSetCHV3frq"); m_fieldMap["CntSetCHV3frq"] = &AMACv2Reg::CntSetCHV3frq;
-  CntSetCHV3en.initReg(m_cfg, RW, 0, 1, 28, 41, "CntSetCHV3en"); m_fieldMap["CntSetCHV3en"] = &AMACv2Reg::CntSetCHV3en;
-  CntSetCHV2frq.initReg(m_cfg, RW, 3, 2, 25, 41, "CntSetCHV2frq"); m_fieldMap["CntSetCHV2frq"] = &AMACv2Reg::CntSetCHV2frq;
-  CntSetCHV2en.initReg(m_cfg, RW, 0, 1, 24, 41, "CntSetCHV2en"); m_fieldMap["CntSetCHV2en"] = &AMACv2Reg::CntSetCHV2en;
-  CntSetCHV1frq.initReg(m_cfg, RW, 3, 2, 21, 41, "CntSetCHV1frq"); m_fieldMap["CntSetCHV1frq"] = &AMACv2Reg::CntSetCHV1frq;
-  CntSetCHV1en.initReg(m_cfg, RW, 0, 1, 20, 41, "CntSetCHV1en"); m_fieldMap["CntSetCHV1en"] = &AMACv2Reg::CntSetCHV1en;
-  CntSetCHV0frq.initReg(m_cfg, RW, 3, 2, 17, 41, "CntSetCHV0frq"); m_fieldMap["CntSetCHV0frq"] = &AMACv2Reg::CntSetCHV0frq;
-  CntSetCHV0en.initReg(m_cfg, RW, 0, 1, 16, 41, "CntSetCHV0en"); m_fieldMap["CntSetCHV0en"] = &AMACv2Reg::CntSetCHV0en;
-  CntSetCHyLDO2en.initReg(m_cfg, RW, 0, 1, 14, 41, "CntSetCHyLDO2en"); m_fieldMap["CntSetCHyLDO2en"] = &AMACv2Reg::CntSetCHyLDO2en;
-  CntSetCHyLDO1en.initReg(m_cfg, RW, 0, 1, 13, 41, "CntSetCHyLDO1en"); m_fieldMap["CntSetCHyLDO1en"] = &AMACv2Reg::CntSetCHyLDO1en;
-  CntSetCHyLDO0en.initReg(m_cfg, RW, 0, 1, 12, 41, "CntSetCHyLDO0en"); m_fieldMap["CntSetCHyLDO0en"] = &AMACv2Reg::CntSetCHyLDO0en;
-  CntSetCHxLDO2en.initReg(m_cfg, RW, 0, 1, 10, 41, "CntSetCHxLDO2en"); m_fieldMap["CntSetCHxLDO2en"] = &AMACv2Reg::CntSetCHxLDO2en;
-  CntSetCHxLDO1en.initReg(m_cfg, RW, 0, 1, 9, 41, "CntSetCHxLDO1en"); m_fieldMap["CntSetCHxLDO1en"] = &AMACv2Reg::CntSetCHxLDO1en;
-  CntSetCHxLDO0en.initReg(m_cfg, RW, 0, 1, 8, 41, "CntSetCHxLDO0en"); m_fieldMap["CntSetCHxLDO0en"] = &AMACv2Reg::CntSetCHxLDO0en;
-  CntSetCWARN.initReg(m_cfg, RW, 0, 1, 4, 41, "CntSetCWARN"); m_fieldMap["CntSetCWARN"] = &AMACv2Reg::CntSetCWARN;
+  CntSetCHV3frq.initReg(m_cfg, RW, 3, 2, 29, 41, "CntSetCHV3frq"); m_fieldMap["CntSetCHV3frq"] = &AMACv2RegMap::CntSetCHV3frq;
+  CntSetCHV3en.initReg(m_cfg, RW, 0, 1, 28, 41, "CntSetCHV3en"); m_fieldMap["CntSetCHV3en"] = &AMACv2RegMap::CntSetCHV3en;
+  CntSetCHV2frq.initReg(m_cfg, RW, 3, 2, 25, 41, "CntSetCHV2frq"); m_fieldMap["CntSetCHV2frq"] = &AMACv2RegMap::CntSetCHV2frq;
+  CntSetCHV2en.initReg(m_cfg, RW, 0, 1, 24, 41, "CntSetCHV2en"); m_fieldMap["CntSetCHV2en"] = &AMACv2RegMap::CntSetCHV2en;
+  CntSetCHV1frq.initReg(m_cfg, RW, 3, 2, 21, 41, "CntSetCHV1frq"); m_fieldMap["CntSetCHV1frq"] = &AMACv2RegMap::CntSetCHV1frq;
+  CntSetCHV1en.initReg(m_cfg, RW, 0, 1, 20, 41, "CntSetCHV1en"); m_fieldMap["CntSetCHV1en"] = &AMACv2RegMap::CntSetCHV1en;
+  CntSetCHV0frq.initReg(m_cfg, RW, 3, 2, 17, 41, "CntSetCHV0frq"); m_fieldMap["CntSetCHV0frq"] = &AMACv2RegMap::CntSetCHV0frq;
+  CntSetCHV0en.initReg(m_cfg, RW, 0, 1, 16, 41, "CntSetCHV0en"); m_fieldMap["CntSetCHV0en"] = &AMACv2RegMap::CntSetCHV0en;
+  CntSetCHyLDO2en.initReg(m_cfg, RW, 0, 1, 14, 41, "CntSetCHyLDO2en"); m_fieldMap["CntSetCHyLDO2en"] = &AMACv2RegMap::CntSetCHyLDO2en;
+  CntSetCHyLDO1en.initReg(m_cfg, RW, 0, 1, 13, 41, "CntSetCHyLDO1en"); m_fieldMap["CntSetCHyLDO1en"] = &AMACv2RegMap::CntSetCHyLDO1en;
+  CntSetCHyLDO0en.initReg(m_cfg, RW, 0, 1, 12, 41, "CntSetCHyLDO0en"); m_fieldMap["CntSetCHyLDO0en"] = &AMACv2RegMap::CntSetCHyLDO0en;
+  CntSetCHxLDO2en.initReg(m_cfg, RW, 0, 1, 10, 41, "CntSetCHxLDO2en"); m_fieldMap["CntSetCHxLDO2en"] = &AMACv2RegMap::CntSetCHxLDO2en;
+  CntSetCHxLDO1en.initReg(m_cfg, RW, 0, 1, 9, 41, "CntSetCHxLDO1en"); m_fieldMap["CntSetCHxLDO1en"] = &AMACv2RegMap::CntSetCHxLDO1en;
+  CntSetCHxLDO0en.initReg(m_cfg, RW, 0, 1, 8, 41, "CntSetCHxLDO0en"); m_fieldMap["CntSetCHxLDO0en"] = &AMACv2RegMap::CntSetCHxLDO0en;
+  CntSetCWARN.initReg(m_cfg, RW, 0, 1, 4, 41, "CntSetCWARN"); m_fieldMap["CntSetCWARN"] = &AMACv2RegMap::CntSetCWARN;
   // 42 - DCDCen
-  DCDCAdj.initReg(m_cfg, RW, 0, 2, 4, 42, "DCDCAdj"); m_fieldMap["DCDCAdj"] = &AMACv2Reg::DCDCAdj;
-  DCDCen.initReg(m_cfg, RW, 0, 1, 0, 42, "DCDCen"); m_fieldMap["DCDCen"] = &AMACv2Reg::DCDCen;
+  DCDCAdj.initReg(m_cfg, RW, 0, 2, 4, 42, "DCDCAdj"); m_fieldMap["DCDCAdj"] = &AMACv2RegMap::DCDCAdj;
+  DCDCen.initReg(m_cfg, RW, 0, 1, 0, 42, "DCDCen"); m_fieldMap["DCDCen"] = &AMACv2RegMap::DCDCen;
   // 43 - DCDCenC
-  DCDCAdjC.initReg(m_cfg, RW, 0, 2, 4, 43, "DCDCAdjC"); m_fieldMap["DCDCAdjC"] = &AMACv2Reg::DCDCAdjC;
-  DCDCenC.initReg(m_cfg, RW, 0, 1, 0, 43, "DCDCenC"); m_fieldMap["DCDCenC"] = &AMACv2Reg::DCDCenC;
+  DCDCAdjC.initReg(m_cfg, RW, 0, 2, 4, 43, "DCDCAdjC"); m_fieldMap["DCDCAdjC"] = &AMACv2RegMap::DCDCAdjC;
+  DCDCenC.initReg(m_cfg, RW, 0, 1, 0, 43, "DCDCenC"); m_fieldMap["DCDCenC"] = &AMACv2RegMap::DCDCenC;
   // 44 - Ilock
-  IlockWRN.initReg(m_cfg, RW, 0, 1, 5, 44, "IlockWRN"); m_fieldMap["IlockWRN"] = &AMACv2Reg::IlockWRN;
-  IlockDCDC.initReg(m_cfg, RW, 0, 1, 4, 44, "IlockDCDC"); m_fieldMap["IlockDCDC"] = &AMACv2Reg::IlockDCDC;
-  IlockHV2.initReg(m_cfg, RW, 0, 1, 3, 44, "IlockHV2"); m_fieldMap["IlockHV2"] = &AMACv2Reg::IlockHV2;
-  IlockHV2.initReg(m_cfg, RW, 0, 1, 2, 44, "IlockHV2"); m_fieldMap["IlockHV2"] = &AMACv2Reg::IlockHV2;
-  IlockHy.initReg(m_cfg, RW, 0, 1, 1, 44, "IlockHy"); m_fieldMap["IlockHy"] = &AMACv2Reg::IlockHy;
-  IlockHx.initReg(m_cfg, RW, 0, 1, 0, 44, "IlockHx"); m_fieldMap["IlockHx"] = &AMACv2Reg::IlockHx;
+  IlockWRN.initReg(m_cfg, RW, 0, 1, 5, 44, "IlockWRN"); m_fieldMap["IlockWRN"] = &AMACv2RegMap::IlockWRN;
+  IlockDCDC.initReg(m_cfg, RW, 0, 1, 4, 44, "IlockDCDC"); m_fieldMap["IlockDCDC"] = &AMACv2RegMap::IlockDCDC;
+  IlockHV2.initReg(m_cfg, RW, 0, 1, 3, 44, "IlockHV2"); m_fieldMap["IlockHV2"] = &AMACv2RegMap::IlockHV2;
+  IlockHV2.initReg(m_cfg, RW, 0, 1, 2, 44, "IlockHV2"); m_fieldMap["IlockHV2"] = &AMACv2RegMap::IlockHV2;
+  IlockHy.initReg(m_cfg, RW, 0, 1, 1, 44, "IlockHy"); m_fieldMap["IlockHy"] = &AMACv2RegMap::IlockHy;
+  IlockHx.initReg(m_cfg, RW, 0, 1, 0, 44, "IlockHx"); m_fieldMap["IlockHx"] = &AMACv2RegMap::IlockHx;
   // 45 - IlockC
-  IlockCWRN.initReg(m_cfg, RW, 0, 1, 5, 45, "IlockCWRN"); m_fieldMap["IlockCWRN"] = &AMACv2Reg::IlockCWRN;
-  IlockCDCDC.initReg(m_cfg, RW, 0, 1, 4, 45, "IlockCDCDC"); m_fieldMap["IlockCDCDC"] = &AMACv2Reg::IlockCDCDC;
-  IlockCHV2.initReg(m_cfg, RW, 0, 1, 3, 45, "IlockCHV2"); m_fieldMap["IlockCHV2"] = &AMACv2Reg::IlockCHV2;
-  IlockCHV2.initReg(m_cfg, RW, 0, 1, 2, 45, "IlockCHV2"); m_fieldMap["IlockCHV2"] = &AMACv2Reg::IlockCHV2;
-  IlockCHy.initReg(m_cfg, RW, 0, 1, 1, 45, "IlockCHy"); m_fieldMap["IlockCHy"] = &AMACv2Reg::IlockCHy;
-  IlockCHx.initReg(m_cfg, RW, 0, 1, 0, 45, "IlockCHx"); m_fieldMap["IlockCHx"] = &AMACv2Reg::IlockCHx;
+  IlockCWRN.initReg(m_cfg, RW, 0, 1, 5, 45, "IlockCWRN"); m_fieldMap["IlockCWRN"] = &AMACv2RegMap::IlockCWRN;
+  IlockCDCDC.initReg(m_cfg, RW, 0, 1, 4, 45, "IlockCDCDC"); m_fieldMap["IlockCDCDC"] = &AMACv2RegMap::IlockCDCDC;
+  IlockCHV2.initReg(m_cfg, RW, 0, 1, 3, 45, "IlockCHV2"); m_fieldMap["IlockCHV2"] = &AMACv2RegMap::IlockCHV2;
+  IlockCHV2.initReg(m_cfg, RW, 0, 1, 2, 45, "IlockCHV2"); m_fieldMap["IlockCHV2"] = &AMACv2RegMap::IlockCHV2;
+  IlockCHy.initReg(m_cfg, RW, 0, 1, 1, 45, "IlockCHy"); m_fieldMap["IlockCHy"] = &AMACv2RegMap::IlockCHy;
+  IlockCHx.initReg(m_cfg, RW, 0, 1, 0, 45, "IlockCHx"); m_fieldMap["IlockCHx"] = &AMACv2RegMap::IlockCHx;
   // 46 - RstCnt
-  RstCntHyHCCresetB.initReg(m_cfg, RW, 0, 1, 16, 46, "RstCntHyHCCresetB"); m_fieldMap["RstCntHyHCCresetB"] = &AMACv2Reg::RstCntHyHCCresetB;
-  RstCntHxHCCresetB.initReg(m_cfg, RW, 0, 1, 8, 46, "RstCntHxHCCresetB"); m_fieldMap["RstCntHxHCCresetB"] = &AMACv2Reg::RstCntHxHCCresetB;
-  RstCntOF.initReg(m_cfg, RW, 0, 1, 0, 46, "RstCntOF"); m_fieldMap["RstCntOF"] = &AMACv2Reg::RstCntOF;
+  RstCntHyHCCresetB.initReg(m_cfg, RW, 0, 1, 16, 46, "RstCntHyHCCresetB"); m_fieldMap["RstCntHyHCCresetB"] = &AMACv2RegMap::RstCntHyHCCresetB;
+  RstCntHxHCCresetB.initReg(m_cfg, RW, 0, 1, 8, 46, "RstCntHxHCCresetB"); m_fieldMap["RstCntHxHCCresetB"] = &AMACv2RegMap::RstCntHxHCCresetB;
+  RstCntOF.initReg(m_cfg, RW, 0, 1, 0, 46, "RstCntOF"); m_fieldMap["RstCntOF"] = &AMACv2RegMap::RstCntOF;
   // 47 - RstCntC
-  RstCntCHyHCCresetB.initReg(m_cfg, RW, 0, 1, 16, 47, "RstCntCHyHCCresetB"); m_fieldMap["RstCntCHyHCCresetB"] = &AMACv2Reg::RstCntCHyHCCresetB;
-  RstCntCHxHCCresetB.initReg(m_cfg, RW, 0, 1, 8, 47, "RstCntCHxHCCresetB"); m_fieldMap["RstCntCHxHCCresetB"] = &AMACv2Reg::RstCntCHxHCCresetB;
-  RstCntCOF.initReg(m_cfg, RW, 0, 1, 0, 47, "RstCntCOF"); m_fieldMap["RstCntCOF"] = &AMACv2Reg::RstCntCOF;
+  RstCntCHyHCCresetB.initReg(m_cfg, RW, 0, 1, 16, 47, "RstCntCHyHCCresetB"); m_fieldMap["RstCntCHyHCCresetB"] = &AMACv2RegMap::RstCntCHyHCCresetB;
+  RstCntCHxHCCresetB.initReg(m_cfg, RW, 0, 1, 8, 47, "RstCntCHxHCCresetB"); m_fieldMap["RstCntCHxHCCresetB"] = &AMACv2RegMap::RstCntCHxHCCresetB;
+  RstCntCOF.initReg(m_cfg, RW, 0, 1, 0, 47, "RstCntCOF"); m_fieldMap["RstCntCOF"] = &AMACv2RegMap::RstCntCOF;
   // 48 - AMen
-  AMzeroCalib.initReg(m_cfg, RW, 0, 1, 8, 48, "AMzeroCalib"); m_fieldMap["AMzeroCalib"] = &AMACv2Reg::AMzeroCalib;
-  AMen.initReg(m_cfg, RW, 1, 1, 0, 48, "AMen"); m_fieldMap["AMen"] = &AMACv2Reg::AMen;
+  AMzeroCalib.initReg(m_cfg, RW, 0, 1, 8, 48, "AMzeroCalib"); m_fieldMap["AMzeroCalib"] = &AMACv2RegMap::AMzeroCalib;
+  AMen.initReg(m_cfg, RW, 1, 1, 0, 48, "AMen"); m_fieldMap["AMen"] = &AMACv2RegMap::AMen;
   // 49 - AMenC
-  AMzeroCalibC.initReg(m_cfg, RW, 0, 1, 8, 49, "AMzeroCalibC"); m_fieldMap["AMzeroCalibC"] = &AMACv2Reg::AMzeroCalibC;
-  AMenC.initReg(m_cfg, RW, 1, 1, 0, 49, "AMenC"); m_fieldMap["AMenC"] = &AMACv2Reg::AMenC;
+  AMzeroCalibC.initReg(m_cfg, RW, 0, 1, 8, 49, "AMzeroCalibC"); m_fieldMap["AMzeroCalibC"] = &AMACv2RegMap::AMzeroCalibC;
+  AMenC.initReg(m_cfg, RW, 1, 1, 0, 49, "AMenC"); m_fieldMap["AMenC"] = &AMACv2RegMap::AMenC;
   // 50 - AMpwr
-  ReqDCDCPGOOD.initReg(m_cfg, RW, 1, 1, 8, 50, "ReqDCDCPGOOD"); m_fieldMap["ReqDCDCPGOOD"] = &AMACv2Reg::ReqDCDCPGOOD;
-  DCDCenToPwrAMAC.initReg(m_cfg, RW, 0, 1, 0, 50, "DCDCenToPwrAMAC"); m_fieldMap["DCDCenToPwrAMAC"] = &AMACv2Reg::DCDCenToPwrAMAC;
+  ReqDCDCPGOOD.initReg(m_cfg, RW, 1, 1, 8, 50, "ReqDCDCPGOOD"); m_fieldMap["ReqDCDCPGOOD"] = &AMACv2RegMap::ReqDCDCPGOOD;
+  DCDCenToPwrAMAC.initReg(m_cfg, RW, 0, 1, 0, 50, "DCDCenToPwrAMAC"); m_fieldMap["DCDCenToPwrAMAC"] = &AMACv2RegMap::DCDCenToPwrAMAC;
   // 51 - AMpwrC
-  ReqDCDCPGOODC.initReg(m_cfg, RW, 1, 1, 8, 51, "ReqDCDCPGOODC"); m_fieldMap["ReqDCDCPGOODC"] = &AMACv2Reg::ReqDCDCPGOODC;
-  DCDCenToPwrAMACC.initReg(m_cfg, RW, 0, 1, 0, 51, "DCDCenToPwrAMACC"); m_fieldMap["DCDCenToPwrAMACC"] = &AMACv2Reg::DCDCenToPwrAMACC;
+  ReqDCDCPGOODC.initReg(m_cfg, RW, 1, 1, 8, 51, "ReqDCDCPGOODC"); m_fieldMap["ReqDCDCPGOODC"] = &AMACv2RegMap::ReqDCDCPGOODC;
+  DCDCenToPwrAMACC.initReg(m_cfg, RW, 0, 1, 0, 51, "DCDCenToPwrAMACC"); m_fieldMap["DCDCenToPwrAMACC"] = &AMACv2RegMap::DCDCenToPwrAMACC;
   // 52 - BgCnt
-  AMbgen .initReg(m_cfg, RW, 0, 1, 15, 52, "AMbgen" ); m_fieldMap["AMbgen" ] = &AMACv2Reg::AMbgen;
-  AMbg   .initReg(m_cfg, RW, 0, 5,  8, 52, "AMbg"   ); m_fieldMap["AMbg"   ] = &AMACv2Reg::AMbg;
-  VDDbgen.initReg(m_cfg, RW, 0, 1,  7, 52, "VDDbgen"); m_fieldMap["VDDbgen"] = &AMACv2Reg::VDDbgen;
-  VDDbg  .initReg(m_cfg, RW, 0, 5,  0, 52, "VDDbg"  ); m_fieldMap["VDDbg"  ] = &AMACv2Reg::VDDbg;
+  AMbgen .initReg(m_cfg, RW, 0, 1, 15, 52, "AMbgen" ); m_fieldMap["AMbgen" ] = &AMACv2RegMap::AMbgen;
+  AMbg   .initReg(m_cfg, RW, 0, 5,  8, 52, "AMbg"   ); m_fieldMap["AMbg"   ] = &AMACv2RegMap::AMbg;
+  VDDbgen.initReg(m_cfg, RW, 0, 1,  7, 52, "VDDbgen"); m_fieldMap["VDDbgen"] = &AMACv2RegMap::VDDbgen;
+  VDDbg  .initReg(m_cfg, RW, 0, 5,  0, 52, "VDDbg"  ); m_fieldMap["VDDbg"  ] = &AMACv2RegMap::VDDbg;
   // 53 - AMcnt
-  AMintCalib.initReg(m_cfg, RW, 0, 4, 24, 53, "AMintCalib"); m_fieldMap["AMintCalib"] = &AMACv2Reg::AMintCalib;
-  Ch13Mux.initReg(m_cfg, RW, 0, 2, 20, 53, "Ch13Mux"); m_fieldMap["Ch13Mux"] = &AMACv2Reg::Ch13Mux;
-  Ch12Mux.initReg(m_cfg, RW, 0, 2, 16, 53, "Ch12Mux"); m_fieldMap["Ch12Mux"] = &AMACv2Reg::Ch12Mux;
-  Ch5Mux.initReg(m_cfg, RW, 0, 2, 13, 53, "Ch5Mux"); m_fieldMap["Ch5Mux"] = &AMACv2Reg::Ch5Mux;
-  Ch4Mux.initReg(m_cfg, RW, 0, 2, 8, 53, "Ch4Mux"); m_fieldMap["Ch4Mux"] = &AMACv2Reg::Ch4Mux;
-  Ch3Mux.initReg(m_cfg, RW, 0, 2, 4, 53, "Ch3Mux"); m_fieldMap["Ch3Mux"] = &AMACv2Reg::Ch3Mux;
+  AMintCalib.initReg(m_cfg, RW, 0, 4, 24, 53, "AMintCalib"); m_fieldMap["AMintCalib"] = &AMACv2RegMap::AMintCalib;
+  Ch13Mux.initReg(m_cfg, RW, 0, 2, 20, 53, "Ch13Mux"); m_fieldMap["Ch13Mux"] = &AMACv2RegMap::Ch13Mux;
+  Ch12Mux.initReg(m_cfg, RW, 0, 2, 16, 53, "Ch12Mux"); m_fieldMap["Ch12Mux"] = &AMACv2RegMap::Ch12Mux;
+  Ch5Mux.initReg(m_cfg, RW, 0, 2, 13, 53, "Ch5Mux"); m_fieldMap["Ch5Mux"] = &AMACv2RegMap::Ch5Mux;
+  Ch4Mux.initReg(m_cfg, RW, 0, 2, 8, 53, "Ch4Mux"); m_fieldMap["Ch4Mux"] = &AMACv2RegMap::Ch4Mux;
+  Ch3Mux.initReg(m_cfg, RW, 0, 2, 4, 53, "Ch3Mux"); m_fieldMap["Ch3Mux"] = &AMACv2RegMap::Ch3Mux;
   // 54 - Dacs0
-  DACShunty.initReg(m_cfg, RW, 0, 8, 24, 54, "DACShunty"); m_fieldMap["DACShunty"] = &AMACv2Reg::DACShunty;
-  DACShuntx.initReg(m_cfg, RW, 0, 8, 16, 54, "DACShuntx"); m_fieldMap["DACShuntx"] = &AMACv2Reg::DACShuntx;
-  DACCALy.initReg(m_cfg, RW, 0, 8, 8, 54, "DACCALy"); m_fieldMap["DACCALy"] = &AMACv2Reg::DACCALy;
-  DACCalx.initReg(m_cfg, RW, 0, 8, 0, 54, "DACCalx"); m_fieldMap["DACCalx"] = &AMACv2Reg::DACCalx;
+  DACShunty.initReg(m_cfg, RW, 0, 8, 24, 54, "DACShunty"); m_fieldMap["DACShunty"] = &AMACv2RegMap::DACShunty;
+  DACShuntx.initReg(m_cfg, RW, 0, 8, 16, 54, "DACShuntx"); m_fieldMap["DACShuntx"] = &AMACv2RegMap::DACShuntx;
+  DACCALy.initReg(m_cfg, RW, 0, 8, 8, 54, "DACCALy"); m_fieldMap["DACCALy"] = &AMACv2RegMap::DACCALy;
+  DACCalx.initReg(m_cfg, RW, 0, 8, 0, 54, "DACCalx"); m_fieldMap["DACCalx"] = &AMACv2RegMap::DACCalx;
   // 55 - DACbias
-  DACbias.initReg(m_cfg, RW, 0xD, 5, 0, 55, "DACbias"); m_fieldMap["DACbias"] = &AMACv2Reg::DACbias;
+  DACbias.initReg(m_cfg, RW, 0xD, 5, 0, 55, "DACbias"); m_fieldMap["DACbias"] = &AMACv2RegMap::DACbias;
   // 56 - AMACcnt
-  HVcurGain .initReg(m_cfg, RW, 0, 4, 16, 56, "HVcurGain" ); m_fieldMap["HVcurGain" ] = &AMACv2Reg::HVcurGain;
-  DRcomMode .initReg(m_cfg, RW, 0, 2, 12, 56, "DRcomMode" ); m_fieldMap["DRcomMode" ] = &AMACv2Reg::DRcomMode;
-  DRcurr    .initReg(m_cfg, RW, 4, 3,  8, 56, "DRcurr"    ); m_fieldMap["DRcurr"    ] = &AMACv2Reg::DRcurr;
-  RingOscFrq.initReg(m_cfg, RW, 4, 3,  0, 56, "RingOscFrq"); m_fieldMap["RingOscFrq"] = &AMACv2Reg::RingOscFrq;
+  HVcurGain .initReg(m_cfg, RW, 0, 4, 16, 56, "HVcurGain" ); m_fieldMap["HVcurGain" ] = &AMACv2RegMap::HVcurGain;
+  DRcomMode .initReg(m_cfg, RW, 0, 2, 12, 56, "DRcomMode" ); m_fieldMap["DRcomMode" ] = &AMACv2RegMap::DRcomMode;
+  DRcurr    .initReg(m_cfg, RW, 4, 3,  8, 56, "DRcurr"    ); m_fieldMap["DRcurr"    ] = &AMACv2RegMap::DRcurr;
+  RingOscFrq.initReg(m_cfg, RW, 4, 3,  0, 56, "RingOscFrq"); m_fieldMap["RingOscFrq"] = &AMACv2RegMap::RingOscFrq;
   // 57 - NTC
-  CTAToffset     .initReg(m_cfg, RW, 0, 4, 20, 57, "CTAToffset"     ); m_fieldMap["CTAToffset"     ] = &AMACv2Reg::CTAToffset;
-  NTCpbCal       .initReg(m_cfg, RW, 1, 1, 19, 57, "NTCpbCal"       ); m_fieldMap["NTCpbCal"       ] = &AMACv2Reg::NTCpbCal;
-  NTCpbSenseRange.initReg(m_cfg, RW, 4, 3, 16, 57, "NTCpbSenseRange"); m_fieldMap["NTCpbSenseRange"] = &AMACv2Reg::NTCpbSenseRange;
-  NTCy0Cal       .initReg(m_cfg, RW, 1, 1, 11, 57, "NTCy0Cal"       ); m_fieldMap["NTCy0Cal"       ] = &AMACv2Reg::NTCy0Cal;
-  NTCy0SenseRange.initReg(m_cfg, RW, 4, 3,  8, 57, "NTCy0SenseRange"); m_fieldMap["NTCy0SenseRange"] = &AMACv2Reg::NTCy0SenseRange;
-  NTCx0Cal       .initReg(m_cfg, RW, 1, 1,  3, 57, "NTCx0Cal"       ); m_fieldMap["NTCx0Cal"       ] = &AMACv2Reg::NTCx0Cal;
-  NTCx0SenseRange.initReg(m_cfg, RW, 4, 3,  0, 57, "NTCx0SenseRange"); m_fieldMap["NTCx0SenseRange"] = &AMACv2Reg::NTCx0SenseRange;
+  CTAToffset     .initReg(m_cfg, RW, 0, 4, 20, 57, "CTAToffset"     ); m_fieldMap["CTAToffset"     ] = &AMACv2RegMap::CTAToffset;
+  NTCpbCal       .initReg(m_cfg, RW, 1, 1, 19, 57, "NTCpbCal"       ); m_fieldMap["NTCpbCal"       ] = &AMACv2RegMap::NTCpbCal;
+  NTCpbSenseRange.initReg(m_cfg, RW, 4, 3, 16, 57, "NTCpbSenseRange"); m_fieldMap["NTCpbSenseRange"] = &AMACv2RegMap::NTCpbSenseRange;
+  NTCy0Cal       .initReg(m_cfg, RW, 1, 1, 11, 57, "NTCy0Cal"       ); m_fieldMap["NTCy0Cal"       ] = &AMACv2RegMap::NTCy0Cal;
+  NTCy0SenseRange.initReg(m_cfg, RW, 4, 3,  8, 57, "NTCy0SenseRange"); m_fieldMap["NTCy0SenseRange"] = &AMACv2RegMap::NTCy0SenseRange;
+  NTCx0Cal       .initReg(m_cfg, RW, 1, 1,  3, 57, "NTCx0Cal"       ); m_fieldMap["NTCx0Cal"       ] = &AMACv2RegMap::NTCx0Cal;
+  NTCx0SenseRange.initReg(m_cfg, RW, 4, 3,  0, 57, "NTCx0SenseRange"); m_fieldMap["NTCx0SenseRange"] = &AMACv2RegMap::NTCx0SenseRange;
   // 58 - LvCurCal
-  DCDCoOffset     .initReg(m_cfg, RW, 4, 4, 20, 58, "DCDCoOffset"     ); m_fieldMap["DCDCoOffset"     ] = &AMACv2Reg::DCDCoOffset;
-  DCDCoZeroReading.initReg(m_cfg, RW, 0, 1, 19, 58, "DCDCoZeroReading"); m_fieldMap["DCDCoZeroReading"] = &AMACv2Reg::DCDCoZeroReading;
-  DCDCoN          .initReg(m_cfg, RW, 0, 1, 17, 58, "DCDCoN"          ); m_fieldMap["DCDCoN"          ] = &AMACv2Reg::DCDCoN;
-  DCDCoP          .initReg(m_cfg, RW, 0, 1, 16, 58, "DCDCoP"          ); m_fieldMap["DCDCoP"          ] = &AMACv2Reg::DCDCoP;
-  DCDCiZeroReading.initReg(m_cfg, RW, 0, 1, 15, 58, "DCDCiZeroReading"); m_fieldMap["DCDCiZeroReading"] = &AMACv2Reg::DCDCiZeroReading;
-  DCDCiRangeSW    .initReg(m_cfg, RW, 1, 1, 12, 58, "DCDCiRangeSW"    ); m_fieldMap["DCDCiRangeSW"    ] = &AMACv2Reg::DCDCiRangeSW;
-  DCDCiOffset     .initReg(m_cfg, RW, 8, 4,  8, 58, "DCDCiOffset"     ); m_fieldMap["DCDCiOffset"     ] = &AMACv2Reg::DCDCiOffset;
-  DCDCiP          .initReg(m_cfg, RW, 0, 3,  4, 58, "DCDCiP"          ); m_fieldMap["DCDCiP"          ] = &AMACv2Reg::DCDCiP;
-  DCDCiN          .initReg(m_cfg, RW, 0, 3,  0, 58, "DCDCiN"          ); m_fieldMap["DCDCiN"          ] = &AMACv2Reg::DCDCiN;
+  DCDCoOffset     .initReg(m_cfg, RW, 4, 4, 20, 58, "DCDCoOffset"     ); m_fieldMap["DCDCoOffset"     ] = &AMACv2RegMap::DCDCoOffset;
+  DCDCoZeroReading.initReg(m_cfg, RW, 0, 1, 19, 58, "DCDCoZeroReading"); m_fieldMap["DCDCoZeroReading"] = &AMACv2RegMap::DCDCoZeroReading;
+  DCDCoN          .initReg(m_cfg, RW, 0, 1, 17, 58, "DCDCoN"          ); m_fieldMap["DCDCoN"          ] = &AMACv2RegMap::DCDCoN;
+  DCDCoP          .initReg(m_cfg, RW, 0, 1, 16, 58, "DCDCoP"          ); m_fieldMap["DCDCoP"          ] = &AMACv2RegMap::DCDCoP;
+  DCDCiZeroReading.initReg(m_cfg, RW, 0, 1, 15, 58, "DCDCiZeroReading"); m_fieldMap["DCDCiZeroReading"] = &AMACv2RegMap::DCDCiZeroReading;
+  DCDCiRangeSW    .initReg(m_cfg, RW, 1, 1, 12, 58, "DCDCiRangeSW"    ); m_fieldMap["DCDCiRangeSW"    ] = &AMACv2RegMap::DCDCiRangeSW;
+  DCDCiOffset     .initReg(m_cfg, RW, 8, 4,  8, 58, "DCDCiOffset"     ); m_fieldMap["DCDCiOffset"     ] = &AMACv2RegMap::DCDCiOffset;
+  DCDCiP          .initReg(m_cfg, RW, 0, 3,  4, 58, "DCDCiP"          ); m_fieldMap["DCDCiP"          ] = &AMACv2RegMap::DCDCiP;
+  DCDCiN          .initReg(m_cfg, RW, 0, 3,  0, 58, "DCDCiN"          ); m_fieldMap["DCDCiN"          ] = &AMACv2RegMap::DCDCiN;
   // 60 - HxICm_cfg
-  HxLAM.initReg(m_cfg, RW, 0, 1, 16, 60, "HxLAM"); m_fieldMap["HxLAM"] = &AMACv2Reg::HxLAM;
-  HxFlagsLatch.initReg(m_cfg, RW, 1, 1, 12, 60, "HxFlagsLatch"); m_fieldMap["HxFlagsLatch"] = &AMACv2Reg::HxFlagsLatch;
-  HxFlagsLogic.initReg(m_cfg, RW, 0, 1, 8, 60, "HxFlagsLogic"); m_fieldMap["HxFlagsLogic"] = &AMACv2Reg::HxFlagsLogic;
-  HxFlagValid.initReg(m_cfg, RW, 0, 1, 4, 60, "HxFlagValid"); m_fieldMap["HxFlagValid"] = &AMACv2Reg::HxFlagsLogic;
-  HxFlagsValidConf.initReg(m_cfg, RW, 0, 2, 0, 60, "HxFlagValid"); m_fieldMap["HxFlagValid"] = &AMACv2Reg::HxFlagsLogic;
+  HxLAM.initReg(m_cfg, RW, 0, 1, 16, 60, "HxLAM"); m_fieldMap["HxLAM"] = &AMACv2RegMap::HxLAM;
+  HxFlagsLatch.initReg(m_cfg, RW, 1, 1, 12, 60, "HxFlagsLatch"); m_fieldMap["HxFlagsLatch"] = &AMACv2RegMap::HxFlagsLatch;
+  HxFlagsLogic.initReg(m_cfg, RW, 0, 1, 8, 60, "HxFlagsLogic"); m_fieldMap["HxFlagsLogic"] = &AMACv2RegMap::HxFlagsLogic;
+  HxFlagValid.initReg(m_cfg, RW, 0, 1, 4, 60, "HxFlagValid"); m_fieldMap["HxFlagValid"] = &AMACv2RegMap::HxFlagsLogic;
+  HxFlagsValidConf.initReg(m_cfg, RW, 0, 2, 0, 60, "HxFlagValid"); m_fieldMap["HxFlagValid"] = &AMACv2RegMap::HxFlagsLogic;
   // 61 - HyICm_cfg
-  HyLAM.initReg(m_cfg, RW, 0, 1, 16, 61, "HyLAM"); m_fieldMap["HyLAM"] = &AMACv2Reg::HyLAM;
-  HyFlagsLatch.initReg(m_cfg, RW, 1, 1, 12, 61, "HyFlagsLatch"); m_fieldMap["HyFlagsLatch"] = &AMACv2Reg::HyFlagsLatch;
-  HyFlagsLogic.initReg(m_cfg, RW, 0, 1, 8, 61, "HyFlagsLogic"); m_fieldMap["HyFlagsLogic"] = &AMACv2Reg::HyFlagsLogic;
-  HyFlagValid.initReg(m_cfg, RW, 0, 1, 4, 61, "HyFlagValid"); m_fieldMap["HyFlagValid"] = &AMACv2Reg::HyFlagsLogic;
-  HyFlagsValidConf.initReg(m_cfg, RW, 0, 2, 0, 61, "HyFlagValid"); m_fieldMap["HyFlagValid"] = &AMACv2Reg::HyFlagsLogic;
+  HyLAM.initReg(m_cfg, RW, 0, 1, 16, 61, "HyLAM"); m_fieldMap["HyLAM"] = &AMACv2RegMap::HyLAM;
+  HyFlagsLatch.initReg(m_cfg, RW, 1, 1, 12, 61, "HyFlagsLatch"); m_fieldMap["HyFlagsLatch"] = &AMACv2RegMap::HyFlagsLatch;
+  HyFlagsLogic.initReg(m_cfg, RW, 0, 1, 8, 61, "HyFlagsLogic"); m_fieldMap["HyFlagsLogic"] = &AMACv2RegMap::HyFlagsLogic;
+  HyFlagValid.initReg(m_cfg, RW, 0, 1, 4, 61, "HyFlagValid"); m_fieldMap["HyFlagValid"] = &AMACv2RegMap::HyFlagsLogic;
+  HyFlagsValidConf.initReg(m_cfg, RW, 0, 2, 0, 61, "HyFlagValid"); m_fieldMap["HyFlagValid"] = &AMACv2RegMap::HyFlagsLogic;
   // 62 - HV0ICm_cfg
-  HV0LAM.initReg(m_cfg, RW, 0, 1, 16, 62, "HV0LAM"); m_fieldMap["HV0LAM"] = &AMACv2Reg::HV0LAM;
-  HV0FlagsLatch.initReg(m_cfg, RW, 1, 1, 12, 62, "HV0FlagsLatch"); m_fieldMap["HV0FlagsLatch"] = &AMACv2Reg::HV0FlagsLatch;
-  HV0FlagsLogic.initReg(m_cfg, RW, 0, 1, 8, 62, "HV0FlagsLogic"); m_fieldMap["HV0FlagsLogic"] = &AMACv2Reg::HV0FlagsLogic;
-  HV0FlagValid.initReg(m_cfg, RW, 0, 1, 4, 62, "HV0FlagValid"); m_fieldMap["HV0FlagValid"] = &AMACv2Reg::HV0FlagsLogic;
-  HV0FlagsValidConf.initReg(m_cfg, RW, 0, 2, 0, 62, "HV0FlagValid"); m_fieldMap["HV0FlagValid"] = &AMACv2Reg::HV0FlagsLogic;
+  HV0LAM.initReg(m_cfg, RW, 0, 1, 16, 62, "HV0LAM"); m_fieldMap["HV0LAM"] = &AMACv2RegMap::HV0LAM;
+  HV0FlagsLatch.initReg(m_cfg, RW, 1, 1, 12, 62, "HV0FlagsLatch"); m_fieldMap["HV0FlagsLatch"] = &AMACv2RegMap::HV0FlagsLatch;
+  HV0FlagsLogic.initReg(m_cfg, RW, 0, 1, 8, 62, "HV0FlagsLogic"); m_fieldMap["HV0FlagsLogic"] = &AMACv2RegMap::HV0FlagsLogic;
+  HV0FlagValid.initReg(m_cfg, RW, 0, 1, 4, 62, "HV0FlagValid"); m_fieldMap["HV0FlagValid"] = &AMACv2RegMap::HV0FlagsLogic;
+  HV0FlagsValidConf.initReg(m_cfg, RW, 0, 2, 0, 62, "HV0FlagValid"); m_fieldMap["HV0FlagValid"] = &AMACv2RegMap::HV0FlagsLogic;
   // 63 - HV2ICm_cfg
-  HV2LAM.initReg(m_cfg, RW, 0, 1, 16, 63, "HV2LAM"); m_fieldMap["HV2LAM"] = &AMACv2Reg::HV2LAM;
-  HV2FlagsLatch.initReg(m_cfg, RW, 1, 1, 12, 63, "HV2FlagsLatch"); m_fieldMap["HV2FlagsLatch"] = &AMACv2Reg::HV2FlagsLatch;
-  HV2FlagsLogic.initReg(m_cfg, RW, 0, 1, 8, 63, "HV2FlagsLogic"); m_fieldMap["HV2FlagsLogic"] = &AMACv2Reg::HV2FlagsLogic;
-  HV2FlagValid.initReg(m_cfg, RW, 0, 1, 4, 63, "HV2FlagValid"); m_fieldMap["HV2FlagValid"] = &AMACv2Reg::HV2FlagsLogic;
-  HV2FlagsValidConf.initReg(m_cfg, RW, 0, 2, 0, 63, "HV2FlagValid"); m_fieldMap["HV2FlagValid"] = &AMACv2Reg::HV2FlagsLogic;
+  HV2LAM.initReg(m_cfg, RW, 0, 1, 16, 63, "HV2LAM"); m_fieldMap["HV2LAM"] = &AMACv2RegMap::HV2LAM;
+  HV2FlagsLatch.initReg(m_cfg, RW, 1, 1, 12, 63, "HV2FlagsLatch"); m_fieldMap["HV2FlagsLatch"] = &AMACv2RegMap::HV2FlagsLatch;
+  HV2FlagsLogic.initReg(m_cfg, RW, 0, 1, 8, 63, "HV2FlagsLogic"); m_fieldMap["HV2FlagsLogic"] = &AMACv2RegMap::HV2FlagsLogic;
+  HV2FlagValid.initReg(m_cfg, RW, 0, 1, 4, 63, "HV2FlagValid"); m_fieldMap["HV2FlagValid"] = &AMACv2RegMap::HV2FlagsLogic;
+  HV2FlagsValidConf.initReg(m_cfg, RW, 0, 2, 0, 63, "HV2FlagValid"); m_fieldMap["HV2FlagValid"] = &AMACv2RegMap::HV2FlagsLogic;
   // 64 - DCDCICm_cfg
-  DCDCLAM.initReg(m_cfg, RW, 0, 1, 16, 64, "DCDCLAM"); m_fieldMap["DCDCLAM"] = &AMACv2Reg::DCDCLAM;
-  DCDCFlagsLatch.initReg(m_cfg, RW, 1, 1, 12, 64, "DCDCFlagsLatch"); m_fieldMap["DCDCFlagsLatch"] = &AMACv2Reg::DCDCFlagsLatch;
-  DCDCFlagsLogic.initReg(m_cfg, RW, 0, 1, 8, 64, "DCDCFlagsLogic"); m_fieldMap["DCDCFlagsLogic"] = &AMACv2Reg::DCDCFlagsLogic;
-  DCDCFlagValid.initReg(m_cfg, RW, 0, 1, 4, 64, "DCDCFlagValid"); m_fieldMap["DCDCFlagValid"] = &AMACv2Reg::DCDCFlagsLogic;
-  DCDCFlagsValidConf.initReg(m_cfg, RW, 0, 2, 0, 64, "DCDCFlagValid"); m_fieldMap["DCDCFlagValid"] = &AMACv2Reg::DCDCFlagsLogic;
+  DCDCLAM.initReg(m_cfg, RW, 0, 1, 16, 64, "DCDCLAM"); m_fieldMap["DCDCLAM"] = &AMACv2RegMap::DCDCLAM;
+  DCDCFlagsLatch.initReg(m_cfg, RW, 1, 1, 12, 64, "DCDCFlagsLatch"); m_fieldMap["DCDCFlagsLatch"] = &AMACv2RegMap::DCDCFlagsLatch;
+  DCDCFlagsLogic.initReg(m_cfg, RW, 0, 1, 8, 64, "DCDCFlagsLogic"); m_fieldMap["DCDCFlagsLogic"] = &AMACv2RegMap::DCDCFlagsLogic;
+  DCDCFlagValid.initReg(m_cfg, RW, 0, 1, 4, 64, "DCDCFlagValid"); m_fieldMap["DCDCFlagValid"] = &AMACv2RegMap::DCDCFlagsLogic;
+  DCDCFlagsValidConf.initReg(m_cfg, RW, 0, 2, 0, 64, "DCDCFlagValid"); m_fieldMap["DCDCFlagValid"] = &AMACv2RegMap::DCDCFlagsLogic;
   // 65 - WRNICm_cfg
-  WRNLAM.initReg(m_cfg, RW, 0, 1, 16, 65, "WRNLAM"); m_fieldMap["WRNLAM"] = &AMACv2Reg::WRNLAM;
-  WRNFlagsLatch.initReg(m_cfg, RW, 1, 1, 12, 65, "WRNFlagsLatch"); m_fieldMap["WRNFlagsLatch"] = &AMACv2Reg::WRNFlagsLatch;
-  WRNFlagsLogic.initReg(m_cfg, RW, 0, 1, 8, 65, "WRNFlagsLogic"); m_fieldMap["WRNFlagsLogic"] = &AMACv2Reg::WRNFlagsLogic;
-  WRNFlagValid.initReg(m_cfg, RW, 0, 1, 4, 65, "WRNFlagValid"); m_fieldMap["WRNFlagValid"] = &AMACv2Reg::WRNFlagsLogic;
-  WRNFlagsValidConf.initReg(m_cfg, RW, 0, 2, 0, 65, "WRNFlagValid"); m_fieldMap["WRNFlagValid"] = &AMACv2Reg::WRNFlagsLogic;
+  WRNLAM.initReg(m_cfg, RW, 0, 1, 16, 65, "WRNLAM"); m_fieldMap["WRNLAM"] = &AMACv2RegMap::WRNLAM;
+  WRNFlagsLatch.initReg(m_cfg, RW, 1, 1, 12, 65, "WRNFlagsLatch"); m_fieldMap["WRNFlagsLatch"] = &AMACv2RegMap::WRNFlagsLatch;
+  WRNFlagsLogic.initReg(m_cfg, RW, 0, 1, 8, 65, "WRNFlagsLogic"); m_fieldMap["WRNFlagsLogic"] = &AMACv2RegMap::WRNFlagsLogic;
+  WRNFlagValid.initReg(m_cfg, RW, 0, 1, 4, 65, "WRNFlagValid"); m_fieldMap["WRNFlagValid"] = &AMACv2RegMap::WRNFlagsLogic;
+  WRNFlagsValidConf.initReg(m_cfg, RW, 0, 2, 0, 65, "WRNFlagValid"); m_fieldMap["WRNFlagValid"] = &AMACv2RegMap::WRNFlagsLogic;
   // 70 - HxTlut
-  HxTlut.initReg(m_cfg, RW, 0, 8, 0, 70, "HxTlut"); m_fieldMap["HxTlut"] = &AMACv2Reg::HxTlut;
+  HxTlut.initReg(m_cfg, RW, 0, 8, 0, 70, "HxTlut"); m_fieldMap["HxTlut"] = &AMACv2RegMap::HxTlut;
   // 71 - HxModlut1
-  HxModlut1.initReg(m_cfg, RW, 0, 32, 0, 71, "HxModlut1"); m_fieldMap["HxModlut1"] = &AMACv2Reg::HxModlut1;
+  HxModlut1.initReg(m_cfg, RW, 0, 32, 0, 71, "HxModlut1"); m_fieldMap["HxModlut1"] = &AMACv2RegMap::HxModlut1;
   // 72 - HxModlut2
-  HxModlut2.initReg(m_cfg, RW, 0, 32, 0, 72, "HxModlut2"); m_fieldMap["HxModlut2"] = &AMACv2Reg::HxModlut2;
+  HxModlut2.initReg(m_cfg, RW, 0, 32, 0, 72, "HxModlut2"); m_fieldMap["HxModlut2"] = &AMACv2RegMap::HxModlut2;
   // 73 - HyTlut
-  HyTlut.initReg(m_cfg, RW, 0, 8, 0, 73, "HyTlut"); m_fieldMap["HyTlut"] = &AMACv2Reg::HyTlut;
+  HyTlut.initReg(m_cfg, RW, 0, 8, 0, 73, "HyTlut"); m_fieldMap["HyTlut"] = &AMACv2RegMap::HyTlut;
   // 74 - HyModlut1
-  HyModlut1.initReg(m_cfg, RW, 0, 32, 0, 74, "HyModlut1"); m_fieldMap["HyModlut1"] = &AMACv2Reg::HyModlut1;
+  HyModlut1.initReg(m_cfg, RW, 0, 32, 0, 74, "HyModlut1"); m_fieldMap["HyModlut1"] = &AMACv2RegMap::HyModlut1;
   // 75 - HyModlut2
-  HyModlut2.initReg(m_cfg, RW, 0, 32, 0, 75, "HyModlut2"); m_fieldMap["HyModlut2"] = &AMACv2Reg::HyModlut2;
+  HyModlut2.initReg(m_cfg, RW, 0, 32, 0, 75, "HyModlut2"); m_fieldMap["HyModlut2"] = &AMACv2RegMap::HyModlut2;
   // 76 - HV0Tlut;
-  HV0Tlut.initReg(m_cfg, RW, 0, 8, 0, 76, "HV0Tlut"); m_fieldMap["HV0Tlut"] = &AMACv2Reg::HV0Tlut;
+  HV0Tlut.initReg(m_cfg, RW, 0, 8, 0, 76, "HV0Tlut"); m_fieldMap["HV0Tlut"] = &AMACv2RegMap::HV0Tlut;
   // 77 - HV0Modlut1
-  HV0Modlut1.initReg(m_cfg, RW, 0, 32, 0, 77, "HV0Modlut1"); m_fieldMap["HV0Modlut1"] = &AMACv2Reg::HV0Modlut1;
+  HV0Modlut1.initReg(m_cfg, RW, 0, 32, 0, 77, "HV0Modlut1"); m_fieldMap["HV0Modlut1"] = &AMACv2RegMap::HV0Modlut1;
   // 78 - HV0Modlut2
-  HV0Modlut2.initReg(m_cfg, RW, 0, 32, 0, 78, "HV0Modlut2"); m_fieldMap["HV0Modlut2"] = &AMACv2Reg::HV0Modlut2;
+  HV0Modlut2.initReg(m_cfg, RW, 0, 32, 0, 78, "HV0Modlut2"); m_fieldMap["HV0Modlut2"] = &AMACv2RegMap::HV0Modlut2;
   // 79 - HV2Tlut
-  HV2Tlut.initReg(m_cfg, RW, 0, 8, 0, 79, "HV2Tlut"); m_fieldMap["HV2Tlut"] = &AMACv2Reg::HV2Tlut;
+  HV2Tlut.initReg(m_cfg, RW, 0, 8, 0, 79, "HV2Tlut"); m_fieldMap["HV2Tlut"] = &AMACv2RegMap::HV2Tlut;
   // 80 - HV2Modlut1
-  HV2Modlut1.initReg(m_cfg, RW, 0, 32, 0, 80, "HV2Modlut1"); m_fieldMap["HV2Modlut1"] = &AMACv2Reg::HV2Modlut1;
+  HV2Modlut1.initReg(m_cfg, RW, 0, 32, 0, 80, "HV2Modlut1"); m_fieldMap["HV2Modlut1"] = &AMACv2RegMap::HV2Modlut1;
   // 81 - HV2Modlut2
-  HV2Modlut2.initReg(m_cfg, RW, 0, 32, 0, 81, "HV2Modlut2"); m_fieldMap["HV2Modlut2"] = &AMACv2Reg::HV2Modlut2;
+  HV2Modlut2.initReg(m_cfg, RW, 0, 32, 0, 81, "HV2Modlut2"); m_fieldMap["HV2Modlut2"] = &AMACv2RegMap::HV2Modlut2;
   // 82 - DCDCTlut
-  DCDCTlut.initReg(m_cfg, RW, 0, 8, 0, 82, "DCDCTlut"); m_fieldMap["DCDCTlut"] = &AMACv2Reg::DCDCTlut;
+  DCDCTlut.initReg(m_cfg, RW, 0, 8, 0, 82, "DCDCTlut"); m_fieldMap["DCDCTlut"] = &AMACv2RegMap::DCDCTlut;
   // 83 - DCDCModlut1
-  DCDCModlut1.initReg(m_cfg, RW, 0, 32, 0, 83, "DCDCModlut1"); m_fieldMap["DCDCModlut1"] = &AMACv2Reg::DCDCModlut1;
+  DCDCModlut1.initReg(m_cfg, RW, 0, 32, 0, 83, "DCDCModlut1"); m_fieldMap["DCDCModlut1"] = &AMACv2RegMap::DCDCModlut1;
   // 84 - DCDCModlut2
-  DCDCModlut2.initReg(m_cfg, RW, 0, 32, 0, 84, "DCDCModlut2"); m_fieldMap["DCDCModlut2"] = &AMACv2Reg::DCDCModlut2;
+  DCDCModlut2.initReg(m_cfg, RW, 0, 32, 0, 84, "DCDCModlut2"); m_fieldMap["DCDCModlut2"] = &AMACv2RegMap::DCDCModlut2;
   // 85 - WRNTlut
-  WRNTlut.initReg(m_cfg, RW, 0, 8, 0, 85, "WRNTlut"); m_fieldMap["WRNTlut"] = &AMACv2Reg::WRNTlut;
+  WRNTlut.initReg(m_cfg, RW, 0, 8, 0, 85, "WRNTlut"); m_fieldMap["WRNTlut"] = &AMACv2RegMap::WRNTlut;
   // 86 - WRNModlut1
-  WRNModlut1.initReg(m_cfg, RW, 0, 32, 0, 86, "WRNModlut1"); m_fieldMap["WRNModlut1"] = &AMACv2Reg::WRNModlut1;
+  WRNModlut1.initReg(m_cfg, RW, 0, 32, 0, 86, "WRNModlut1"); m_fieldMap["WRNModlut1"] = &AMACv2RegMap::WRNModlut1;
   // 87 - WRNModlut2
-  WRNModlut2.initReg(m_cfg, RW, 0, 32, 0, 87, "WRNModlut2"); m_fieldMap["WRNModlut2"] = &AMACv2Reg::WRNModlut2;
+  WRNModlut2.initReg(m_cfg, RW, 0, 32, 0, 87, "WRNModlut2"); m_fieldMap["WRNModlut2"] = &AMACv2RegMap::WRNModlut2;
   // 90 - HxFlagEn
-  HxFlagsEnHi.initReg(m_cfg, RW, 0, 16, 16, 90, "HxFlagsEnHi"); m_fieldMap["HxFlagsEnHi"] = &AMACv2Reg::HxFlagsEnHi;
-  HxFlagsEnLo.initReg(m_cfg, RW, 0, 16, 16, 90, "HxFlagsEnLo"); m_fieldMap["HxFlagsEnLo"] = &AMACv2Reg::HxFlagsEnLo;
+  HxFlagsEnHi.initReg(m_cfg, RW, 0, 16, 16, 90, "HxFlagsEnHi"); m_fieldMap["HxFlagsEnHi"] = &AMACv2RegMap::HxFlagsEnHi;
+  HxFlagsEnLo.initReg(m_cfg, RW, 0, 16, 16, 90, "HxFlagsEnLo"); m_fieldMap["HxFlagsEnLo"] = &AMACv2RegMap::HxFlagsEnLo;
   // 91 - HyFlagEn
-  HyFlagsEnHi.initReg(m_cfg, RW, 0, 16, 16, 91, "HyFlagsEnHi"); m_fieldMap["HyFlagsEnHi"] = &AMACv2Reg::HyFlagsEnHi;
-  HyFlagsEnLo.initReg(m_cfg, RW, 0, 16, 16, 91, "HyFlagsEnLo"); m_fieldMap["HyFlagsEnLo"] = &AMACv2Reg::HyFlagsEnLo;
+  HyFlagsEnHi.initReg(m_cfg, RW, 0, 16, 16, 91, "HyFlagsEnHi"); m_fieldMap["HyFlagsEnHi"] = &AMACv2RegMap::HyFlagsEnHi;
+  HyFlagsEnLo.initReg(m_cfg, RW, 0, 16, 16, 91, "HyFlagsEnLo"); m_fieldMap["HyFlagsEnLo"] = &AMACv2RegMap::HyFlagsEnLo;
   // 92 - HV0FlagEn
-  HV0FlagsEnHi.initReg(m_cfg, RW, 0, 16, 16, 92, "HV0FlagsEnHi"); m_fieldMap["HV0FlagsEnHi"] = &AMACv2Reg::HV0FlagsEnHi;
-  HV0FlagsEnLo.initReg(m_cfg, RW, 0, 16, 16, 92, "HV0FlagsEnLo"); m_fieldMap["HV0FlagsEnLo"] = &AMACv2Reg::HV0FlagsEnLo;
+  HV0FlagsEnHi.initReg(m_cfg, RW, 0, 16, 16, 92, "HV0FlagsEnHi"); m_fieldMap["HV0FlagsEnHi"] = &AMACv2RegMap::HV0FlagsEnHi;
+  HV0FlagsEnLo.initReg(m_cfg, RW, 0, 16, 16, 92, "HV0FlagsEnLo"); m_fieldMap["HV0FlagsEnLo"] = &AMACv2RegMap::HV0FlagsEnLo;
   // 93 - HV2FlagEn
-  HV2FlagsEnHi.initReg(m_cfg, RW, 0, 16, 16, 93, "HxFlagsEnHi"); m_fieldMap["HxFlagsEnHi"] = &AMACv2Reg::HxFlagsEnHi;
-  HV2FlagsEnLo.initReg(m_cfg, RW, 0, 16, 16, 93, "HxFlagsEnLo"); m_fieldMap["HxFlagsEnLo"] = &AMACv2Reg::HxFlagsEnLo;
+  HV2FlagsEnHi.initReg(m_cfg, RW, 0, 16, 16, 93, "HxFlagsEnHi"); m_fieldMap["HxFlagsEnHi"] = &AMACv2RegMap::HxFlagsEnHi;
+  HV2FlagsEnLo.initReg(m_cfg, RW, 0, 16, 16, 93, "HxFlagsEnLo"); m_fieldMap["HxFlagsEnLo"] = &AMACv2RegMap::HxFlagsEnLo;
   // 94 - DCDCFlagEn
-  DCDCFlagsEnHi.initReg(m_cfg, RW, 0, 16, 16, 94, "DCDCFlagsEnHi"); m_fieldMap["DCDCFlagsEnHi"] = &AMACv2Reg::DCDCFlagsEnHi;
-  DCDCFlagsEnLo.initReg(m_cfg, RW, 0, 16, 16, 94, "DCDCFlagsEnLo"); m_fieldMap["DCDCFlagsEnLo"] = &AMACv2Reg::DCDCFlagsEnLo;
+  DCDCFlagsEnHi.initReg(m_cfg, RW, 0, 16, 16, 94, "DCDCFlagsEnHi"); m_fieldMap["DCDCFlagsEnHi"] = &AMACv2RegMap::DCDCFlagsEnHi;
+  DCDCFlagsEnLo.initReg(m_cfg, RW, 0, 16, 16, 94, "DCDCFlagsEnLo"); m_fieldMap["DCDCFlagsEnLo"] = &AMACv2RegMap::DCDCFlagsEnLo;
   // 94 - WRNFlagEn
-  WRNFlagsEnHi.initReg(m_cfg, RW, 0, 16, 16, 95, "WRNFlagsEnHi"); m_fieldMap["WRNFlagsEnHi"] = &AMACv2Reg::WRNFlagsEnHi;
-  WRNFlagsEnLo.initReg(m_cfg, RW, 0, 16, 16, 95, "WRNFlagsEnLo"); m_fieldMap["WRNFlagsEnLo"] = &AMACv2Reg::WRNFlagsEnLo;
+  WRNFlagsEnHi.initReg(m_cfg, RW, 0, 16, 16, 95, "WRNFlagsEnHi"); m_fieldMap["WRNFlagsEnHi"] = &AMACv2RegMap::WRNFlagsEnHi;
+  WRNFlagsEnLo.initReg(m_cfg, RW, 0, 16, 16, 95, "WRNFlagsEnLo"); m_fieldMap["WRNFlagsEnLo"] = &AMACv2RegMap::WRNFlagsEnLo;
   // 95 - SynFlagEn
-  WRNsynFlagEnHi.initReg(m_cfg, RW, 0, 1, 21, 95, "WRNsynFlagEnHi"); m_fieldMap["WRNsynFlagEnHi"] = &AMACv2Reg::WRNsynFlagEnHi;
-  WRNsynFlagEnLo.initReg(m_cfg, RW, 0, 1, 20, 95, "WRNsynFlagEnLo"); m_fieldMap["WRNsynFlagEnLo"] = &AMACv2Reg::WRNsynFlagEnLo;
-  DCDCsynFlagEnHi.initReg(m_cfg, RW, 0, 1, 17, 95, "DCDCsynFlagEnHi"); m_fieldMap["DCDCsynFlagEnHi"] = &AMACv2Reg::DCDCsynFlagEnHi;
-  DCDCsynFlagEnLo.initReg(m_cfg, RW, 0, 1, 16, 95, "DCDCsynFlagEnLo"); m_fieldMap["DCDCsynFlagEnLo"] = &AMACv2Reg::DCDCsynFlagEnLo;
-  HV2synFlagEnHi.initReg(m_cfg, RW, 0, 1, 13, 95, "HV2synFlagEnHi"); m_fieldMap["HV2synFlagEnHi"] = &AMACv2Reg::HV2synFlagEnHi;
-  HV2synFlagEnLo.initReg(m_cfg, RW, 0, 1, 12, 95, "HV2synFlagEnLo"); m_fieldMap["HV2synFlagEnLo"] = &AMACv2Reg::HV2synFlagEnLo;
-  HV0synFlagEnHi.initReg(m_cfg, RW, 0, 1, 9, 95, "HV0synFlagEnHi"); m_fieldMap["HV0synFlagEnHi"] = &AMACv2Reg::HV0synFlagEnHi;
-  HV0synFlagEnLo.initReg(m_cfg, RW, 0, 1, 8, 95, "HV0synFlagEnLo"); m_fieldMap["HV0synFlagEnLo"] = &AMACv2Reg::HV0synFlagEnLo;
-  HysynFlagEnHi.initReg(m_cfg, RW, 0, 1, 5, 95, "HysynFlagEnHi"); m_fieldMap["HysynFlagEnHi"] = &AMACv2Reg::HysynFlagEnHi;
-  HysynFlagEnLo.initReg(m_cfg, RW, 0, 1, 4, 95, "HysynFlagEnLo"); m_fieldMap["HysynFlagEnLo"] = &AMACv2Reg::HysynFlagEnLo;
-  HxsynFlagEnHi.initReg(m_cfg, RW, 0, 1, 1, 95, "HxsynFlagEnHi"); m_fieldMap["HxsynFlagEnHi"] = &AMACv2Reg::HxsynFlagEnHi;
-  HxsynFlagEnLo.initReg(m_cfg, RW, 0, 1, 0, 95, "HxsynFlagEnLo"); m_fieldMap["HxsynFlagEnLo"] = &AMACv2Reg::HxsynFlagEnLo;
+  WRNsynFlagEnHi.initReg(m_cfg, RW, 0, 1, 21, 95, "WRNsynFlagEnHi"); m_fieldMap["WRNsynFlagEnHi"] = &AMACv2RegMap::WRNsynFlagEnHi;
+  WRNsynFlagEnLo.initReg(m_cfg, RW, 0, 1, 20, 95, "WRNsynFlagEnLo"); m_fieldMap["WRNsynFlagEnLo"] = &AMACv2RegMap::WRNsynFlagEnLo;
+  DCDCsynFlagEnHi.initReg(m_cfg, RW, 0, 1, 17, 95, "DCDCsynFlagEnHi"); m_fieldMap["DCDCsynFlagEnHi"] = &AMACv2RegMap::DCDCsynFlagEnHi;
+  DCDCsynFlagEnLo.initReg(m_cfg, RW, 0, 1, 16, 95, "DCDCsynFlagEnLo"); m_fieldMap["DCDCsynFlagEnLo"] = &AMACv2RegMap::DCDCsynFlagEnLo;
+  HV2synFlagEnHi.initReg(m_cfg, RW, 0, 1, 13, 95, "HV2synFlagEnHi"); m_fieldMap["HV2synFlagEnHi"] = &AMACv2RegMap::HV2synFlagEnHi;
+  HV2synFlagEnLo.initReg(m_cfg, RW, 0, 1, 12, 95, "HV2synFlagEnLo"); m_fieldMap["HV2synFlagEnLo"] = &AMACv2RegMap::HV2synFlagEnLo;
+  HV0synFlagEnHi.initReg(m_cfg, RW, 0, 1, 9, 95, "HV0synFlagEnHi"); m_fieldMap["HV0synFlagEnHi"] = &AMACv2RegMap::HV0synFlagEnHi;
+  HV0synFlagEnLo.initReg(m_cfg, RW, 0, 1, 8, 95, "HV0synFlagEnLo"); m_fieldMap["HV0synFlagEnLo"] = &AMACv2RegMap::HV0synFlagEnLo;
+  HysynFlagEnHi.initReg(m_cfg, RW, 0, 1, 5, 95, "HysynFlagEnHi"); m_fieldMap["HysynFlagEnHi"] = &AMACv2RegMap::HysynFlagEnHi;
+  HysynFlagEnLo.initReg(m_cfg, RW, 0, 1, 4, 95, "HysynFlagEnLo"); m_fieldMap["HysynFlagEnLo"] = &AMACv2RegMap::HysynFlagEnLo;
+  HxsynFlagEnHi.initReg(m_cfg, RW, 0, 1, 1, 95, "HxsynFlagEnHi"); m_fieldMap["HxsynFlagEnHi"] = &AMACv2RegMap::HxsynFlagEnHi;
+  HxsynFlagEnLo.initReg(m_cfg, RW, 0, 1, 0, 95, "HxsynFlagEnLo"); m_fieldMap["HxsynFlagEnLo"] = &AMACv2RegMap::HxsynFlagEnLo;
   // 100 - HxLoTh0
-  HxLoThCh0.initReg(m_cfg, RW, 0, 10, 0, 100, "HxLoThCh0"); m_fieldMap["HxLoThCh0"] = &AMACv2Reg::HxLoThCh0;
-  HxLoThCh1.initReg(m_cfg, RW, 0, 10, 10, 100, "HxLoThCh1"); m_fieldMap["HxLoThCh1"] = &AMACv2Reg::HxLoThCh1;
-  HxLoThCh2.initReg(m_cfg, RW, 0, 10, 20, 100, "HxLoThCh2"); m_fieldMap["HxLoThCh2"] = &AMACv2Reg::HxLoThCh2;
+  HxLoThCh0.initReg(m_cfg, RW, 0, 10, 0, 100, "HxLoThCh0"); m_fieldMap["HxLoThCh0"] = &AMACv2RegMap::HxLoThCh0;
+  HxLoThCh1.initReg(m_cfg, RW, 0, 10, 10, 100, "HxLoThCh1"); m_fieldMap["HxLoThCh1"] = &AMACv2RegMap::HxLoThCh1;
+  HxLoThCh2.initReg(m_cfg, RW, 0, 10, 20, 100, "HxLoThCh2"); m_fieldMap["HxLoThCh2"] = &AMACv2RegMap::HxLoThCh2;
   // 101 - HxLoTh1
-  HxLoThCh3.initReg(m_cfg, RW, 0, 10, 0, 101, "HxLoThCh3"); m_fieldMap["HxLoThCh3"] = &AMACv2Reg::HxLoThCh3;
-  HxLoThCh4.initReg(m_cfg, RW, 0, 10, 10, 101, "HxLoThCh4"); m_fieldMap["HxLoThCh4"] = &AMACv2Reg::HxLoThCh4;
-  HxLoThCh5.initReg(m_cfg, RW, 0, 10, 20, 101, "HxLoThCh5"); m_fieldMap["HxLoThCh5"] = &AMACv2Reg::HxLoThCh5;
+  HxLoThCh3.initReg(m_cfg, RW, 0, 10, 0, 101, "HxLoThCh3"); m_fieldMap["HxLoThCh3"] = &AMACv2RegMap::HxLoThCh3;
+  HxLoThCh4.initReg(m_cfg, RW, 0, 10, 10, 101, "HxLoThCh4"); m_fieldMap["HxLoThCh4"] = &AMACv2RegMap::HxLoThCh4;
+  HxLoThCh5.initReg(m_cfg, RW, 0, 10, 20, 101, "HxLoThCh5"); m_fieldMap["HxLoThCh5"] = &AMACv2RegMap::HxLoThCh5;
   // 102 - HxLoTh2
-  HxLoThCh6.initReg(m_cfg, RW, 0, 10, 0, 102, "HxLoThCh6"); m_fieldMap["HxLoThCh6"] = &AMACv2Reg::HxLoThCh6;
-  HxLoThCh7.initReg(m_cfg, RW, 0, 10, 10, 102, "HxLoThCh7"); m_fieldMap["HxLoThCh7"] = &AMACv2Reg::HxLoThCh7;
-  HxLoThCh8.initReg(m_cfg, RW, 0, 10, 20, 102, "HxLoThCh8"); m_fieldMap["HxLoThCh8"] = &AMACv2Reg::HxLoThCh8;
+  HxLoThCh6.initReg(m_cfg, RW, 0, 10, 0, 102, "HxLoThCh6"); m_fieldMap["HxLoThCh6"] = &AMACv2RegMap::HxLoThCh6;
+  HxLoThCh7.initReg(m_cfg, RW, 0, 10, 10, 102, "HxLoThCh7"); m_fieldMap["HxLoThCh7"] = &AMACv2RegMap::HxLoThCh7;
+  HxLoThCh8.initReg(m_cfg, RW, 0, 10, 20, 102, "HxLoThCh8"); m_fieldMap["HxLoThCh8"] = &AMACv2RegMap::HxLoThCh8;
   // 103 - HxLoTh3
-  HxLoThCh9.initReg(m_cfg, RW, 0, 10, 0, 103, "HxLoThCh9"); m_fieldMap["HxLoThCh9"] = &AMACv2Reg::HxLoThCh9;
-  HxLoThCh10.initReg(m_cfg, RW, 0, 10, 10, 103, "HxLoThCh10"); m_fieldMap["HxLoThCh10"] = &AMACv2Reg::HxLoThCh10;
-  HxLoThCh11.initReg(m_cfg, RW, 0, 10, 20, 103, "HxLoThCh11"); m_fieldMap["HxLoThCh11"] = &AMACv2Reg::HxLoThCh11;
+  HxLoThCh9.initReg(m_cfg, RW, 0, 10, 0, 103, "HxLoThCh9"); m_fieldMap["HxLoThCh9"] = &AMACv2RegMap::HxLoThCh9;
+  HxLoThCh10.initReg(m_cfg, RW, 0, 10, 10, 103, "HxLoThCh10"); m_fieldMap["HxLoThCh10"] = &AMACv2RegMap::HxLoThCh10;
+  HxLoThCh11.initReg(m_cfg, RW, 0, 10, 20, 103, "HxLoThCh11"); m_fieldMap["HxLoThCh11"] = &AMACv2RegMap::HxLoThCh11;
   // 104 - HxLoTh4
-  HxLoThCh12.initReg(m_cfg, RW, 0, 10, 0, 104, "HxLoThCh12"); m_fieldMap["HxLoThCh12"] = &AMACv2Reg::HxLoThCh12;
-  HxLoThCh13.initReg(m_cfg, RW, 0, 10, 10, 104, "HxLoThCh13"); m_fieldMap["HxLoThCh13"] = &AMACv2Reg::HxLoThCh13;
-  HxLoThCh14.initReg(m_cfg, RW, 0, 10, 20, 104, "HxLoThCh14"); m_fieldMap["HxLoThCh14"] = &AMACv2Reg::HxLoThCh14;
+  HxLoThCh12.initReg(m_cfg, RW, 0, 10, 0, 104, "HxLoThCh12"); m_fieldMap["HxLoThCh12"] = &AMACv2RegMap::HxLoThCh12;
+  HxLoThCh13.initReg(m_cfg, RW, 0, 10, 10, 104, "HxLoThCh13"); m_fieldMap["HxLoThCh13"] = &AMACv2RegMap::HxLoThCh13;
+  HxLoThCh14.initReg(m_cfg, RW, 0, 10, 20, 104, "HxLoThCh14"); m_fieldMap["HxLoThCh14"] = &AMACv2RegMap::HxLoThCh14;
   // 105 - HxLoTh5
-  HxLoThCh15.initReg(m_cfg, RW, 0, 10, 0, 105, "HxLoThCh15"); m_fieldMap["HxLoThCh15"] = &AMACv2Reg::HxLoThCh15;
+  HxLoThCh15.initReg(m_cfg, RW, 0, 10, 0, 105, "HxLoThCh15"); m_fieldMap["HxLoThCh15"] = &AMACv2RegMap::HxLoThCh15;
   // 106 - HxHiTh0
-  HxHiThCh0.initReg(m_cfg, RW, 0x3FF, 10, 0, 106, "HxLoThCh0"); m_fieldMap["HxLoThCh0"] = &AMACv2Reg::HxLoThCh0;
-  HxHiThCh1.initReg(m_cfg, RW, 0x3FF, 10, 10, 106, "HxLoThCh1"); m_fieldMap["HxLoThCh1"] = &AMACv2Reg::HxLoThCh1;
-  HxHiThCh2.initReg(m_cfg, RW, 0x3FF, 10, 20, 106, "HxLoThCh2"); m_fieldMap["HxLoThCh2"] = &AMACv2Reg::HxLoThCh2;
+  HxHiThCh0.initReg(m_cfg, RW, 0x3FF, 10, 0, 106, "HxLoThCh0"); m_fieldMap["HxLoThCh0"] = &AMACv2RegMap::HxLoThCh0;
+  HxHiThCh1.initReg(m_cfg, RW, 0x3FF, 10, 10, 106, "HxLoThCh1"); m_fieldMap["HxLoThCh1"] = &AMACv2RegMap::HxLoThCh1;
+  HxHiThCh2.initReg(m_cfg, RW, 0x3FF, 10, 20, 106, "HxLoThCh2"); m_fieldMap["HxLoThCh2"] = &AMACv2RegMap::HxLoThCh2;
   // 107 - HxHiTh1
-  HxHiThCh3.initReg(m_cfg, RW, 0x3FF, 10, 0, 107, "HxHiThCh3"); m_fieldMap["HxHiThCh3"] = &AMACv2Reg::HxHiThCh3;
-  HxHiThCh4.initReg(m_cfg, RW, 0x3FF, 10, 10, 107, "HxHiThCh4"); m_fieldMap["HxHiThCh4"] = &AMACv2Reg::HxHiThCh4;
-  HxHiThCh5.initReg(m_cfg, RW, 0x3FF, 10, 20, 107, "HxHiThCh5"); m_fieldMap["HxHiThCh5"] = &AMACv2Reg::HxHiThCh5;
+  HxHiThCh3.initReg(m_cfg, RW, 0x3FF, 10, 0, 107, "HxHiThCh3"); m_fieldMap["HxHiThCh3"] = &AMACv2RegMap::HxHiThCh3;
+  HxHiThCh4.initReg(m_cfg, RW, 0x3FF, 10, 10, 107, "HxHiThCh4"); m_fieldMap["HxHiThCh4"] = &AMACv2RegMap::HxHiThCh4;
+  HxHiThCh5.initReg(m_cfg, RW, 0x3FF, 10, 20, 107, "HxHiThCh5"); m_fieldMap["HxHiThCh5"] = &AMACv2RegMap::HxHiThCh5;
   // 108 - HxHiTh2
-  HxHiThCh6.initReg(m_cfg, RW, 0x3FF, 10, 0, 108, "HxHiThCh6"); m_fieldMap["HxHiThCh6"] = &AMACv2Reg::HxHiThCh6;
-  HxHiThCh7.initReg(m_cfg, RW, 0x3FF, 10, 10, 108, "HxHiThCh7"); m_fieldMap["HxHiThCh7"] = &AMACv2Reg::HxHiThCh7;
-  HxHiThCh8.initReg(m_cfg, RW, 0x3FF, 10, 20, 108, "HxHiThCh8"); m_fieldMap["HxHiThCh8"] = &AMACv2Reg::HxHiThCh8;
+  HxHiThCh6.initReg(m_cfg, RW, 0x3FF, 10, 0, 108, "HxHiThCh6"); m_fieldMap["HxHiThCh6"] = &AMACv2RegMap::HxHiThCh6;
+  HxHiThCh7.initReg(m_cfg, RW, 0x3FF, 10, 10, 108, "HxHiThCh7"); m_fieldMap["HxHiThCh7"] = &AMACv2RegMap::HxHiThCh7;
+  HxHiThCh8.initReg(m_cfg, RW, 0x3FF, 10, 20, 108, "HxHiThCh8"); m_fieldMap["HxHiThCh8"] = &AMACv2RegMap::HxHiThCh8;
   // 109 - HxHiTh3
-  HxHiThCh9.initReg(m_cfg, RW, 0x3FF, 10, 0, 109, "HxHiThCh9"); m_fieldMap["HxHiThCh9"] = &AMACv2Reg::HxHiThCh9;
-  HxHiThCh10.initReg(m_cfg, RW, 0x3FF, 10, 10, 109, "HxHiThCh10"); m_fieldMap["HxHiThCh10"] = &AMACv2Reg::HxHiThCh10;
-  HxHiThCh11.initReg(m_cfg, RW, 0x3FF, 10, 20, 109, "HxHiThCh11"); m_fieldMap["HxHiThCh11"] = &AMACv2Reg::HxHiThCh11;
+  HxHiThCh9.initReg(m_cfg, RW, 0x3FF, 10, 0, 109, "HxHiThCh9"); m_fieldMap["HxHiThCh9"] = &AMACv2RegMap::HxHiThCh9;
+  HxHiThCh10.initReg(m_cfg, RW, 0x3FF, 10, 10, 109, "HxHiThCh10"); m_fieldMap["HxHiThCh10"] = &AMACv2RegMap::HxHiThCh10;
+  HxHiThCh11.initReg(m_cfg, RW, 0x3FF, 10, 20, 109, "HxHiThCh11"); m_fieldMap["HxHiThCh11"] = &AMACv2RegMap::HxHiThCh11;
   // 110 - HxHiTh4
-  HxHiThCh12.initReg(m_cfg, RW, 0x3FF, 10, 0, 110, "HxHiThCh12"); m_fieldMap["HxHiThCh12"] = &AMACv2Reg::HxHiThCh12;
-  HxHiThCh13.initReg(m_cfg, RW, 0x3FF, 10, 10, 110, "HxHiThCh13"); m_fieldMap["HxHiThCh13"] = &AMACv2Reg::HxHiThCh13;
-  HxHiThCh14.initReg(m_cfg, RW, 0x3FF, 10, 20, 110, "HxHiThCh14"); m_fieldMap["HxHiThCh14"] = &AMACv2Reg::HxHiThCh14;
+  HxHiThCh12.initReg(m_cfg, RW, 0x3FF, 10, 0, 110, "HxHiThCh12"); m_fieldMap["HxHiThCh12"] = &AMACv2RegMap::HxHiThCh12;
+  HxHiThCh13.initReg(m_cfg, RW, 0x3FF, 10, 10, 110, "HxHiThCh13"); m_fieldMap["HxHiThCh13"] = &AMACv2RegMap::HxHiThCh13;
+  HxHiThCh14.initReg(m_cfg, RW, 0x3FF, 10, 20, 110, "HxHiThCh14"); m_fieldMap["HxHiThCh14"] = &AMACv2RegMap::HxHiThCh14;
   // 111 - HxHiTh5
-  HxHiThCh15.initReg(m_cfg, RW, 0x3FF, 10, 0, 111, "HxHiThCh15"); m_fieldMap["HxHiThCh15"] = &AMACv2Reg::HxHiThCh15;
+  HxHiThCh15.initReg(m_cfg, RW, 0x3FF, 10, 0, 111, "HxHiThCh15"); m_fieldMap["HxHiThCh15"] = &AMACv2RegMap::HxHiThCh15;
   // 112 - HyLoTh0
-  HyLoThCh0.initReg(m_cfg, RW, 0, 10, 0, 112, "HyLoThCh0"); m_fieldMap["HyLoThCh0"] = &AMACv2Reg::HyLoThCh0;
-  HyLoThCh1.initReg(m_cfg, RW, 0, 10, 10, 112, "HyLoThCh1"); m_fieldMap["HyLoThCh1"] = &AMACv2Reg::HyLoThCh1;
-  HyLoThCh2.initReg(m_cfg, RW, 0, 10, 20, 112, "HyLoThCh2"); m_fieldMap["HyLoThCh2"] = &AMACv2Reg::HyLoThCh2;
+  HyLoThCh0.initReg(m_cfg, RW, 0, 10, 0, 112, "HyLoThCh0"); m_fieldMap["HyLoThCh0"] = &AMACv2RegMap::HyLoThCh0;
+  HyLoThCh1.initReg(m_cfg, RW, 0, 10, 10, 112, "HyLoThCh1"); m_fieldMap["HyLoThCh1"] = &AMACv2RegMap::HyLoThCh1;
+  HyLoThCh2.initReg(m_cfg, RW, 0, 10, 20, 112, "HyLoThCh2"); m_fieldMap["HyLoThCh2"] = &AMACv2RegMap::HyLoThCh2;
   // 113 - HyLoTh1
-  HyLoThCh3.initReg(m_cfg, RW, 0, 10, 0, 113, "HyLoThCh3"); m_fieldMap["HyLoThCh3"] = &AMACv2Reg::HyLoThCh3;
-  HyLoThCh4.initReg(m_cfg, RW, 0, 10, 10, 113, "HyLoThCh4"); m_fieldMap["HyLoThCh4"] = &AMACv2Reg::HyLoThCh4;
-  HyLoThCh5.initReg(m_cfg, RW, 0, 10, 20, 113, "HyLoThCh5"); m_fieldMap["HyLoThCh5"] = &AMACv2Reg::HyLoThCh5;
+  HyLoThCh3.initReg(m_cfg, RW, 0, 10, 0, 113, "HyLoThCh3"); m_fieldMap["HyLoThCh3"] = &AMACv2RegMap::HyLoThCh3;
+  HyLoThCh4.initReg(m_cfg, RW, 0, 10, 10, 113, "HyLoThCh4"); m_fieldMap["HyLoThCh4"] = &AMACv2RegMap::HyLoThCh4;
+  HyLoThCh5.initReg(m_cfg, RW, 0, 10, 20, 113, "HyLoThCh5"); m_fieldMap["HyLoThCh5"] = &AMACv2RegMap::HyLoThCh5;
   // 114 - HyLoTh2
-  HyLoThCh6.initReg(m_cfg, RW, 0, 10, 0, 114, "HyLoThCh6"); m_fieldMap["HyLoThCh6"] = &AMACv2Reg::HyLoThCh6;
-  HyLoThCh7.initReg(m_cfg, RW, 0, 10, 10, 114, "HyLoThCh7"); m_fieldMap["HyLoThCh7"] = &AMACv2Reg::HyLoThCh7;
-  HyLoThCh8.initReg(m_cfg, RW, 0, 10, 20, 114, "HyLoThCh8"); m_fieldMap["HyLoThCh8"] = &AMACv2Reg::HyLoThCh8;
+  HyLoThCh6.initReg(m_cfg, RW, 0, 10, 0, 114, "HyLoThCh6"); m_fieldMap["HyLoThCh6"] = &AMACv2RegMap::HyLoThCh6;
+  HyLoThCh7.initReg(m_cfg, RW, 0, 10, 10, 114, "HyLoThCh7"); m_fieldMap["HyLoThCh7"] = &AMACv2RegMap::HyLoThCh7;
+  HyLoThCh8.initReg(m_cfg, RW, 0, 10, 20, 114, "HyLoThCh8"); m_fieldMap["HyLoThCh8"] = &AMACv2RegMap::HyLoThCh8;
   // 115 - HyLoTh3
-  HyLoThCh9.initReg(m_cfg, RW, 0, 10, 0, 115, "HyLoThCh9"); m_fieldMap["HyLoThCh9"] = &AMACv2Reg::HyLoThCh9;
-  HyLoThCh10.initReg(m_cfg, RW, 0, 10, 10, 115, "HyLoThCh10"); m_fieldMap["HyLoThCh10"] = &AMACv2Reg::HyLoThCh10;
-  HyLoThCh11.initReg(m_cfg, RW, 0, 10, 20, 115, "HyLoThCh11"); m_fieldMap["HyLoThCh11"] = &AMACv2Reg::HyLoThCh11;
+  HyLoThCh9.initReg(m_cfg, RW, 0, 10, 0, 115, "HyLoThCh9"); m_fieldMap["HyLoThCh9"] = &AMACv2RegMap::HyLoThCh9;
+  HyLoThCh10.initReg(m_cfg, RW, 0, 10, 10, 115, "HyLoThCh10"); m_fieldMap["HyLoThCh10"] = &AMACv2RegMap::HyLoThCh10;
+  HyLoThCh11.initReg(m_cfg, RW, 0, 10, 20, 115, "HyLoThCh11"); m_fieldMap["HyLoThCh11"] = &AMACv2RegMap::HyLoThCh11;
   // 116 - HyLoTh4
-  HyLoThCh12.initReg(m_cfg, RW, 0, 10, 0, 116, "HyLoThCh12"); m_fieldMap["HyLoThCh12"] = &AMACv2Reg::HyLoThCh12;
-  HyLoThCh13.initReg(m_cfg, RW, 0, 10, 10, 116, "HyLoThCh13"); m_fieldMap["HyLoThCh13"] = &AMACv2Reg::HyLoThCh13;
-  HyLoThCh14.initReg(m_cfg, RW, 0, 10, 20, 116, "HyLoThCh14"); m_fieldMap["HyLoThCh14"] = &AMACv2Reg::HyLoThCh14;
+  HyLoThCh12.initReg(m_cfg, RW, 0, 10, 0, 116, "HyLoThCh12"); m_fieldMap["HyLoThCh12"] = &AMACv2RegMap::HyLoThCh12;
+  HyLoThCh13.initReg(m_cfg, RW, 0, 10, 10, 116, "HyLoThCh13"); m_fieldMap["HyLoThCh13"] = &AMACv2RegMap::HyLoThCh13;
+  HyLoThCh14.initReg(m_cfg, RW, 0, 10, 20, 116, "HyLoThCh14"); m_fieldMap["HyLoThCh14"] = &AMACv2RegMap::HyLoThCh14;
   // 117 - HyLoTh5
-  HyLoThCh15.initReg(m_cfg, RW, 0, 10, 0, 117, "HyLoThCh15"); m_fieldMap["HyLoThCh15"] = &AMACv2Reg::HyLoThCh15;
+  HyLoThCh15.initReg(m_cfg, RW, 0, 10, 0, 117, "HyLoThCh15"); m_fieldMap["HyLoThCh15"] = &AMACv2RegMap::HyLoThCh15;
   // 118 - HyHiTh0
-  HyHiThCh0.initReg(m_cfg, RW, 0x3FF, 10, 0, 118, "HyLoThCh0"); m_fieldMap["HyLoThCh0"] = &AMACv2Reg::HyLoThCh0;
-  HyHiThCh1.initReg(m_cfg, RW, 0x3FF, 10, 10, 118, "HyLoThCh1"); m_fieldMap["HyLoThCh1"] = &AMACv2Reg::HyLoThCh1;
-  HyHiThCh2.initReg(m_cfg, RW, 0x3FF, 10, 20, 118, "HyLoThCh2"); m_fieldMap["HyLoThCh2"] = &AMACv2Reg::HyLoThCh2;
+  HyHiThCh0.initReg(m_cfg, RW, 0x3FF, 10, 0, 118, "HyLoThCh0"); m_fieldMap["HyLoThCh0"] = &AMACv2RegMap::HyLoThCh0;
+  HyHiThCh1.initReg(m_cfg, RW, 0x3FF, 10, 10, 118, "HyLoThCh1"); m_fieldMap["HyLoThCh1"] = &AMACv2RegMap::HyLoThCh1;
+  HyHiThCh2.initReg(m_cfg, RW, 0x3FF, 10, 20, 118, "HyLoThCh2"); m_fieldMap["HyLoThCh2"] = &AMACv2RegMap::HyLoThCh2;
   // 119 - HyHiTh1
-  HyHiThCh3.initReg(m_cfg, RW, 0x3FF, 10, 0, 119, "HyHiThCh3"); m_fieldMap["HyHiThCh3"] = &AMACv2Reg::HyHiThCh3;
-  HyHiThCh4.initReg(m_cfg, RW, 0x3FF, 10, 10, 119, "HyHiThCh4"); m_fieldMap["HyHiThCh4"] = &AMACv2Reg::HyHiThCh4;
-  HyHiThCh5.initReg(m_cfg, RW, 0x3FF, 10, 20, 119, "HyHiThCh5"); m_fieldMap["HyHiThCh5"] = &AMACv2Reg::HyHiThCh5;
+  HyHiThCh3.initReg(m_cfg, RW, 0x3FF, 10, 0, 119, "HyHiThCh3"); m_fieldMap["HyHiThCh3"] = &AMACv2RegMap::HyHiThCh3;
+  HyHiThCh4.initReg(m_cfg, RW, 0x3FF, 10, 10, 119, "HyHiThCh4"); m_fieldMap["HyHiThCh4"] = &AMACv2RegMap::HyHiThCh4;
+  HyHiThCh5.initReg(m_cfg, RW, 0x3FF, 10, 20, 119, "HyHiThCh5"); m_fieldMap["HyHiThCh5"] = &AMACv2RegMap::HyHiThCh5;
   // 120 - HyHiTh2
-  HyHiThCh6.initReg(m_cfg, RW, 0x3FF, 10, 0, 120, "HyHiThCh6"); m_fieldMap["HyHiThCh6"] = &AMACv2Reg::HyHiThCh6;
-  HyHiThCh7.initReg(m_cfg, RW, 0x3FF, 10, 10, 120, "HyHiThCh7"); m_fieldMap["HyHiThCh7"] = &AMACv2Reg::HyHiThCh7;
-  HyHiThCh8.initReg(m_cfg, RW, 0x3FF, 10, 20, 120, "HyHiThCh8"); m_fieldMap["HyHiThCh8"] = &AMACv2Reg::HyHiThCh8;
+  HyHiThCh6.initReg(m_cfg, RW, 0x3FF, 10, 0, 120, "HyHiThCh6"); m_fieldMap["HyHiThCh6"] = &AMACv2RegMap::HyHiThCh6;
+  HyHiThCh7.initReg(m_cfg, RW, 0x3FF, 10, 10, 120, "HyHiThCh7"); m_fieldMap["HyHiThCh7"] = &AMACv2RegMap::HyHiThCh7;
+  HyHiThCh8.initReg(m_cfg, RW, 0x3FF, 10, 20, 120, "HyHiThCh8"); m_fieldMap["HyHiThCh8"] = &AMACv2RegMap::HyHiThCh8;
   // 121 - HyHiTh3
-  HyHiThCh9.initReg(m_cfg, RW, 0x3FF, 10, 0, 121, "HyHiThCh9"); m_fieldMap["HyHiThCh9"] = &AMACv2Reg::HyHiThCh9;
-  HyHiThCh10.initReg(m_cfg, RW, 0x3FF, 10, 10, 121, "HyHiThCh10"); m_fieldMap["HyHiThCh10"] = &AMACv2Reg::HyHiThCh10;
-  HyHiThCh11.initReg(m_cfg, RW, 0x3FF, 10, 20, 121, "HyHiThCh11"); m_fieldMap["HyHiThCh11"] = &AMACv2Reg::HyHiThCh11;
+  HyHiThCh9.initReg(m_cfg, RW, 0x3FF, 10, 0, 121, "HyHiThCh9"); m_fieldMap["HyHiThCh9"] = &AMACv2RegMap::HyHiThCh9;
+  HyHiThCh10.initReg(m_cfg, RW, 0x3FF, 10, 10, 121, "HyHiThCh10"); m_fieldMap["HyHiThCh10"] = &AMACv2RegMap::HyHiThCh10;
+  HyHiThCh11.initReg(m_cfg, RW, 0x3FF, 10, 20, 121, "HyHiThCh11"); m_fieldMap["HyHiThCh11"] = &AMACv2RegMap::HyHiThCh11;
   // 122 - HyHiTh4
-  HyHiThCh12.initReg(m_cfg, RW, 0x3FF, 10, 0, 122, "HyHiThCh12"); m_fieldMap["HyHiThCh12"] = &AMACv2Reg::HyHiThCh12;
-  HyHiThCh13.initReg(m_cfg, RW, 0x3FF, 10, 10, 122, "HyHiThCh13"); m_fieldMap["HyHiThCh13"] = &AMACv2Reg::HyHiThCh13;
-  HyHiThCh14.initReg(m_cfg, RW, 0x3FF, 10, 20, 122, "HyHiThCh14"); m_fieldMap["HyHiThCh14"] = &AMACv2Reg::HyHiThCh14;
+  HyHiThCh12.initReg(m_cfg, RW, 0x3FF, 10, 0, 122, "HyHiThCh12"); m_fieldMap["HyHiThCh12"] = &AMACv2RegMap::HyHiThCh12;
+  HyHiThCh13.initReg(m_cfg, RW, 0x3FF, 10, 10, 122, "HyHiThCh13"); m_fieldMap["HyHiThCh13"] = &AMACv2RegMap::HyHiThCh13;
+  HyHiThCh14.initReg(m_cfg, RW, 0x3FF, 10, 20, 122, "HyHiThCh14"); m_fieldMap["HyHiThCh14"] = &AMACv2RegMap::HyHiThCh14;
   // 123 - HyHiTh5
-  HyHiThCh15.initReg(m_cfg, RW, 0x3FF, 10, 0, 123, "HyHiThCh15"); m_fieldMap["HyHiThCh15"] = &AMACv2Reg::HyHiThCh15;
+  HyHiThCh15.initReg(m_cfg, RW, 0x3FF, 10, 0, 123, "HyHiThCh15"); m_fieldMap["HyHiThCh15"] = &AMACv2RegMap::HyHiThCh15;
   // 124 - HV0LoTh0
-  HV0LoThCh0.initReg(m_cfg, RW, 0, 10, 0, 124, "HV0LoThCh0"); m_fieldMap["HV0LoThCh0"] = &AMACv2Reg::HV0LoThCh0;
-  HV0LoThCh1.initReg(m_cfg, RW, 0, 10, 10, 124, "HV0LoThCh1"); m_fieldMap["HV0LoThCh1"] = &AMACv2Reg::HV0LoThCh1;
-  HV0LoThCh2.initReg(m_cfg, RW, 0, 10, 20, 124, "HV0LoThCh2"); m_fieldMap["HV0LoThCh2"] = &AMACv2Reg::HV0LoThCh2;
+  HV0LoThCh0.initReg(m_cfg, RW, 0, 10, 0, 124, "HV0LoThCh0"); m_fieldMap["HV0LoThCh0"] = &AMACv2RegMap::HV0LoThCh0;
+  HV0LoThCh1.initReg(m_cfg, RW, 0, 10, 10, 124, "HV0LoThCh1"); m_fieldMap["HV0LoThCh1"] = &AMACv2RegMap::HV0LoThCh1;
+  HV0LoThCh2.initReg(m_cfg, RW, 0, 10, 20, 124, "HV0LoThCh2"); m_fieldMap["HV0LoThCh2"] = &AMACv2RegMap::HV0LoThCh2;
   // 125 - HV0LoTh1
-  HV0LoThCh3.initReg(m_cfg, RW, 0, 10, 0, 125, "HV0LoThCh3"); m_fieldMap["HV0LoThCh3"] = &AMACv2Reg::HV0LoThCh3;
-  HV0LoThCh4.initReg(m_cfg, RW, 0, 10, 10, 125, "HV0LoThCh4"); m_fieldMap["HV0LoThCh4"] = &AMACv2Reg::HV0LoThCh4;
-  HV0LoThCh5.initReg(m_cfg, RW, 0, 10, 20, 125, "HV0LoThCh5"); m_fieldMap["HV0LoThCh5"] = &AMACv2Reg::HV0LoThCh5;
+  HV0LoThCh3.initReg(m_cfg, RW, 0, 10, 0, 125, "HV0LoThCh3"); m_fieldMap["HV0LoThCh3"] = &AMACv2RegMap::HV0LoThCh3;
+  HV0LoThCh4.initReg(m_cfg, RW, 0, 10, 10, 125, "HV0LoThCh4"); m_fieldMap["HV0LoThCh4"] = &AMACv2RegMap::HV0LoThCh4;
+  HV0LoThCh5.initReg(m_cfg, RW, 0, 10, 20, 125, "HV0LoThCh5"); m_fieldMap["HV0LoThCh5"] = &AMACv2RegMap::HV0LoThCh5;
   // 126 - HV0LoTh2
-  HV0LoThCh6.initReg(m_cfg, RW, 0, 10, 0, 126, "HV0LoThCh6"); m_fieldMap["HV0LoThCh6"] = &AMACv2Reg::HV0LoThCh6;
-  HV0LoThCh7.initReg(m_cfg, RW, 0, 10, 10, 126, "HV0LoThCh7"); m_fieldMap["HV0LoThCh7"] = &AMACv2Reg::HV0LoThCh7;
-  HV0LoThCh8.initReg(m_cfg, RW, 0, 10, 20, 126, "HV0LoThCh8"); m_fieldMap["HV0LoThCh8"] = &AMACv2Reg::HV0LoThCh8;
+  HV0LoThCh6.initReg(m_cfg, RW, 0, 10, 0, 126, "HV0LoThCh6"); m_fieldMap["HV0LoThCh6"] = &AMACv2RegMap::HV0LoThCh6;
+  HV0LoThCh7.initReg(m_cfg, RW, 0, 10, 10, 126, "HV0LoThCh7"); m_fieldMap["HV0LoThCh7"] = &AMACv2RegMap::HV0LoThCh7;
+  HV0LoThCh8.initReg(m_cfg, RW, 0, 10, 20, 126, "HV0LoThCh8"); m_fieldMap["HV0LoThCh8"] = &AMACv2RegMap::HV0LoThCh8;
   // 127 - HV0LoTh3
-  HV0LoThCh9.initReg(m_cfg, RW, 0, 10, 0, 127, "HV0LoThCh9"); m_fieldMap["HV0LoThCh9"] = &AMACv2Reg::HV0LoThCh9;
-  HV0LoThCh10.initReg(m_cfg, RW, 0, 10, 10, 127, "HV0LoThCh10"); m_fieldMap["HV0LoThCh10"] = &AMACv2Reg::HV0LoThCh10;
-  HV0LoThCh11.initReg(m_cfg, RW, 0, 10, 20, 127, "HV0LoThCh11"); m_fieldMap["HV0LoThCh11"] = &AMACv2Reg::HV0LoThCh11;
+  HV0LoThCh9.initReg(m_cfg, RW, 0, 10, 0, 127, "HV0LoThCh9"); m_fieldMap["HV0LoThCh9"] = &AMACv2RegMap::HV0LoThCh9;
+  HV0LoThCh10.initReg(m_cfg, RW, 0, 10, 10, 127, "HV0LoThCh10"); m_fieldMap["HV0LoThCh10"] = &AMACv2RegMap::HV0LoThCh10;
+  HV0LoThCh11.initReg(m_cfg, RW, 0, 10, 20, 127, "HV0LoThCh11"); m_fieldMap["HV0LoThCh11"] = &AMACv2RegMap::HV0LoThCh11;
   // 128 - HV0LoTh4
-  HV0LoThCh12.initReg(m_cfg, RW, 0, 10, 0, 128, "HV0LoThCh12"); m_fieldMap["HV0LoThCh12"] = &AMACv2Reg::HV0LoThCh12;
-  HV0LoThCh13.initReg(m_cfg, RW, 0, 10, 10, 128, "HV0LoThCh13"); m_fieldMap["HV0LoThCh13"] = &AMACv2Reg::HV0LoThCh13;
-  HV0LoThCh14.initReg(m_cfg, RW, 0, 10, 20, 128, "HV0LoThCh14"); m_fieldMap["HV0LoThCh14"] = &AMACv2Reg::HV0LoThCh14;
+  HV0LoThCh12.initReg(m_cfg, RW, 0, 10, 0, 128, "HV0LoThCh12"); m_fieldMap["HV0LoThCh12"] = &AMACv2RegMap::HV0LoThCh12;
+  HV0LoThCh13.initReg(m_cfg, RW, 0, 10, 10, 128, "HV0LoThCh13"); m_fieldMap["HV0LoThCh13"] = &AMACv2RegMap::HV0LoThCh13;
+  HV0LoThCh14.initReg(m_cfg, RW, 0, 10, 20, 128, "HV0LoThCh14"); m_fieldMap["HV0LoThCh14"] = &AMACv2RegMap::HV0LoThCh14;
   // 129 - HV0LoTh5
-  HV0LoThCh15.initReg(m_cfg, RW, 0, 10, 0, 129, "HV0LoThCh15"); m_fieldMap["HV0LoThCh15"] = &AMACv2Reg::HV0LoThCh15;
+  HV0LoThCh15.initReg(m_cfg, RW, 0, 10, 0, 129, "HV0LoThCh15"); m_fieldMap["HV0LoThCh15"] = &AMACv2RegMap::HV0LoThCh15;
   // 130 - HV0HiTh0
-  HV0HiThCh0.initReg(m_cfg, RW, 0x3FF, 10, 0, 130, "HV0LoThCh0"); m_fieldMap["HV0LoThCh0"] = &AMACv2Reg::HV0LoThCh0;
-  HV0HiThCh1.initReg(m_cfg, RW, 0x3FF, 10, 10, 130, "HV0LoThCh1"); m_fieldMap["HV0LoThCh1"] = &AMACv2Reg::HV0LoThCh1;
-  HV0HiThCh2.initReg(m_cfg, RW, 0x3FF, 10, 20, 130, "HV0LoThCh2"); m_fieldMap["HV0LoThCh2"] = &AMACv2Reg::HV0LoThCh2;
+  HV0HiThCh0.initReg(m_cfg, RW, 0x3FF, 10, 0, 130, "HV0LoThCh0"); m_fieldMap["HV0LoThCh0"] = &AMACv2RegMap::HV0LoThCh0;
+  HV0HiThCh1.initReg(m_cfg, RW, 0x3FF, 10, 10, 130, "HV0LoThCh1"); m_fieldMap["HV0LoThCh1"] = &AMACv2RegMap::HV0LoThCh1;
+  HV0HiThCh2.initReg(m_cfg, RW, 0x3FF, 10, 20, 130, "HV0LoThCh2"); m_fieldMap["HV0LoThCh2"] = &AMACv2RegMap::HV0LoThCh2;
   // 131 - HV0HiTh1
-  HV0HiThCh3.initReg(m_cfg, RW, 0x3FF, 10, 0, 131, "HV0HiThCh3"); m_fieldMap["HV0HiThCh3"] = &AMACv2Reg::HV0HiThCh3;
-  HV0HiThCh4.initReg(m_cfg, RW, 0x3FF, 10, 10, 131, "HV0HiThCh4"); m_fieldMap["HV0HiThCh4"] = &AMACv2Reg::HV0HiThCh4;
-  HV0HiThCh5.initReg(m_cfg, RW, 0x3FF, 10, 20, 131, "HV0HiThCh5"); m_fieldMap["HV0HiThCh5"] = &AMACv2Reg::HV0HiThCh5;
+  HV0HiThCh3.initReg(m_cfg, RW, 0x3FF, 10, 0, 131, "HV0HiThCh3"); m_fieldMap["HV0HiThCh3"] = &AMACv2RegMap::HV0HiThCh3;
+  HV0HiThCh4.initReg(m_cfg, RW, 0x3FF, 10, 10, 131, "HV0HiThCh4"); m_fieldMap["HV0HiThCh4"] = &AMACv2RegMap::HV0HiThCh4;
+  HV0HiThCh5.initReg(m_cfg, RW, 0x3FF, 10, 20, 131, "HV0HiThCh5"); m_fieldMap["HV0HiThCh5"] = &AMACv2RegMap::HV0HiThCh5;
   // 132 - HV0HiTh2
-  HV0HiThCh6.initReg(m_cfg, RW, 0x3FF, 10, 0, 132, "HV0HiThCh6"); m_fieldMap["HV0HiThCh6"] = &AMACv2Reg::HV0HiThCh6;
-  HV0HiThCh7.initReg(m_cfg, RW, 0x3FF, 10, 10, 132, "HV0HiThCh7"); m_fieldMap["HV0HiThCh7"] = &AMACv2Reg::HV0HiThCh7;
-  HV0HiThCh8.initReg(m_cfg, RW, 0x3FF, 10, 20, 132, "HV0HiThCh8"); m_fieldMap["HV0HiThCh8"] = &AMACv2Reg::HV0HiThCh8;
+  HV0HiThCh6.initReg(m_cfg, RW, 0x3FF, 10, 0, 132, "HV0HiThCh6"); m_fieldMap["HV0HiThCh6"] = &AMACv2RegMap::HV0HiThCh6;
+  HV0HiThCh7.initReg(m_cfg, RW, 0x3FF, 10, 10, 132, "HV0HiThCh7"); m_fieldMap["HV0HiThCh7"] = &AMACv2RegMap::HV0HiThCh7;
+  HV0HiThCh8.initReg(m_cfg, RW, 0x3FF, 10, 20, 132, "HV0HiThCh8"); m_fieldMap["HV0HiThCh8"] = &AMACv2RegMap::HV0HiThCh8;
   // 133 - HV0HiTh3
-  HV0HiThCh9.initReg(m_cfg, RW, 0x3FF, 10, 0, 133, "HV0HiThCh9"); m_fieldMap["HV0HiThCh9"] = &AMACv2Reg::HV0HiThCh9;
-  HV0HiThCh10.initReg(m_cfg, RW, 0x3FF, 10, 10, 133, "HV0HiThCh10"); m_fieldMap["HV0HiThCh10"] = &AMACv2Reg::HV0HiThCh10;
-  HV0HiThCh11.initReg(m_cfg, RW, 0x3FF, 10, 20, 133, "HV0HiThCh11"); m_fieldMap["HV0HiThCh11"] = &AMACv2Reg::HV0HiThCh11;
+  HV0HiThCh9.initReg(m_cfg, RW, 0x3FF, 10, 0, 133, "HV0HiThCh9"); m_fieldMap["HV0HiThCh9"] = &AMACv2RegMap::HV0HiThCh9;
+  HV0HiThCh10.initReg(m_cfg, RW, 0x3FF, 10, 10, 133, "HV0HiThCh10"); m_fieldMap["HV0HiThCh10"] = &AMACv2RegMap::HV0HiThCh10;
+  HV0HiThCh11.initReg(m_cfg, RW, 0x3FF, 10, 20, 133, "HV0HiThCh11"); m_fieldMap["HV0HiThCh11"] = &AMACv2RegMap::HV0HiThCh11;
   // 134 - HV0HiTh4
-  HV0HiThCh12.initReg(m_cfg, RW, 0x3FF, 10, 0, 134, "HV0HiThCh12"); m_fieldMap["HV0HiThCh12"] = &AMACv2Reg::HV0HiThCh12;
-  HV0HiThCh13.initReg(m_cfg, RW, 0x3FF, 10, 10, 134, "HV0HiThCh13"); m_fieldMap["HV0HiThCh13"] = &AMACv2Reg::HV0HiThCh13;
-  HV0HiThCh14.initReg(m_cfg, RW, 0x3FF, 10, 20, 134, "HV0HiThCh14"); m_fieldMap["HV0HiThCh14"] = &AMACv2Reg::HV0HiThCh14;
+  HV0HiThCh12.initReg(m_cfg, RW, 0x3FF, 10, 0, 134, "HV0HiThCh12"); m_fieldMap["HV0HiThCh12"] = &AMACv2RegMap::HV0HiThCh12;
+  HV0HiThCh13.initReg(m_cfg, RW, 0x3FF, 10, 10, 134, "HV0HiThCh13"); m_fieldMap["HV0HiThCh13"] = &AMACv2RegMap::HV0HiThCh13;
+  HV0HiThCh14.initReg(m_cfg, RW, 0x3FF, 10, 20, 134, "HV0HiThCh14"); m_fieldMap["HV0HiThCh14"] = &AMACv2RegMap::HV0HiThCh14;
   // 135 - HV0HiTh5
-  HV0HiThCh15.initReg(m_cfg, RW, 0x3FF, 10, 0, 135, "HV0HiThCh15"); m_fieldMap["HV0HiThCh15"] = &AMACv2Reg::HV0HiThCh15;
+  HV0HiThCh15.initReg(m_cfg, RW, 0x3FF, 10, 0, 135, "HV0HiThCh15"); m_fieldMap["HV0HiThCh15"] = &AMACv2RegMap::HV0HiThCh15;
   // 136 - HV2LoTh0
-  HV2LoThCh0.initReg(m_cfg, RW, 0, 10, 0, 136, "HV2LoThCh0"); m_fieldMap["HV2LoThCh0"] = &AMACv2Reg::HV2LoThCh0;
-  HV2LoThCh1.initReg(m_cfg, RW, 0, 10, 10, 136, "HV2LoThCh1"); m_fieldMap["HV2LoThCh1"] = &AMACv2Reg::HV2LoThCh1;
-  HV2LoThCh2.initReg(m_cfg, RW, 0, 10, 20, 136, "HV2LoThCh2"); m_fieldMap["HV2LoThCh2"] = &AMACv2Reg::HV2LoThCh2;
+  HV2LoThCh0.initReg(m_cfg, RW, 0, 10, 0, 136, "HV2LoThCh0"); m_fieldMap["HV2LoThCh0"] = &AMACv2RegMap::HV2LoThCh0;
+  HV2LoThCh1.initReg(m_cfg, RW, 0, 10, 10, 136, "HV2LoThCh1"); m_fieldMap["HV2LoThCh1"] = &AMACv2RegMap::HV2LoThCh1;
+  HV2LoThCh2.initReg(m_cfg, RW, 0, 10, 20, 136, "HV2LoThCh2"); m_fieldMap["HV2LoThCh2"] = &AMACv2RegMap::HV2LoThCh2;
   // 137 - HV2LoTh1
-  HV2LoThCh3.initReg(m_cfg, RW, 0, 10, 0, 137, "HV2LoThCh3"); m_fieldMap["HV2LoThCh3"] = &AMACv2Reg::HV2LoThCh3;
-  HV2LoThCh4.initReg(m_cfg, RW, 0, 10, 10, 137, "HV2LoThCh4"); m_fieldMap["HV2LoThCh4"] = &AMACv2Reg::HV2LoThCh4;
-  HV2LoThCh5.initReg(m_cfg, RW, 0, 10, 20, 137, "HV2LoThCh5"); m_fieldMap["HV2LoThCh5"] = &AMACv2Reg::HV2LoThCh5;
+  HV2LoThCh3.initReg(m_cfg, RW, 0, 10, 0, 137, "HV2LoThCh3"); m_fieldMap["HV2LoThCh3"] = &AMACv2RegMap::HV2LoThCh3;
+  HV2LoThCh4.initReg(m_cfg, RW, 0, 10, 10, 137, "HV2LoThCh4"); m_fieldMap["HV2LoThCh4"] = &AMACv2RegMap::HV2LoThCh4;
+  HV2LoThCh5.initReg(m_cfg, RW, 0, 10, 20, 137, "HV2LoThCh5"); m_fieldMap["HV2LoThCh5"] = &AMACv2RegMap::HV2LoThCh5;
   // 138 - HV2LoTh2
-  HV2LoThCh6.initReg(m_cfg, RW, 0, 10, 0, 138, "HV2LoThCh6"); m_fieldMap["HV2LoThCh6"] = &AMACv2Reg::HV2LoThCh6;
-  HV2LoThCh7.initReg(m_cfg, RW, 0, 10, 10, 138, "HV2LoThCh7"); m_fieldMap["HV2LoThCh7"] = &AMACv2Reg::HV2LoThCh7;
-  HV2LoThCh8.initReg(m_cfg, RW, 0, 10, 20, 138, "HV2LoThCh8"); m_fieldMap["HV2LoThCh8"] = &AMACv2Reg::HV2LoThCh8;
+  HV2LoThCh6.initReg(m_cfg, RW, 0, 10, 0, 138, "HV2LoThCh6"); m_fieldMap["HV2LoThCh6"] = &AMACv2RegMap::HV2LoThCh6;
+  HV2LoThCh7.initReg(m_cfg, RW, 0, 10, 10, 138, "HV2LoThCh7"); m_fieldMap["HV2LoThCh7"] = &AMACv2RegMap::HV2LoThCh7;
+  HV2LoThCh8.initReg(m_cfg, RW, 0, 10, 20, 138, "HV2LoThCh8"); m_fieldMap["HV2LoThCh8"] = &AMACv2RegMap::HV2LoThCh8;
   // 139 - HV2LoTh3
-  HV2LoThCh9.initReg(m_cfg, RW, 0, 10, 0, 139, "HV2LoThCh9"); m_fieldMap["HV2LoThCh9"] = &AMACv2Reg::HV2LoThCh9;
-  HV2LoThCh10.initReg(m_cfg, RW, 0, 10, 10, 139, "HV2LoThCh10"); m_fieldMap["HV2LoThCh10"] = &AMACv2Reg::HV2LoThCh10;
-  HV2LoThCh11.initReg(m_cfg, RW, 0, 10, 20, 139, "HV2LoThCh11"); m_fieldMap["HV2LoThCh11"] = &AMACv2Reg::HV2LoThCh11;
+  HV2LoThCh9.initReg(m_cfg, RW, 0, 10, 0, 139, "HV2LoThCh9"); m_fieldMap["HV2LoThCh9"] = &AMACv2RegMap::HV2LoThCh9;
+  HV2LoThCh10.initReg(m_cfg, RW, 0, 10, 10, 139, "HV2LoThCh10"); m_fieldMap["HV2LoThCh10"] = &AMACv2RegMap::HV2LoThCh10;
+  HV2LoThCh11.initReg(m_cfg, RW, 0, 10, 20, 139, "HV2LoThCh11"); m_fieldMap["HV2LoThCh11"] = &AMACv2RegMap::HV2LoThCh11;
   // 140 - HV2LoTh4
-  HV2LoThCh12.initReg(m_cfg, RW, 0, 10, 0, 140, "HV2LoThCh12"); m_fieldMap["HV2LoThCh12"] = &AMACv2Reg::HV2LoThCh12;
-  HV2LoThCh13.initReg(m_cfg, RW, 0, 10, 10, 140, "HV2LoThCh13"); m_fieldMap["HV2LoThCh13"] = &AMACv2Reg::HV2LoThCh13;
-  HV2LoThCh14.initReg(m_cfg, RW, 0, 10, 20, 140, "HV2LoThCh14"); m_fieldMap["HV2LoThCh14"] = &AMACv2Reg::HV2LoThCh14;
+  HV2LoThCh12.initReg(m_cfg, RW, 0, 10, 0, 140, "HV2LoThCh12"); m_fieldMap["HV2LoThCh12"] = &AMACv2RegMap::HV2LoThCh12;
+  HV2LoThCh13.initReg(m_cfg, RW, 0, 10, 10, 140, "HV2LoThCh13"); m_fieldMap["HV2LoThCh13"] = &AMACv2RegMap::HV2LoThCh13;
+  HV2LoThCh14.initReg(m_cfg, RW, 0, 10, 20, 140, "HV2LoThCh14"); m_fieldMap["HV2LoThCh14"] = &AMACv2RegMap::HV2LoThCh14;
   // 141 - HV2LoTh5
-  HV2LoThCh15.initReg(m_cfg, RW, 0, 10, 0, 141, "HV2LoThCh15"); m_fieldMap["HV2LoThCh15"] = &AMACv2Reg::HV2LoThCh15;
+  HV2LoThCh15.initReg(m_cfg, RW, 0, 10, 0, 141, "HV2LoThCh15"); m_fieldMap["HV2LoThCh15"] = &AMACv2RegMap::HV2LoThCh15;
   // 142 - HV2HiTh0
-  HV2HiThCh0.initReg(m_cfg, RW, 0x3FF, 10, 0, 142, "HV2LoThCh0"); m_fieldMap["HV2LoThCh0"] = &AMACv2Reg::HV2LoThCh0;
-  HV2HiThCh1.initReg(m_cfg, RW, 0x3FF, 10, 10, 142, "HV2LoThCh1"); m_fieldMap["HV2LoThCh1"] = &AMACv2Reg::HV2LoThCh1;
-  HV2HiThCh2.initReg(m_cfg, RW, 0x3FF, 10, 20, 142, "HV2LoThCh2"); m_fieldMap["HV2LoThCh2"] = &AMACv2Reg::HV2LoThCh2;
+  HV2HiThCh0.initReg(m_cfg, RW, 0x3FF, 10, 0, 142, "HV2LoThCh0"); m_fieldMap["HV2LoThCh0"] = &AMACv2RegMap::HV2LoThCh0;
+  HV2HiThCh1.initReg(m_cfg, RW, 0x3FF, 10, 10, 142, "HV2LoThCh1"); m_fieldMap["HV2LoThCh1"] = &AMACv2RegMap::HV2LoThCh1;
+  HV2HiThCh2.initReg(m_cfg, RW, 0x3FF, 10, 20, 142, "HV2LoThCh2"); m_fieldMap["HV2LoThCh2"] = &AMACv2RegMap::HV2LoThCh2;
   // 143 - HV2HiTh1
-  HV2HiThCh3.initReg(m_cfg, RW, 0x3FF, 10, 0, 143, "HV2HiThCh3"); m_fieldMap["HV2HiThCh3"] = &AMACv2Reg::HV2HiThCh3;
-  HV2HiThCh4.initReg(m_cfg, RW, 0x3FF, 10, 10, 143, "HV2HiThCh4"); m_fieldMap["HV2HiThCh4"] = &AMACv2Reg::HV2HiThCh4;
-  HV2HiThCh5.initReg(m_cfg, RW, 0x3FF, 10, 20, 143, "HV2HiThCh5"); m_fieldMap["HV2HiThCh5"] = &AMACv2Reg::HV2HiThCh5;
+  HV2HiThCh3.initReg(m_cfg, RW, 0x3FF, 10, 0, 143, "HV2HiThCh3"); m_fieldMap["HV2HiThCh3"] = &AMACv2RegMap::HV2HiThCh3;
+  HV2HiThCh4.initReg(m_cfg, RW, 0x3FF, 10, 10, 143, "HV2HiThCh4"); m_fieldMap["HV2HiThCh4"] = &AMACv2RegMap::HV2HiThCh4;
+  HV2HiThCh5.initReg(m_cfg, RW, 0x3FF, 10, 20, 143, "HV2HiThCh5"); m_fieldMap["HV2HiThCh5"] = &AMACv2RegMap::HV2HiThCh5;
   // 144 - HV2HiTh2
-  HV2HiThCh6.initReg(m_cfg, RW, 0x3FF, 10, 0, 144, "HV2HiThCh6"); m_fieldMap["HV2HiThCh6"] = &AMACv2Reg::HV2HiThCh6;
-  HV2HiThCh7.initReg(m_cfg, RW, 0x3FF, 10, 10, 144, "HV2HiThCh7"); m_fieldMap["HV2HiThCh7"] = &AMACv2Reg::HV2HiThCh7;
-  HV2HiThCh8.initReg(m_cfg, RW, 0x3FF, 10, 20, 144, "HV2HiThCh8"); m_fieldMap["HV2HiThCh8"] = &AMACv2Reg::HV2HiThCh8;
+  HV2HiThCh6.initReg(m_cfg, RW, 0x3FF, 10, 0, 144, "HV2HiThCh6"); m_fieldMap["HV2HiThCh6"] = &AMACv2RegMap::HV2HiThCh6;
+  HV2HiThCh7.initReg(m_cfg, RW, 0x3FF, 10, 10, 144, "HV2HiThCh7"); m_fieldMap["HV2HiThCh7"] = &AMACv2RegMap::HV2HiThCh7;
+  HV2HiThCh8.initReg(m_cfg, RW, 0x3FF, 10, 20, 144, "HV2HiThCh8"); m_fieldMap["HV2HiThCh8"] = &AMACv2RegMap::HV2HiThCh8;
   // 145 - HV2HiTh3
-  HV2HiThCh9.initReg(m_cfg, RW, 0x3FF, 10, 0, 145, "HV2HiThCh9"); m_fieldMap["HV2HiThCh9"] = &AMACv2Reg::HV2HiThCh9;
-  HV2HiThCh10.initReg(m_cfg, RW, 0x3FF, 10, 10, 145, "HV2HiThCh10"); m_fieldMap["HV2HiThCh10"] = &AMACv2Reg::HV2HiThCh10;
-  HV2HiThCh11.initReg(m_cfg, RW, 0x3FF, 10, 20, 145, "HV2HiThCh11"); m_fieldMap["HV2HiThCh11"] = &AMACv2Reg::HV2HiThCh11;
+  HV2HiThCh9.initReg(m_cfg, RW, 0x3FF, 10, 0, 145, "HV2HiThCh9"); m_fieldMap["HV2HiThCh9"] = &AMACv2RegMap::HV2HiThCh9;
+  HV2HiThCh10.initReg(m_cfg, RW, 0x3FF, 10, 10, 145, "HV2HiThCh10"); m_fieldMap["HV2HiThCh10"] = &AMACv2RegMap::HV2HiThCh10;
+  HV2HiThCh11.initReg(m_cfg, RW, 0x3FF, 10, 20, 145, "HV2HiThCh11"); m_fieldMap["HV2HiThCh11"] = &AMACv2RegMap::HV2HiThCh11;
   // 146 - HV2HiTh4
-  HV2HiThCh12.initReg(m_cfg, RW, 0x3FF, 10, 0, 146, "HV2HiThCh12"); m_fieldMap["HV2HiThCh12"] = &AMACv2Reg::HV2HiThCh12;
-  HV2HiThCh13.initReg(m_cfg, RW, 0x3FF, 10, 10, 146, "HV2HiThCh13"); m_fieldMap["HV2HiThCh13"] = &AMACv2Reg::HV2HiThCh13;
-  HV2HiThCh14.initReg(m_cfg, RW, 0x3FF, 10, 20, 146, "HV2HiThCh14"); m_fieldMap["HV2HiThCh14"] = &AMACv2Reg::HV2HiThCh14;
+  HV2HiThCh12.initReg(m_cfg, RW, 0x3FF, 10, 0, 146, "HV2HiThCh12"); m_fieldMap["HV2HiThCh12"] = &AMACv2RegMap::HV2HiThCh12;
+  HV2HiThCh13.initReg(m_cfg, RW, 0x3FF, 10, 10, 146, "HV2HiThCh13"); m_fieldMap["HV2HiThCh13"] = &AMACv2RegMap::HV2HiThCh13;
+  HV2HiThCh14.initReg(m_cfg, RW, 0x3FF, 10, 20, 146, "HV2HiThCh14"); m_fieldMap["HV2HiThCh14"] = &AMACv2RegMap::HV2HiThCh14;
   // 147 - HV2HiTh5
-  HV2HiThCh15.initReg(m_cfg, RW, 0x3FF, 10, 0, 147, "HV2HiThCh15"); m_fieldMap["HV2HiThCh15"] = &AMACv2Reg::HV2HiThCh15;
+  HV2HiThCh15.initReg(m_cfg, RW, 0x3FF, 10, 0, 147, "HV2HiThCh15"); m_fieldMap["HV2HiThCh15"] = &AMACv2RegMap::HV2HiThCh15;
   // 148 - DCDCLoTh0
-  DCDCLoThCh0.initReg(m_cfg, RW, 0, 10, 0, 148, "DCDCLoThCh0"); m_fieldMap["DCDCLoThCh0"] = &AMACv2Reg::DCDCLoThCh0;
-  DCDCLoThCh1.initReg(m_cfg, RW, 0, 10, 10, 148, "DCDCLoThCh1"); m_fieldMap["DCDCLoThCh1"] = &AMACv2Reg::DCDCLoThCh1;
-  DCDCLoThCh2.initReg(m_cfg, RW, 0, 10, 20, 148, "DCDCLoThCh2"); m_fieldMap["DCDCLoThCh2"] = &AMACv2Reg::DCDCLoThCh2;
+  DCDCLoThCh0.initReg(m_cfg, RW, 0, 10, 0, 148, "DCDCLoThCh0"); m_fieldMap["DCDCLoThCh0"] = &AMACv2RegMap::DCDCLoThCh0;
+  DCDCLoThCh1.initReg(m_cfg, RW, 0, 10, 10, 148, "DCDCLoThCh1"); m_fieldMap["DCDCLoThCh1"] = &AMACv2RegMap::DCDCLoThCh1;
+  DCDCLoThCh2.initReg(m_cfg, RW, 0, 10, 20, 148, "DCDCLoThCh2"); m_fieldMap["DCDCLoThCh2"] = &AMACv2RegMap::DCDCLoThCh2;
   // 149 - DCDCLoTh1
-  DCDCLoThCh3.initReg(m_cfg, RW, 0, 10, 0, 149, "DCDCLoThCh3"); m_fieldMap["DCDCLoThCh3"] = &AMACv2Reg::DCDCLoThCh3;
-  DCDCLoThCh4.initReg(m_cfg, RW, 0, 10, 10, 149, "DCDCLoThCh4"); m_fieldMap["DCDCLoThCh4"] = &AMACv2Reg::DCDCLoThCh4;
-  DCDCLoThCh5.initReg(m_cfg, RW, 0, 10, 20, 149, "DCDCLoThCh5"); m_fieldMap["DCDCLoThCh5"] = &AMACv2Reg::DCDCLoThCh5;
+  DCDCLoThCh3.initReg(m_cfg, RW, 0, 10, 0, 149, "DCDCLoThCh3"); m_fieldMap["DCDCLoThCh3"] = &AMACv2RegMap::DCDCLoThCh3;
+  DCDCLoThCh4.initReg(m_cfg, RW, 0, 10, 10, 149, "DCDCLoThCh4"); m_fieldMap["DCDCLoThCh4"] = &AMACv2RegMap::DCDCLoThCh4;
+  DCDCLoThCh5.initReg(m_cfg, RW, 0, 10, 20, 149, "DCDCLoThCh5"); m_fieldMap["DCDCLoThCh5"] = &AMACv2RegMap::DCDCLoThCh5;
   // 150 - DCDCLoTh2
-  DCDCLoThCh6.initReg(m_cfg, RW, 0, 10, 0, 150, "DCDCLoThCh6"); m_fieldMap["DCDCLoThCh6"] = &AMACv2Reg::DCDCLoThCh6;
-  DCDCLoThCh7.initReg(m_cfg, RW, 0, 10, 10, 150, "DCDCLoThCh7"); m_fieldMap["DCDCLoThCh7"] = &AMACv2Reg::DCDCLoThCh7;
-  DCDCLoThCh8.initReg(m_cfg, RW, 0, 10, 20, 150, "DCDCLoThCh8"); m_fieldMap["DCDCLoThCh8"] = &AMACv2Reg::DCDCLoThCh8;
+  DCDCLoThCh6.initReg(m_cfg, RW, 0, 10, 0, 150, "DCDCLoThCh6"); m_fieldMap["DCDCLoThCh6"] = &AMACv2RegMap::DCDCLoThCh6;
+  DCDCLoThCh7.initReg(m_cfg, RW, 0, 10, 10, 150, "DCDCLoThCh7"); m_fieldMap["DCDCLoThCh7"] = &AMACv2RegMap::DCDCLoThCh7;
+  DCDCLoThCh8.initReg(m_cfg, RW, 0, 10, 20, 150, "DCDCLoThCh8"); m_fieldMap["DCDCLoThCh8"] = &AMACv2RegMap::DCDCLoThCh8;
   // 151 - DCDCLoTh3
-  DCDCLoThCh9.initReg(m_cfg, RW, 0, 10, 0, 151, "DCDCLoThCh9"); m_fieldMap["DCDCLoThCh9"] = &AMACv2Reg::DCDCLoThCh9;
-  DCDCLoThCh10.initReg(m_cfg, RW, 0, 10, 10, 151, "DCDCLoThCh10"); m_fieldMap["DCDCLoThCh10"] = &AMACv2Reg::DCDCLoThCh10;
-  DCDCLoThCh11.initReg(m_cfg, RW, 0, 10, 20, 151, "DCDCLoThCh11"); m_fieldMap["DCDCLoThCh11"] = &AMACv2Reg::DCDCLoThCh11;
+  DCDCLoThCh9.initReg(m_cfg, RW, 0, 10, 0, 151, "DCDCLoThCh9"); m_fieldMap["DCDCLoThCh9"] = &AMACv2RegMap::DCDCLoThCh9;
+  DCDCLoThCh10.initReg(m_cfg, RW, 0, 10, 10, 151, "DCDCLoThCh10"); m_fieldMap["DCDCLoThCh10"] = &AMACv2RegMap::DCDCLoThCh10;
+  DCDCLoThCh11.initReg(m_cfg, RW, 0, 10, 20, 151, "DCDCLoThCh11"); m_fieldMap["DCDCLoThCh11"] = &AMACv2RegMap::DCDCLoThCh11;
   // 152 - DCDCLoTh4
-  DCDCLoThCh12.initReg(m_cfg, RW, 0, 10, 0, 152, "DCDCLoThCh12"); m_fieldMap["DCDCLoThCh12"] = &AMACv2Reg::DCDCLoThCh12;
-  DCDCLoThCh13.initReg(m_cfg, RW, 0, 10, 10, 152, "DCDCLoThCh13"); m_fieldMap["DCDCLoThCh13"] = &AMACv2Reg::DCDCLoThCh13;
-  DCDCLoThCh14.initReg(m_cfg, RW, 0, 10, 20, 152, "DCDCLoThCh14"); m_fieldMap["DCDCLoThCh14"] = &AMACv2Reg::DCDCLoThCh14;
+  DCDCLoThCh12.initReg(m_cfg, RW, 0, 10, 0, 152, "DCDCLoThCh12"); m_fieldMap["DCDCLoThCh12"] = &AMACv2RegMap::DCDCLoThCh12;
+  DCDCLoThCh13.initReg(m_cfg, RW, 0, 10, 10, 152, "DCDCLoThCh13"); m_fieldMap["DCDCLoThCh13"] = &AMACv2RegMap::DCDCLoThCh13;
+  DCDCLoThCh14.initReg(m_cfg, RW, 0, 10, 20, 152, "DCDCLoThCh14"); m_fieldMap["DCDCLoThCh14"] = &AMACv2RegMap::DCDCLoThCh14;
   // 153 - DCDCLoTh5
-  DCDCLoThCh15.initReg(m_cfg, RW, 0, 10, 0, 153, "DCDCLoThCh15"); m_fieldMap["DCDCLoThCh15"] = &AMACv2Reg::DCDCLoThCh15;
+  DCDCLoThCh15.initReg(m_cfg, RW, 0, 10, 0, 153, "DCDCLoThCh15"); m_fieldMap["DCDCLoThCh15"] = &AMACv2RegMap::DCDCLoThCh15;
   // 154 - DCDCHiTh0
-  DCDCHiThCh0.initReg(m_cfg, RW, 0x3FF, 10, 0, 154, "DCDCLoThCh0"); m_fieldMap["DCDCLoThCh0"] = &AMACv2Reg::DCDCLoThCh0;
-  DCDCHiThCh1.initReg(m_cfg, RW, 0x3FF, 10, 10, 154, "DCDCLoThCh1"); m_fieldMap["DCDCLoThCh1"] = &AMACv2Reg::DCDCLoThCh1;
-  DCDCHiThCh2.initReg(m_cfg, RW, 0x3FF, 10, 20, 154, "DCDCLoThCh2"); m_fieldMap["DCDCLoThCh2"] = &AMACv2Reg::DCDCLoThCh2;
+  DCDCHiThCh0.initReg(m_cfg, RW, 0x3FF, 10, 0, 154, "DCDCLoThCh0"); m_fieldMap["DCDCLoThCh0"] = &AMACv2RegMap::DCDCLoThCh0;
+  DCDCHiThCh1.initReg(m_cfg, RW, 0x3FF, 10, 10, 154, "DCDCLoThCh1"); m_fieldMap["DCDCLoThCh1"] = &AMACv2RegMap::DCDCLoThCh1;
+  DCDCHiThCh2.initReg(m_cfg, RW, 0x3FF, 10, 20, 154, "DCDCLoThCh2"); m_fieldMap["DCDCLoThCh2"] = &AMACv2RegMap::DCDCLoThCh2;
   // 155 - DCDCHiTh1
-  DCDCHiThCh3.initReg(m_cfg, RW, 0x3FF, 10, 0, 155, "DCDCHiThCh3"); m_fieldMap["DCDCHiThCh3"] = &AMACv2Reg::DCDCHiThCh3;
-  DCDCHiThCh4.initReg(m_cfg, RW, 0x3FF, 10, 10, 155, "DCDCHiThCh4"); m_fieldMap["DCDCHiThCh4"] = &AMACv2Reg::DCDCHiThCh4;
-  DCDCHiThCh5.initReg(m_cfg, RW, 0x3FF, 10, 20, 155, "DCDCHiThCh5"); m_fieldMap["DCDCHiThCh5"] = &AMACv2Reg::DCDCHiThCh5;
+  DCDCHiThCh3.initReg(m_cfg, RW, 0x3FF, 10, 0, 155, "DCDCHiThCh3"); m_fieldMap["DCDCHiThCh3"] = &AMACv2RegMap::DCDCHiThCh3;
+  DCDCHiThCh4.initReg(m_cfg, RW, 0x3FF, 10, 10, 155, "DCDCHiThCh4"); m_fieldMap["DCDCHiThCh4"] = &AMACv2RegMap::DCDCHiThCh4;
+  DCDCHiThCh5.initReg(m_cfg, RW, 0x3FF, 10, 20, 155, "DCDCHiThCh5"); m_fieldMap["DCDCHiThCh5"] = &AMACv2RegMap::DCDCHiThCh5;
   // 156 - DCDCHiTh2
-  DCDCHiThCh6.initReg(m_cfg, RW, 0x3FF, 10, 0, 156, "DCDCHiThCh6"); m_fieldMap["DCDCHiThCh6"] = &AMACv2Reg::DCDCHiThCh6;
-  DCDCHiThCh7.initReg(m_cfg, RW, 0x3FF, 10, 10, 156, "DCDCHiThCh7"); m_fieldMap["DCDCHiThCh7"] = &AMACv2Reg::DCDCHiThCh7;
-  DCDCHiThCh8.initReg(m_cfg, RW, 0x3FF, 10, 20, 156, "DCDCHiThCh8"); m_fieldMap["DCDCHiThCh8"] = &AMACv2Reg::DCDCHiThCh8;
+  DCDCHiThCh6.initReg(m_cfg, RW, 0x3FF, 10, 0, 156, "DCDCHiThCh6"); m_fieldMap["DCDCHiThCh6"] = &AMACv2RegMap::DCDCHiThCh6;
+  DCDCHiThCh7.initReg(m_cfg, RW, 0x3FF, 10, 10, 156, "DCDCHiThCh7"); m_fieldMap["DCDCHiThCh7"] = &AMACv2RegMap::DCDCHiThCh7;
+  DCDCHiThCh8.initReg(m_cfg, RW, 0x3FF, 10, 20, 156, "DCDCHiThCh8"); m_fieldMap["DCDCHiThCh8"] = &AMACv2RegMap::DCDCHiThCh8;
   // 157 - DCDCHiTh3
-  DCDCHiThCh9.initReg(m_cfg, RW, 0x3FF, 10, 0, 157, "DCDCHiThCh9"); m_fieldMap["DCDCHiThCh9"] = &AMACv2Reg::DCDCHiThCh9;
-  DCDCHiThCh10.initReg(m_cfg, RW, 0x3FF, 10, 10, 157, "DCDCHiThCh10"); m_fieldMap["DCDCHiThCh10"] = &AMACv2Reg::DCDCHiThCh10;
-  DCDCHiThCh11.initReg(m_cfg, RW, 0x3FF, 10, 20, 157, "DCDCHiThCh11"); m_fieldMap["DCDCHiThCh11"] = &AMACv2Reg::DCDCHiThCh11;
+  DCDCHiThCh9.initReg(m_cfg, RW, 0x3FF, 10, 0, 157, "DCDCHiThCh9"); m_fieldMap["DCDCHiThCh9"] = &AMACv2RegMap::DCDCHiThCh9;
+  DCDCHiThCh10.initReg(m_cfg, RW, 0x3FF, 10, 10, 157, "DCDCHiThCh10"); m_fieldMap["DCDCHiThCh10"] = &AMACv2RegMap::DCDCHiThCh10;
+  DCDCHiThCh11.initReg(m_cfg, RW, 0x3FF, 10, 20, 157, "DCDCHiThCh11"); m_fieldMap["DCDCHiThCh11"] = &AMACv2RegMap::DCDCHiThCh11;
   // 158 - DCDCHiTh4
-  DCDCHiThCh12.initReg(m_cfg, RW, 0x3FF, 10, 0, 158, "DCDCHiThCh12"); m_fieldMap["DCDCHiThCh12"] = &AMACv2Reg::DCDCHiThCh12;
-  DCDCHiThCh13.initReg(m_cfg, RW, 0x3FF, 10, 10, 158, "DCDCHiThCh13"); m_fieldMap["DCDCHiThCh13"] = &AMACv2Reg::DCDCHiThCh13;
-  DCDCHiThCh14.initReg(m_cfg, RW, 0x3FF, 10, 20, 158, "DCDCHiThCh14"); m_fieldMap["DCDCHiThCh14"] = &AMACv2Reg::DCDCHiThCh14;
+  DCDCHiThCh12.initReg(m_cfg, RW, 0x3FF, 10, 0, 158, "DCDCHiThCh12"); m_fieldMap["DCDCHiThCh12"] = &AMACv2RegMap::DCDCHiThCh12;
+  DCDCHiThCh13.initReg(m_cfg, RW, 0x3FF, 10, 10, 158, "DCDCHiThCh13"); m_fieldMap["DCDCHiThCh13"] = &AMACv2RegMap::DCDCHiThCh13;
+  DCDCHiThCh14.initReg(m_cfg, RW, 0x3FF, 10, 20, 158, "DCDCHiThCh14"); m_fieldMap["DCDCHiThCh14"] = &AMACv2RegMap::DCDCHiThCh14;
   // 159 - DCDCHiTh5
-  DCDCHiThCh15.initReg(m_cfg, RW, 0x3FF, 10, 0, 159, "DCDCHiThCh15"); m_fieldMap["DCDCHiThCh15"] = &AMACv2Reg::DCDCHiThCh15;
+  DCDCHiThCh15.initReg(m_cfg, RW, 0x3FF, 10, 0, 159, "DCDCHiThCh15"); m_fieldMap["DCDCHiThCh15"] = &AMACv2RegMap::DCDCHiThCh15;
   // 160 - WRNLoTh0
-  WRNLoThCh0.initReg(m_cfg, RW, 0, 10, 0, 160, "WRNLoThCh0"); m_fieldMap["WRNLoThCh0"] = &AMACv2Reg::WRNLoThCh0;
-  WRNLoThCh1.initReg(m_cfg, RW, 0, 10, 10, 160, "WRNLoThCh1"); m_fieldMap["WRNLoThCh1"] = &AMACv2Reg::WRNLoThCh1;
-  WRNLoThCh2.initReg(m_cfg, RW, 0, 10, 20, 160, "WRNLoThCh2"); m_fieldMap["WRNLoThCh2"] = &AMACv2Reg::WRNLoThCh2;
+  WRNLoThCh0.initReg(m_cfg, RW, 0, 10, 0, 160, "WRNLoThCh0"); m_fieldMap["WRNLoThCh0"] = &AMACv2RegMap::WRNLoThCh0;
+  WRNLoThCh1.initReg(m_cfg, RW, 0, 10, 10, 160, "WRNLoThCh1"); m_fieldMap["WRNLoThCh1"] = &AMACv2RegMap::WRNLoThCh1;
+  WRNLoThCh2.initReg(m_cfg, RW, 0, 10, 20, 160, "WRNLoThCh2"); m_fieldMap["WRNLoThCh2"] = &AMACv2RegMap::WRNLoThCh2;
   // 161 - WRNLoTh1
-  WRNLoThCh3.initReg(m_cfg, RW, 0, 10, 0, 161, "WRNLoThCh3"); m_fieldMap["WRNLoThCh3"] = &AMACv2Reg::WRNLoThCh3;
-  WRNLoThCh4.initReg(m_cfg, RW, 0, 10, 10, 161, "WRNLoThCh4"); m_fieldMap["WRNLoThCh4"] = &AMACv2Reg::WRNLoThCh4;
-  WRNLoThCh5.initReg(m_cfg, RW, 0, 10, 20, 161, "WRNLoThCh5"); m_fieldMap["WRNLoThCh5"] = &AMACv2Reg::WRNLoThCh5;
+  WRNLoThCh3.initReg(m_cfg, RW, 0, 10, 0, 161, "WRNLoThCh3"); m_fieldMap["WRNLoThCh3"] = &AMACv2RegMap::WRNLoThCh3;
+  WRNLoThCh4.initReg(m_cfg, RW, 0, 10, 10, 161, "WRNLoThCh4"); m_fieldMap["WRNLoThCh4"] = &AMACv2RegMap::WRNLoThCh4;
+  WRNLoThCh5.initReg(m_cfg, RW, 0, 10, 20, 161, "WRNLoThCh5"); m_fieldMap["WRNLoThCh5"] = &AMACv2RegMap::WRNLoThCh5;
   // 162 - WRNLoTh2
-  WRNLoThCh6.initReg(m_cfg, RW, 0, 10, 0, 162, "WRNLoThCh6"); m_fieldMap["WRNLoThCh6"] = &AMACv2Reg::WRNLoThCh6;
-  WRNLoThCh7.initReg(m_cfg, RW, 0, 10, 10, 162, "WRNLoThCh7"); m_fieldMap["WRNLoThCh7"] = &AMACv2Reg::WRNLoThCh7;
-  WRNLoThCh8.initReg(m_cfg, RW, 0, 10, 20, 162, "WRNLoThCh8"); m_fieldMap["WRNLoThCh8"] = &AMACv2Reg::WRNLoThCh8;
+  WRNLoThCh6.initReg(m_cfg, RW, 0, 10, 0, 162, "WRNLoThCh6"); m_fieldMap["WRNLoThCh6"] = &AMACv2RegMap::WRNLoThCh6;
+  WRNLoThCh7.initReg(m_cfg, RW, 0, 10, 10, 162, "WRNLoThCh7"); m_fieldMap["WRNLoThCh7"] = &AMACv2RegMap::WRNLoThCh7;
+  WRNLoThCh8.initReg(m_cfg, RW, 0, 10, 20, 162, "WRNLoThCh8"); m_fieldMap["WRNLoThCh8"] = &AMACv2RegMap::WRNLoThCh8;
   // 163 - WRNLoTh3
-  WRNLoThCh9.initReg(m_cfg, RW, 0, 10, 0, 163, "WRNLoThCh9"); m_fieldMap["WRNLoThCh9"] = &AMACv2Reg::WRNLoThCh9;
-  WRNLoThCh10.initReg(m_cfg, RW, 0, 10, 10, 163, "WRNLoThCh10"); m_fieldMap["WRNLoThCh10"] = &AMACv2Reg::WRNLoThCh10;
-  WRNLoThCh11.initReg(m_cfg, RW, 0, 10, 20, 163, "WRNLoThCh11"); m_fieldMap["WRNLoThCh11"] = &AMACv2Reg::WRNLoThCh11;
+  WRNLoThCh9.initReg(m_cfg, RW, 0, 10, 0, 163, "WRNLoThCh9"); m_fieldMap["WRNLoThCh9"] = &AMACv2RegMap::WRNLoThCh9;
+  WRNLoThCh10.initReg(m_cfg, RW, 0, 10, 10, 163, "WRNLoThCh10"); m_fieldMap["WRNLoThCh10"] = &AMACv2RegMap::WRNLoThCh10;
+  WRNLoThCh11.initReg(m_cfg, RW, 0, 10, 20, 163, "WRNLoThCh11"); m_fieldMap["WRNLoThCh11"] = &AMACv2RegMap::WRNLoThCh11;
   // 164 - WRNLoTh4
-  WRNLoThCh12.initReg(m_cfg, RW, 0, 10, 0, 164, "WRNLoThCh12"); m_fieldMap["WRNLoThCh12"] = &AMACv2Reg::WRNLoThCh12;
-  WRNLoThCh13.initReg(m_cfg, RW, 0, 10, 10, 164, "WRNLoThCh13"); m_fieldMap["WRNLoThCh13"] = &AMACv2Reg::WRNLoThCh13;
-  WRNLoThCh14.initReg(m_cfg, RW, 0, 10, 20, 164, "WRNLoThCh14"); m_fieldMap["WRNLoThCh14"] = &AMACv2Reg::WRNLoThCh14;
+  WRNLoThCh12.initReg(m_cfg, RW, 0, 10, 0, 164, "WRNLoThCh12"); m_fieldMap["WRNLoThCh12"] = &AMACv2RegMap::WRNLoThCh12;
+  WRNLoThCh13.initReg(m_cfg, RW, 0, 10, 10, 164, "WRNLoThCh13"); m_fieldMap["WRNLoThCh13"] = &AMACv2RegMap::WRNLoThCh13;
+  WRNLoThCh14.initReg(m_cfg, RW, 0, 10, 20, 164, "WRNLoThCh14"); m_fieldMap["WRNLoThCh14"] = &AMACv2RegMap::WRNLoThCh14;
   // 165 - WRNLoTh5
-  WRNLoThCh15.initReg(m_cfg, RW, 0, 10, 0, 165, "WRNLoThCh15"); m_fieldMap["WRNLoThCh15"] = &AMACv2Reg::WRNLoThCh15;
+  WRNLoThCh15.initReg(m_cfg, RW, 0, 10, 0, 165, "WRNLoThCh15"); m_fieldMap["WRNLoThCh15"] = &AMACv2RegMap::WRNLoThCh15;
   // 166 - WRNHiTh0
-  WRNHiThCh0.initReg(m_cfg, RW, 0x3FF, 10, 0, 166, "WRNLoThCh0"); m_fieldMap["WRNLoThCh0"] = &AMACv2Reg::WRNLoThCh0;
-  WRNHiThCh1.initReg(m_cfg, RW, 0x3FF, 10, 10, 166, "WRNLoThCh1"); m_fieldMap["WRNLoThCh1"] = &AMACv2Reg::WRNLoThCh1;
-  WRNHiThCh2.initReg(m_cfg, RW, 0x3FF, 10, 20, 166, "WRNLoThCh2"); m_fieldMap["WRNLoThCh2"] = &AMACv2Reg::WRNLoThCh2;
+  WRNHiThCh0.initReg(m_cfg, RW, 0x3FF, 10, 0, 166, "WRNLoThCh0"); m_fieldMap["WRNLoThCh0"] = &AMACv2RegMap::WRNLoThCh0;
+  WRNHiThCh1.initReg(m_cfg, RW, 0x3FF, 10, 10, 166, "WRNLoThCh1"); m_fieldMap["WRNLoThCh1"] = &AMACv2RegMap::WRNLoThCh1;
+  WRNHiThCh2.initReg(m_cfg, RW, 0x3FF, 10, 20, 166, "WRNLoThCh2"); m_fieldMap["WRNLoThCh2"] = &AMACv2RegMap::WRNLoThCh2;
   // 167 - WRNHiTh1
-  WRNHiThCh3.initReg(m_cfg, RW, 0x3FF, 10, 0, 167, "WRNHiThCh3"); m_fieldMap["WRNHiThCh3"] = &AMACv2Reg::WRNHiThCh3;
-  WRNHiThCh4.initReg(m_cfg, RW, 0x3FF, 10, 10, 167, "WRNHiThCh4"); m_fieldMap["WRNHiThCh4"] = &AMACv2Reg::WRNHiThCh4;
-  WRNHiThCh5.initReg(m_cfg, RW, 0x3FF, 10, 20, 167, "WRNHiThCh5"); m_fieldMap["WRNHiThCh5"] = &AMACv2Reg::WRNHiThCh5;
+  WRNHiThCh3.initReg(m_cfg, RW, 0x3FF, 10, 0, 167, "WRNHiThCh3"); m_fieldMap["WRNHiThCh3"] = &AMACv2RegMap::WRNHiThCh3;
+  WRNHiThCh4.initReg(m_cfg, RW, 0x3FF, 10, 10, 167, "WRNHiThCh4"); m_fieldMap["WRNHiThCh4"] = &AMACv2RegMap::WRNHiThCh4;
+  WRNHiThCh5.initReg(m_cfg, RW, 0x3FF, 10, 20, 167, "WRNHiThCh5"); m_fieldMap["WRNHiThCh5"] = &AMACv2RegMap::WRNHiThCh5;
   // 168 - WRNHiTh2
-  WRNHiThCh6.initReg(m_cfg, RW, 0x3FF, 10, 0, 168, "WRNHiThCh6"); m_fieldMap["WRNHiThCh6"] = &AMACv2Reg::WRNHiThCh6;
-  WRNHiThCh7.initReg(m_cfg, RW, 0x3FF, 10, 10, 168, "WRNHiThCh7"); m_fieldMap["WRNHiThCh7"] = &AMACv2Reg::WRNHiThCh7;
-  WRNHiThCh8.initReg(m_cfg, RW, 0x3FF, 10, 20, 168, "WRNHiThCh8"); m_fieldMap["WRNHiThCh8"] = &AMACv2Reg::WRNHiThCh8;
+  WRNHiThCh6.initReg(m_cfg, RW, 0x3FF, 10, 0, 168, "WRNHiThCh6"); m_fieldMap["WRNHiThCh6"] = &AMACv2RegMap::WRNHiThCh6;
+  WRNHiThCh7.initReg(m_cfg, RW, 0x3FF, 10, 10, 168, "WRNHiThCh7"); m_fieldMap["WRNHiThCh7"] = &AMACv2RegMap::WRNHiThCh7;
+  WRNHiThCh8.initReg(m_cfg, RW, 0x3FF, 10, 20, 168, "WRNHiThCh8"); m_fieldMap["WRNHiThCh8"] = &AMACv2RegMap::WRNHiThCh8;
   // 169 - WRNHiTh3
-  WRNHiThCh9.initReg(m_cfg, RW, 0x3FF, 10, 0, 169, "WRNHiThCh9"); m_fieldMap["WRNHiThCh9"] = &AMACv2Reg::WRNHiThCh9;
-  WRNHiThCh10.initReg(m_cfg, RW, 0x3FF, 10, 10, 169, "WRNHiThCh10"); m_fieldMap["WRNHiThCh10"] = &AMACv2Reg::WRNHiThCh10;
-  WRNHiThCh11.initReg(m_cfg, RW, 0x3FF, 10, 20, 169, "WRNHiThCh11"); m_fieldMap["WRNHiThCh11"] = &AMACv2Reg::WRNHiThCh11;
+  WRNHiThCh9.initReg(m_cfg, RW, 0x3FF, 10, 0, 169, "WRNHiThCh9"); m_fieldMap["WRNHiThCh9"] = &AMACv2RegMap::WRNHiThCh9;
+  WRNHiThCh10.initReg(m_cfg, RW, 0x3FF, 10, 10, 169, "WRNHiThCh10"); m_fieldMap["WRNHiThCh10"] = &AMACv2RegMap::WRNHiThCh10;
+  WRNHiThCh11.initReg(m_cfg, RW, 0x3FF, 10, 20, 169, "WRNHiThCh11"); m_fieldMap["WRNHiThCh11"] = &AMACv2RegMap::WRNHiThCh11;
   // 170 - WRNHiTh4
-  WRNHiThCh12.initReg(m_cfg, RW, 0x3FF, 10, 0, 170, "WRNHiThCh12"); m_fieldMap["WRNHiThCh12"] = &AMACv2Reg::WRNHiThCh12;
-  WRNHiThCh13.initReg(m_cfg, RW, 0x3FF, 10, 10, 170, "WRNHiThCh13"); m_fieldMap["WRNHiThCh13"] = &AMACv2Reg::WRNHiThCh13;
-  WRNHiThCh14.initReg(m_cfg, RW, 0x3FF, 10, 20, 170, "WRNHiThCh14"); m_fieldMap["WRNHiThCh14"] = &AMACv2Reg::WRNHiThCh14;
+  WRNHiThCh12.initReg(m_cfg, RW, 0x3FF, 10, 0, 170, "WRNHiThCh12"); m_fieldMap["WRNHiThCh12"] = &AMACv2RegMap::WRNHiThCh12;
+  WRNHiThCh13.initReg(m_cfg, RW, 0x3FF, 10, 10, 170, "WRNHiThCh13"); m_fieldMap["WRNHiThCh13"] = &AMACv2RegMap::WRNHiThCh13;
+  WRNHiThCh14.initReg(m_cfg, RW, 0x3FF, 10, 20, 170, "WRNHiThCh14"); m_fieldMap["WRNHiThCh14"] = &AMACv2RegMap::WRNHiThCh14;
   // 171 - WRNHiTh5
-  WRNHiThCh15.initReg(m_cfg, RW, 0x3FF, 10, 0, 171, "WRNHiThCh15"); m_fieldMap["WRNHiThCh15"] = &AMACv2Reg::WRNHiThCh15;
+  WRNHiThCh15.initReg(m_cfg, RW, 0x3FF, 10, 0, 171, "WRNHiThCh15"); m_fieldMap["WRNHiThCh15"] = &AMACv2RegMap::WRNHiThCh15;
 }
 
-std::vector<const AMACv2Field*> AMACv2Reg::getFields() const
+std::vector<const AMACv2Field*> AMACv2RegMap::getFields() const
 {
   std::vector<const AMACv2Field*> fields;
   fields.reserve(m_fieldMap.size());
@@ -831,12 +740,12 @@ std::vector<const AMACv2Field*> AMACv2Reg::getFields() const
   return fields;
 }
 
-AMACv2Field* AMACv2Reg::findField(AMACv2Field AMACv2Reg::* ref)
+AMACv2Field* AMACv2RegMap::findField(AMACv2Field AMACv2RegMap::* ref)
 {
   return &(this->*ref);
 }
 
-AMACv2Field* AMACv2Reg::findField(const std::string& fieldName)
+AMACv2Field* AMACv2RegMap::findField(const std::string& fieldName)
 {
   if(m_fieldMap.find(fieldName) != m_fieldMap.end())
     return &(this->*m_fieldMap[fieldName]);
@@ -844,12 +753,12 @@ AMACv2Field* AMACv2Reg::findField(const std::string& fieldName)
   return nullptr;
 }
 
-uint32_t AMACv2Reg::getField(AMACv2Field AMACv2Reg::* ref)
+uint32_t AMACv2RegMap::getField(AMACv2Field AMACv2RegMap::* ref)
 {
   return (this->*ref).read();
 }
 
-uint32_t AMACv2Reg::getField(const std::string& fieldName)
+uint32_t AMACv2RegMap::getField(const std::string& fieldName)
 {
   if(m_fieldMap.find(fieldName) != m_fieldMap.end())
     return(this->*m_fieldMap[fieldName]).read();
@@ -858,7 +767,7 @@ uint32_t AMACv2Reg::getField(const std::string& fieldName)
   return 0;
 }
 
-uint32_t AMACv2Reg::getReg(uint32_t reg)
+uint32_t AMACv2RegMap::getReg(uint32_t reg)
 {
   if(reg<numRegs)
     return m_cfg[reg];
@@ -866,12 +775,12 @@ uint32_t AMACv2Reg::getReg(uint32_t reg)
     return 0;
 }
 
-uint32_t AMACv2Reg::getReg(AMACv2Field AMACv2Reg::* ref)
+uint32_t AMACv2RegMap::getReg(AMACv2Field AMACv2RegMap::* ref)
 {
   return (this->*ref).readRaw();
 }
 
-uint32_t AMACv2Reg::getReg(const std::string& fieldName)
+uint32_t AMACv2RegMap::getReg(const std::string& fieldName)
 {
   if(m_fieldMap.find(fieldName) != m_fieldMap.end())
     return(this->*m_fieldMap[fieldName]).readRaw();
@@ -880,12 +789,12 @@ uint32_t AMACv2Reg::getReg(const std::string& fieldName)
   return 0;
 }
 
-void AMACv2Reg::setField(AMACv2Field AMACv2Reg::* ref, uint32_t value)
+void AMACv2RegMap::setField(AMACv2Field AMACv2RegMap::* ref, uint32_t value)
 {
   (this->*ref).write(value);
 }
 
-void AMACv2Reg::setField(const std::string& fieldName, uint32_t value)
+void AMACv2RegMap::setField(const std::string& fieldName, uint32_t value)
 {
   if(m_fieldMap.find(fieldName) != m_fieldMap.end())
     return(this->*m_fieldMap[fieldName]).write(value);
@@ -894,22 +803,22 @@ void AMACv2Reg::setField(const std::string& fieldName, uint32_t value)
   return;
 }
 
-void AMACv2Reg::setReg(uint32_t reg, uint32_t value)
+void AMACv2RegMap::setReg(uint32_t reg, uint32_t value)
 {
   m_cfg[reg]=value;
 }
 
-void AMACv2Reg::setReg(AMACv2Field AMACv2Reg::* ref, uint32_t value)
+void AMACv2RegMap::setReg(AMACv2Field AMACv2RegMap::* ref, uint32_t value)
 {
   (this->*ref).writeRaw(value);
 }
 
-uint8_t AMACv2Reg::getAddr(AMACv2Field AMACv2Reg::* ref)
+uint8_t AMACv2RegMap::getAddr(AMACv2Field AMACv2RegMap::* ref)
 {
   return (this->*ref).addr();
 }
 
-uint8_t AMACv2Reg::getAddr(const std::string& fieldName)
+uint8_t AMACv2RegMap::getAddr(const std::string& fieldName)
 {
   if(m_fieldMap.find(fieldName) != m_fieldMap.end())
     return (this->*m_fieldMap[fieldName]).addr();
@@ -919,7 +828,7 @@ uint8_t AMACv2Reg::getAddr(const std::string& fieldName)
 }
 
 
-bool AMACv2Reg::canBeWritten(AMACv2Field AMACv2Reg::* ref)
+bool AMACv2RegMap::canBeWritten(AMACv2Field AMACv2RegMap::* ref)
 {
   return (this->*ref).canBeWrittenField();
 }
diff --git a/pbv3/AMACv2Reg.h b/pbv3/AMACv2RegMap.h
similarity index 86%
rename from pbv3/AMACv2Reg.h
rename to pbv3/AMACv2RegMap.h
index 87e4e7bb..7e7a0041 100644
--- a/pbv3/AMACv2Reg.h
+++ b/pbv3/AMACv2RegMap.h
@@ -1,5 +1,5 @@
-#ifndef AMACREG_H
-#define AMACREG_H
+#ifndef AMACREGMAP_H
+#define AMACREGMAP_H
 
 #include <memory>
 #include <unordered_map>
@@ -8,87 +8,43 @@
 #include <stdint.h>
 #include <string>
 
+#include "AMACv2Field.h"
 
-enum rw_t {RO, WO, RW};
-
-class AMACv2Field
-{
- private:
-  uint32_t *m_cfg = nullptr;
-  rw_t m_rw = RO;
-  uint32_t m_defaultVal = 0;
-  uint8_t m_width = 0;
-  uint8_t m_offset = 0;
-  uint8_t m_regNbr = 0;
-  uint32_t m_mask = 0;
-  std::string m_fieldName = "";
- public:
-  AMACv2Field();
-
-  bool canBeWrittenField() const;
-  bool canBeReadField() const;
-  bool isReadWrite() const;
-
-  /** Get field name
-   * \return name of the field
-   */
-  std::string getFieldName() const;
-
-  /** Get field width
-   * \return width of field in bytes
-   */
-  uint8_t getWidth() const;
-		
-  void initReg(uint32_t* cfg, rw_t rw, uint32_t defaultVal, uint8_t width, uint8_t offset, uint8_t regNbr, const std::string& fieldName);
-
-  void setDefaultVal(uint32_t defaultVal);
-  void writeDefaultVal();
-
-  uint32_t read() const;
-  uint32_t readRaw() const;
-
-  void write(const uint32_t& cfgBits);		
-  void writeRaw(const uint32_t& cfgBits);
-
-  uint8_t addr() const;
-};
-
-class AMACv2Reg
+//! \brief AMACv2 register map
+/**
+ * Contains definition of all fields and registers inside AMAC
+ */
+class AMACv2RegMap
 {
 private:
   void init();
 
 public:
-  //! Map of register address to RW status
-  static const std::unordered_map<uint32_t, rw_t> Registers;
-
-
-  uint32_t m_cfg[numRegs];
-
-  AMACv2Reg();
+  AMACv2RegMap();
 
-  std::vector<const AMACv2Field*> getFields() const;
+  std::vector<const AMACv2Register*> getRegisters() const;
+  std::vector<const AMACv2Field*   > getFields() const;
 
-  AMACv2Field* findField(AMACv2Field AMACv2Reg::* ref);
+  AMACv2Field* findField(AMACv2Field AMACv2RegMap::* ref);
   AMACv2Field* findField(const std::string& fieldName);
 
-  uint32_t getField(AMACv2Field AMACv2Reg::* ref);
+  uint32_t getField(AMACv2Field AMACv2RegMap::* ref);
   uint32_t getField(const std::string& fieldName);
 
   uint32_t getReg(uint32_t reg);
-  uint32_t getReg(AMACv2Field AMACv2Reg::* ref);
+  uint32_t getReg(AMACv2Field AMACv2RegMap::* ref);
   uint32_t getReg(const std::string& fieldName);
 
-  void setField(AMACv2Field AMACv2Reg::* ref, uint32_t value);
+  void setField(AMACv2Field AMACv2RegMap::* ref, uint32_t value);
   void setField(const std::string& fieldName, uint32_t value);
 
   void setReg(uint32_t reg, uint32_t value);
-  void setReg(AMACv2Field AMACv2Reg::* ref, uint32_t value);
+  void setReg(AMACv2Field AMACv2RegMap::* ref, uint32_t value);
 
-  uint8_t getAddr(AMACv2Field AMACv2Reg::* ref);
+  uint8_t getAddr(AMACv2Field AMACv2RegMap::* ref);
   uint8_t getAddr(const std::string& fieldName);
 
-  bool canBeWritten(AMACv2Field AMACv2Reg::* ref);
+  bool canBeWritten(AMACv2Field AMACv2RegMap::* ref);
 
   // 0 - Status register
   AMACv2Field StatusAM;
@@ -662,6 +618,6 @@ public:
   AMACv2Field WRNHiThCh15;
 
 protected:
-  std::unordered_map<std::string, AMACv2Field AMACv2Reg::*> m_fieldMap;
+  std::unordered_map<std::string, AMACv2Field AMACv2RegMap::*> m_fieldMap;
 };
-#endif //AMACREG_H
+#endif //AMACREGMAP_H
diff --git a/pbv3/AMACv2Register.cpp b/pbv3/AMACv2Register.cpp
new file mode 100644
index 00000000..e69de29b
diff --git a/pbv3/AMACv2Register.h b/pbv3/AMACv2Register.h
new file mode 100644
index 00000000..e6834920
--- /dev/null
+++ b/pbv3/AMACv2Register.h
@@ -0,0 +1,22 @@
+#ifndef AMACV2REGISTER_H
+#define AMACV2REGISTER_H
+
+enum rw_t {RO=1, WO=2, RW=3};
+
+//! \brief Description of an AMACv2 register
+class AMACv2Register
+{
+ public:
+  //! Helpful name for register
+  std::string name;
+
+  //! Register address
+  uint8_t address;
+  //! Register value
+  uint32_t value;
+
+  //! Read/write mode
+  rw_t rw;
+};
+
+#endif // AMACV2REGISTER_H
diff --git a/pbv3/CMakeLists.txt b/pbv3/CMakeLists.txt
index 8bdc2a37..501cc28b 100644
--- a/pbv3/CMakeLists.txt
+++ b/pbv3/CMakeLists.txt
@@ -20,7 +20,9 @@ target_sources(PBv3
   EndeavourComException.cpp
 
   AMACv2.cpp
-  AMACv2Reg.cpp
+  AMACv2Field.cpp
+  AMACv2Register.cpp
+  AMACv2RegMap.cpp
 
   PBv3TestTools.cpp
   PBv3ConfigTools.cpp
-- 
GitLab


From 712a575279fd1e2a5d4823c48d26ed92c889bd37 Mon Sep 17 00:00:00 2001
From: Karol Krizka <kkrizka@gmail.com>
Date: Mon, 24 Aug 2020 21:18:29 -0700
Subject: [PATCH 18/29] AMACv2Field now points to AMACv2Register.

---
 pbv3/AMACv2.cpp                       |   30 +-
 pbv3/AMACv2Field.cpp                  |   69 +-
 pbv3/AMACv2Field.h                    |   30 +-
 pbv3/AMACv2RegMap.cpp                 | 1089 ++++++++----------------
 pbv3/AMACv2RegMap.h                   | 1100 ++++++++++++++-----------
 pbv3/AMACv2Register.cpp               |   20 +
 pbv3/AMACv2Register.h                 |   39 +-
 pbv3/PBv3ConfigTools.cpp              |  172 ++--
 pbv3/PBv3ConfigTools.h                |    2 +-
 pbv3/PBv3TestTools.cpp                |  402 ++++-----
 pbv3/PBv3TestTools.h                  |    2 +-
 pbv3/tools/pbv3_active_fancy_load.cpp |   16 +-
 pbv3/tools/pbv3_field.cpp             |    2 +-
 pbv3/tools/pbv3_print_status.cpp      |    4 +-
 pbv3/tools/pbv3_readADC.cpp           |    8 +-
 15 files changed, 1388 insertions(+), 1597 deletions(-)

diff --git a/pbv3/AMACv2.cpp b/pbv3/AMACv2.cpp
index bf00dcb6..3c84cac0 100644
--- a/pbv3/AMACv2.cpp
+++ b/pbv3/AMACv2.cpp
@@ -26,32 +26,32 @@ void AMACv2::init()
 void AMACv2::initRegisters()
 { 
   // Initialize registers with default values
-  for(auto fieldKV : m_fieldMap)
+  for(AMACv2Field AMACv2RegMap::* field : m_fields)
     {
-      if((this->*fieldKV.second).canBeWrittenField())
-	(this->*fieldKV.second).writeDefaultVal();
+      if((this->*field).canBeWrittenField())
+	(this->*field).writeDefaultVal();
     }
 
   // Write AMAC registers into the chip
-  for(const std::pair<uint32_t, rw_t>& reg : AMACv2RegMap::Registers)
+  for(const AMACv2Register *reg : getRegisters())
     {
-      if(reg.second!=RW)
+      if(reg->isRW()!=RW)
 	continue;
 
-      EndeavourCom::write_reg(reg.first, getReg(reg.first));
+      EndeavourCom::write_reg(reg->getAddress(), getReg(reg->getAddress()));
     }
 }
 
 void AMACv2::loadRegisters()
 { 
   // Load register map with current values
-  for(const std::pair<uint32_t, rw_t>& reg : AMACv2RegMap::Registers)
+  for(const AMACv2Register *reg : getRegisters())
     {
-      if(reg.second!=RW && reg.second!=RO)
+      if(reg->isRW()!=RW && reg->isRW()!=RO)
 	continue;
 
-      uint32_t value=EndeavourCom::read_reg(reg.first);
-      setReg(reg.first, value);
+      uint32_t value=EndeavourCom::read_reg(reg->getAddress());
+      setReg(reg->getAddress(), value);
     }
 }
 
@@ -66,21 +66,21 @@ bool AMACv2::isCommIDSet()
 
 void AMACv2::syncReg(AMACv2Field AMACv2RegMap::* ref)
 {
-  EndeavourCom::write_reg(getAddr(ref), (this->*ref).readRaw());
+  AMACv2Register *reg=(this->*ref).getRegister();
+  EndeavourCom::write_reg(reg->getAddress(), reg->getValue());
 }
 
 void AMACv2::wrField(AMACv2Field AMACv2RegMap::* ref, uint32_t data)
 {
   setField(ref, data);
-  EndeavourCom::write_reg(getAddr(ref), (this->*ref).readRaw());
+  AMACv2Register *reg=(this->*ref).getRegister();
+  EndeavourCom::write_reg(reg->getAddress(), reg->getValue());
   usleep(1e4);
 }
 
 void AMACv2::wrField(const std::string& fieldName, uint32_t data)
 {
-  setField(fieldName, data);
-  EndeavourCom::write_reg(getAddr(fieldName), getReg(fieldName));
-  usleep(1e4);
+  wrField(m_fieldMap[fieldName], data);
 }
 
 uint32_t AMACv2::rdField(AMACv2Field AMACv2RegMap::* ref)
diff --git a/pbv3/AMACv2Field.cpp b/pbv3/AMACv2Field.cpp
index 2bf5c8df..c30365ec 100644
--- a/pbv3/AMACv2Field.cpp
+++ b/pbv3/AMACv2Field.cpp
@@ -1,37 +1,31 @@
 #include "AMACv2Field.h"
 
-AMACv2Field::AMACv2Field()
-{ }
+AMACv2Field::AMACv2Field(const std::string& fieldName, AMACv2Register *reg, uint8_t offset, uint8_t width, uint32_t defaultVal)
+  : m_fieldName(fieldName), m_register(reg), m_offset(offset), m_width(width), m_defaultVal(defaultVal)
+{
+  m_mask = (uint32_t) (((1 << m_width) - 1) << m_offset);
+  if(reg->isRW() != RO)
+    this->write(m_defaultVal);
+}
 
 bool AMACv2Field::canBeWrittenField() const
-{ return (m_rw != RO); }
+{ return (m_register->isRW() != RO); }
 
 bool AMACv2Field::canBeReadField() const
-{ return (m_rw != WO); }
+{ return (m_register->isRW() != WO); }
 
 bool AMACv2Field::isReadWrite() const
-{ return (m_rw == RW); }
+{ return (m_register->isRW() == RW); }
 
-std::string AMACv2Field::getFieldName() const
+std::string AMACv2Field::getName() const
 { return m_fieldName; }
 
+AMACv2Register* AMACv2Field::getRegister() const
+{ return m_register; }
+
 uint8_t AMACv2Field::getWidth() const
 { return m_width; }
 
-void AMACv2Field::initReg(uint32_t* cfg, rw_t rw, uint32_t defaultVal, uint8_t width, uint8_t offset, uint8_t regNbr, const std::string& fieldName)
-{
-  m_cfg = cfg;
-  m_rw = rw;
-  m_defaultVal = defaultVal;
-  m_width = width;
-  m_offset = offset;
-  m_regNbr = regNbr;
-  m_mask = (uint32_t) (((1 << m_width) - 1) << m_offset);
-  m_fieldName = fieldName;
-  if(m_rw != RO)
-    this->write(m_defaultVal);
-}
-
 void AMACv2Field::setDefaultVal(uint32_t defaultVal)
 {
   m_defaultVal=defaultVal;
@@ -39,7 +33,7 @@ void AMACv2Field::setDefaultVal(uint32_t defaultVal)
 
 void AMACv2Field::writeDefaultVal()
 {
-  if(m_rw == RO)
+  if(m_register->isRW() == RO)
     {
       std::cerr << " --> Error: Read-only register \"" << m_fieldName <<"\""<< std::endl;
       return;
@@ -50,45 +44,24 @@ void AMACv2Field::writeDefaultVal()
 
 void AMACv2Field::write(const uint32_t& cfgBits)
 {
-  if(m_rw == RO)
+  if(m_register->isRW() == RO)
     {
       std::cerr << " --> Error: Read-only register \"" << m_fieldName <<"\""<< std::endl;
       return;
     }
-  m_cfg[m_regNbr] = (m_cfg[m_regNbr]&~m_mask) | ((cfgBits << m_offset) & m_mask);
+  uint32_t value=m_register->getValue();
+  value = (value&~m_mask) | ((cfgBits << m_offset) & m_mask);
+  m_register->setValue(value);
 }
 
 uint32_t AMACv2Field::read() const
 {
-  if(m_rw == WO)
+  if(m_register->isRW() == WO)
     {
       std::cerr << " --> Error: Write-only register \"" << m_fieldName <<"\""<< std::endl;
       return 0;
     }
-  return ((m_cfg[m_regNbr] & m_mask) >> m_offset);
+  return ((m_register->getValue() & m_mask) >> m_offset);
 }
 
-uint32_t AMACv2Field::readRaw() const
-{
-  if(m_rw == WO)
-    {
-      std::cerr << " --> Error: Write-only register \"" << m_fieldName <<"\""<< std::endl;
-      return 0;
-    }
-  return m_cfg[m_regNbr];
-}
-
-void AMACv2Field::writeRaw(const uint32_t& cfgBits)
-{
-  if(m_rw == RO)
-    {
-      std::cerr << " --> Error: Read-only register \"" << m_fieldName <<"\""<< std::endl;
-      return;
-    }
-  m_cfg[m_regNbr] = cfgBits;
-}
-
-uint8_t AMACv2Field::addr() const
-{ return m_regNbr; }
-
 
diff --git a/pbv3/AMACv2Field.h b/pbv3/AMACv2Field.h
index 973cccea..af215261 100644
--- a/pbv3/AMACv2Field.h
+++ b/pbv3/AMACv2Field.h
@@ -1,6 +1,9 @@
 #ifndef AMACV2_FIELD_H
 #define AMACV2_FIELD_H
 
+#include <memory>
+#include <string>
+
 #include "AMACv2Register.h"
 
 //! \brief Definition and manipulation of an AMACv2 register field
@@ -12,7 +15,7 @@ class AMACv2Field
 {
 private:
   //! The whole register
-  std::shared_ptr<AMACv2Register> m_register;
+  AMACv2Register *m_register = nullptr;
 
   //! Default field value
   uint32_t m_defaultVal = 0;
@@ -22,40 +25,39 @@ private:
 
   //! Position of the LSB
   uint8_t m_offset = 0;
-  uint8_t m_regNbr = 0;
+
+  //! Mask for updating register values
   uint32_t m_mask = 0;
 
   //! Name of field
   std::string m_fieldName = "";
 public:
-  AMACv2Field();
+  AMACv2Field(const std::string& fieldName, AMACv2Register *reg, uint8_t offset, uint8_t width, uint32_t defaultVal);
 
   bool canBeWrittenField() const;
   bool canBeReadField() const;
   bool isReadWrite() const;
 
-  /** Get field name
+  //! \brief Get field name
+  /**
    * \return name of the field
    */
-  std::string getFieldName() const;
+  std::string getName() const;
+
+  //! \brief Get underlaying register
+  AMACv2Register* getRegister() const;
 
-  /** Get field width
+  //! \brief Get field width
+  /**
    * \return width of field in bytes
    */
   uint8_t getWidth() const;
 		
-  void initField(std::shared_ptr<AMACv2Register> reg, uint32_t defaultVal, uint8_t width, uint8_t offset, const std::string& fieldName);
-
   void setDefaultVal(uint32_t defaultVal);
   void writeDefaultVal();
 
+  void write(const uint32_t& cfgBits);
   uint32_t read() const;
-  uint32_t readRaw() const;
-
-  void write(const uint32_t& cfgBits);		
-  void writeRaw(const uint32_t& cfgBits);
-
-  uint8_t addr() const;
 };
 
 
diff --git a/pbv3/AMACv2RegMap.cpp b/pbv3/AMACv2RegMap.cpp
index e3ced869..fea3ad14 100644
--- a/pbv3/AMACv2RegMap.cpp
+++ b/pbv3/AMACv2RegMap.cpp
@@ -1,155 +1,6 @@
 #include "AMACv2RegMap.h"
 
-const std::unordered_map<uint32_t, rw_t> AMACv2RegMap::Registers =
-  {
-    {  0, RO},
-    {  1, RO},
-    {  2, RO},
-    {  3, RO},
-    {  4, RO},
-    {  5, RO},
-    {  6, RO},
-    {  7, RO},
-
-    { 10, RO},
-    { 11, RO},
-    { 12, RO},
-    { 13, RO},
-    { 14, RO},
-    { 15, RO},
-
-    { 31, RO},
-
-    { 32, WO},
-    { 33, WO},
-    { 34, WO},
-
-    { 40, RW},
-    { 41, RW},
-    { 42, RW},
-    { 43, RW},
-    { 44, RW},
-    { 45, RW},
-    { 46, RW},
-    { 47, RW},
-    { 48, RW},
-    { 49, RW},
-    { 50, RW},
-    { 51, RW},
-    { 52, RW},
-    { 53, RW},
-    { 54, RW},
-    { 55, RW},
-    { 56, RW},
-    { 57, RW},
-
-    { 60, RW},
-    { 61, RW},
-    { 62, RW},
-    { 63, RW},
-    { 64, RW},
-    { 65, RW},
-
-    { 70, RW},
-    { 71, RW},
-    { 72, RW},
-    { 73, RW},
-    { 74, RW},
-    { 75, RW},
-    { 76, RW},
-    { 77, RW},
-    { 78, RW},
-    { 79, RW},
-    { 80, RW},
-    { 81, RW},
-    { 82, RW},
-    { 83, RW},
-    { 84, RW},
-    { 85, RW},
-    { 86, RW},
-    { 87, RW},
-    { 88, RW},
-    { 89, RW},
-    { 90, RW},
-    { 91, RW},
-    { 92, RW},
-    { 93, RW},
-    { 94, RW},
-    { 95, RW},
-
-    {100, RW},
-    {101, RW},
-    {102, RW},
-    {103, RW},
-    {104, RW},
-    {105, RW},
-    {106, RW},
-    {107, RW},
-    {108, RW},
-    {109, RW},
-    {110, RW},
-    {111, RW},
-    {112, RW},
-    {113, RW},
-    {114, RW},
-    {115, RW},
-    {116, RW},
-    {117, RW},
-    {118, RW},
-    {119, RW},
-    {120, RW},
-    {121, RW},
-    {122, RW},
-    {123, RW},
-    {124, RW},
-    {125, RW},
-    {126, RW},
-    {127, RW},
-    {128, RW},
-    {129, RW},
-    {130, RW},
-    {131, RW},
-    {132, RW},
-    {133, RW},
-    {134, RW},
-    {135, RW},
-    {136, RW},
-    {137, RW},
-    {138, RW},
-    {139, RW},
-    {140, RW},
-    {141, RW},
-    {142, RW},
-    {143, RW},
-    {144, RW},
-    {145, RW},
-    {146, RW},
-    {147, RW},
-    {148, RW},
-    {149, RW},
-    {150, RW},
-    {151, RW},
-    {152, RW},
-    {153, RW},
-    {154, RW},
-    {155, RW},
-    {156, RW},
-    {157, RW},
-    {158, RW},
-    {159, RW},
-    {160, RW},
-    {161, RW},
-    {162, RW},
-    {163, RW},
-    {164, RW},
-    {165, RW},
-    {166, RW},
-    {167, RW},
-    {168, RW},
-    {169, RW},
-    {170, RW},
-    {171, RW}
-  };
+#include <algorithm>
 
 AMACv2RegMap::AMACv2RegMap()
 {
@@ -158,585 +9,349 @@ AMACv2RegMap::AMACv2RegMap()
 
 void AMACv2RegMap::init()
 {
-	
-  for (unsigned int i=0; i<numRegs; i++) m_cfg[i] = 0;
-	
-  StatusAM  .initReg(m_cfg, RO, 0, 1, 31, 0, "StatusAM"  ); m_fieldMap["StatusAM"  ] = &AMACv2RegMap::StatusAM;
-  StatusWARN.initReg(m_cfg, RO, 0, 1, 29, 0, "StatusWARN"); m_fieldMap["StatusWARN"] = &AMACv2RegMap::StatusWARN;
-  StatusDCDC.initReg(m_cfg, RO, 0, 1, 28, 0, "StatusDCDC"); m_fieldMap["StatusDCDC"] = &AMACv2RegMap::StatusDCDC;
-  StatusHV3.initReg(m_cfg, RO, 0, 1, 27, 0, "StatusHV3"); m_fieldMap["StatusHV3"] = &AMACv2RegMap::StatusHV3;
-  StatusHV2.initReg(m_cfg, RO, 0, 1, 26, 0, "StatusHV2"); m_fieldMap["StatusHV2"] = &AMACv2RegMap::StatusHV2;
-  StatusHV1.initReg(m_cfg, RO, 0, 1, 25, 0, "StatusHV1"); m_fieldMap["StatusHV1"] = &AMACv2RegMap::StatusHV1;
-  StatusHV0.initReg(m_cfg, RO, 0, 1, 24, 0, "StatusHV0"); m_fieldMap["StatusHV0"] = &AMACv2RegMap::StatusHV0;
-  StatusY2LDO.initReg(m_cfg, RO, 0, 1, 22, 0, "StatusY2LDO"); m_fieldMap["StatusY2LDO"] = &AMACv2RegMap::StatusY2LDO;
-  StatusY1LDO.initReg(m_cfg, RO, 0, 1, 21, 0, "StatusY1LDO"); m_fieldMap["StatusY1LDO"] = &AMACv2RegMap::StatusY1LDO;
-  StatusY0LDO.initReg(m_cfg, RO, 0, 1, 20, 0, "StatusY0LDO"); m_fieldMap["StatusY0LDO"] = &AMACv2RegMap::StatusY0LDO;
-  StatusX2LDO.initReg(m_cfg, RO, 0, 1, 18, 0, "StatusX2LDO"); m_fieldMap["StatusX2LDO"] = &AMACv2RegMap::StatusX2LDO;
-  StatusX1LDO.initReg(m_cfg, RO, 0, 1, 17, 0, "StatusX1LDO"); m_fieldMap["StatusX1LDO"] = &AMACv2RegMap::StatusX1LDO;
-  StatusX0LDO.initReg(m_cfg, RO, 0, 1, 16, 0, "StatusX0LDO"); m_fieldMap["StatusX0LDO"] = &AMACv2RegMap::StatusX0LDO;
-  StatusGPI.initReg(m_cfg, RO, 0, 1, 12, 0, "StatusGPI"); m_fieldMap["StatusGPI"] = &AMACv2RegMap::StatusGPI;
-  StatusPGOOD.initReg(m_cfg, RO, 0, 1, 8, 0, "StatusPGOOD"); m_fieldMap["StatusPGOOD"] = &AMACv2RegMap::StatusPGOOD;
-  StatusILockWARN.initReg(m_cfg, RO, 0, 1, 5, 0, "StatusILockWARN"); m_fieldMap["StatusILockWARN"] = &AMACv2RegMap::StatusILockWARN;
-  StatusILockDCDC.initReg(m_cfg, RO, 0, 1, 4, 0, "StatusILockDCDC"); m_fieldMap["StatusILockDCDC"] = &AMACv2RegMap::StatusILockDCDC;
-  StatusILockHV2.initReg(m_cfg, RO, 0, 1, 3, 0, "StatusILockHV2"); m_fieldMap["StatusILockHV2"] = &AMACv2RegMap::StatusILockHV2;
-  StatusILockHV2.initReg(m_cfg, RO, 0, 1, 2, 0, "StatusILockHV2"); m_fieldMap["StatusILockHV2"] = &AMACv2RegMap::StatusILockHV2;
-  StatusILockYLDO.initReg(m_cfg, RO, 0, 1, 1, 0, "StatusILockYLDO"); m_fieldMap["StatusILockYLDO"] = &AMACv2RegMap::StatusILockYLDO;
-  StatusILockxLDO.initReg(m_cfg, RO, 0, 1, 0, 0, "StatusILockxLDO"); m_fieldMap["StatusILockxLDO"] = &AMACv2RegMap::StatusILockxLDO;
-  // 1 - HxFlags
-  HxFlagsHi.initReg(m_cfg, RO, 0, 16, 16, 1, "HxFlagsHi"); m_fieldMap["HxFlagsHi"] = &AMACv2RegMap::HxFlagsHi;
-  HxFlagsLo.initReg(m_cfg, RO, 0, 16, 0, 1, "HxFlagsLo"); m_fieldMap["HxFlagsLo"] = &AMACv2RegMap::HxFlagsLo;
-  // 2 - HyFlags
-  HyFlagsHi.initReg(m_cfg, RO, 0, 16, 16, 2, "HyFlagsHi"); m_fieldMap["HyFlagsHi"] = &AMACv2RegMap::HyFlagsHi;
-  HyFlagsLo.initReg(m_cfg, RO, 0, 16, 0, 2, "HyFlagsLo"); m_fieldMap["HyFlagsLo"] = &AMACv2RegMap::HyFlagsLo;
-  // 3 - HV0Flags
-  HV0FlagsHi.initReg(m_cfg, RO, 0, 16, 16, 3, "HV0FlagsHi"); m_fieldMap["HV0FlagsHi"] = &AMACv2RegMap::HV0FlagsHi;
-  HV0FlagsLo.initReg(m_cfg, RO, 0, 16, 0, 3, "HV0FlagsLo"); m_fieldMap["HV0FlagsLo"] = &AMACv2RegMap::HV0FlagsLo;
-  // 4 - HV2Flags
-  HV2FlagsHi.initReg(m_cfg, RO, 0, 16, 16, 4, "HV2FlagsHi"); m_fieldMap["HV2FlagsHi"] = &AMACv2RegMap::HV2FlagsHi;
-  HV2FlagsLo.initReg(m_cfg, RO, 0, 16, 0, 4, "HV2FlagsLo"); m_fieldMap["HV2FlagsLo"] = &AMACv2RegMap::HV2FlagsLo;
-  // 5 - DCDCflags
-  DCDCflagsHi.initReg(m_cfg, RO, 0, 16, 16, 5, "DCDCflagsHi"); m_fieldMap["DCDCflagsHi"] = &AMACv2RegMap::DCDCflagsHi;
-  DCDCflagsLo.initReg(m_cfg, RO, 0, 16, 0, 5, "DCDCflagsLo"); m_fieldMap["DCDCflagsLo"] = &AMACv2RegMap::DCDCflagsLo;
-  // 6 - WRNflags
-  WRNflagsHi.initReg(m_cfg, RO, 0, 16, 16, 6, "WRNflagsHi"); m_fieldMap["WRNflagsHi"] = &AMACv2RegMap::WRNflagsHi;
-  WRNflagsLo.initReg(m_cfg, RO, 0, 16, 0, 6, "WRNflagsLo"); m_fieldMap["WRNflagsLo"] = &AMACv2RegMap::WRNflagsLo;
-  // 7 - SynFlags
-  SynFlagsWRN.initReg(m_cfg, RO, 0, 2, 20, 7, "SynFlagsWRN"); m_fieldMap["SynFlagsWRN"] = &AMACv2RegMap::SynFlagsWRN;
-  SynFlagsDCDC.initReg(m_cfg, RO, 0, 2, 16, 7, "SynFlagsDCDC"); m_fieldMap["SynFlagsDCDC"] = &AMACv2RegMap::SynFlagsDCDC;
-  SynFlagsHV2.initReg(m_cfg, RO, 0, 2, 12, 7, "SynFlagsHV2"); m_fieldMap["SynFlagsHV2"] = &AMACv2RegMap::SynFlagsHV2;
-  SynFlagsHV2.initReg(m_cfg, RO, 0, 2, 8, 7, "SynFlagsHV2"); m_fieldMap["SynFlagsHV2"] = &AMACv2RegMap::SynFlagsHV2;
-  SynFlagsHy.initReg(m_cfg, RO, 0, 2, 4, 7, "SynFlagsHy"); m_fieldMap["SynFlagsHy"] = &AMACv2RegMap::SynFlagsHy;
-  SynFlagsHx.initReg(m_cfg, RO, 0, 2, 0, 7, "SynFlagsHx"); m_fieldMap["SynFlagsHx"] = &AMACv2RegMap::SynFlagsHx;
-  // 10 - Value0
-  Value0AMen.initReg(m_cfg, RO, 0, 1, 31, 10, "Value0AMen"); m_fieldMap["Value0AMen"] = &AMACv2RegMap::Value0AMen;
-  Ch0Value.initReg(m_cfg, RO, 0, 10, 0, 10, "Ch0Value"); m_fieldMap["Ch0Value"] = &AMACv2RegMap::Ch0Value;
-  Ch1Value.initReg(m_cfg, RO, 0, 10, 10, 10, "Ch1Value"); m_fieldMap["Ch1Value"] = &AMACv2RegMap::Ch1Value;
-  Ch2Value.initReg(m_cfg, RO, 0, 10, 20, 10, "Ch2Value"); m_fieldMap["Ch2Value"] = &AMACv2RegMap::Ch2Value;
-  // 11 - Value1
-  Value1AMen.initReg(m_cfg, RO, 0, 1, 31, 11, "Value1AMen"); m_fieldMap["Value1AMen"] = &AMACv2RegMap::Value1AMen;
-  Ch3Value.initReg(m_cfg, RO, 0, 10, 0, 11, "Ch3Value"); m_fieldMap["Ch3Value"] = &AMACv2RegMap::Ch3Value;
-  Ch4Value.initReg(m_cfg, RO, 0, 10, 10, 11, "Ch4Value"); m_fieldMap["Ch4Value"] = &AMACv2RegMap::Ch4Value;
-  Ch5Value.initReg(m_cfg, RO, 0, 10, 20, 11, "Ch5Value"); m_fieldMap["Ch5Value"] = &AMACv2RegMap::Ch5Value;
-  // 12 - Value2
-  Value2AMen.initReg(m_cfg, RO, 0, 1, 31, 12, "Value2AMen"); m_fieldMap["Value2AMen"] = &AMACv2RegMap::Value2AMen;
-  Ch6Value.initReg(m_cfg, RO, 0, 10, 0, 12, "Ch6Value"); m_fieldMap["Ch6Value"] = &AMACv2RegMap::Ch6Value;
-  Ch7Value.initReg(m_cfg, RO, 0, 10, 10, 12, "Ch7Value"); m_fieldMap["Ch7Value"] = &AMACv2RegMap::Ch7Value;
-  Ch8Value.initReg(m_cfg, RO, 0, 10, 20, 12, "Ch8Value"); m_fieldMap["Ch8Value"] = &AMACv2RegMap::Ch8Value;
-  // 13 - Value3
-  Value3AMen.initReg(m_cfg, RO, 0, 1, 31, 13, "Value3AMen"); m_fieldMap["Value3AMen"] = &AMACv2RegMap::Value3AMen;
-  Ch9Value.initReg(m_cfg, RO, 0, 10, 0, 13, "Ch9Value"); m_fieldMap["Ch9Value"] = &AMACv2RegMap::Ch9Value;
-  Ch10Value.initReg(m_cfg, RO, 0, 10, 10, 13, "Ch10Value"); m_fieldMap["Ch10Value"] = &AMACv2RegMap::Ch10Value;
-  Ch11Value.initReg(m_cfg, RO, 0, 10, 20, 13, "Ch11Value"); m_fieldMap["Ch11Value"] = &AMACv2RegMap::Ch11Value;
-  // 14 - Value4
-  Value4AMen.initReg(m_cfg, RO, 0, 1, 31, 14, "Value4AMen"); m_fieldMap["Value4AMen"] = &AMACv2RegMap::Value4AMen;
-  Ch12Value.initReg(m_cfg, RO, 0, 10, 0, 14, "Ch12Value"); m_fieldMap["Ch12Value"] = &AMACv2RegMap::Ch12Value;
-  Ch13Value.initReg(m_cfg, RO, 0, 10, 10, 14, "Ch13Value"); m_fieldMap["Ch13Value"] = &AMACv2RegMap::Ch13Value;
-  Ch14Value.initReg(m_cfg, RO, 0, 10, 20, 14, "Ch14Value"); m_fieldMap["Ch14Value"] = &AMACv2RegMap::Ch14Value;
-  // 15 - Value5
-  Value5AMen.initReg(m_cfg, RO, 0, 1, 31, 15, "Value5AMen"); m_fieldMap["Value5AMen"] = &AMACv2RegMap::Value5AMen;
-  Ch15Value.initReg(m_cfg, RO, 0, 10, 0, 15, "Ch15Value"); m_fieldMap["Ch15Value"] = &AMACv2RegMap::Ch15Value;
-  // 31 - SerNum
-  PadID.initReg(m_cfg, RO, 0, 5, 24, 31, "PadID"); m_fieldMap["PadID"] = &AMACv2RegMap::PadID;
-  SerNum.initReg(m_cfg, RO, 0, 16, 0, 31, "SerNum"); m_fieldMap["SerNum"] = &AMACv2RegMap::SerNum;
-  // 32 - FlagResets
-  FlagResetWRN.initReg(m_cfg, WO, 0, 1, 5, 32, "FlagResetWRN"); m_fieldMap["FlagResetWRN"] = &AMACv2RegMap::FlagResetWRN;
-  FlagResetDCDC.initReg(m_cfg, WO, 0, 1, 4, 32, "FlagResetDCDC"); m_fieldMap["FlagResetDCDC"] = &AMACv2RegMap::FlagResetDCDC;
-  FlagResetHV2.initReg(m_cfg, WO, 0, 1, 3, 32, "FlagResetHV2"); m_fieldMap["FlagResetHV2"] = &AMACv2RegMap::FlagResetHV2;
-  FlagResetHV0.initReg(m_cfg, WO, 0, 1, 2, 32, "FlagResetHV0"); m_fieldMap["FlagResetHV0"] = &AMACv2RegMap::FlagResetHV0;
-  FlagResetXLDO.initReg(m_cfg, WO, 0, 1, 1, 32, "FlagResetXLDO"); m_fieldMap["FlagResetXLDO"] = &AMACv2RegMap::FlagResetXLDO;
-  FlagResetYLDO.initReg(m_cfg, WO, 0, 1, 0, 32, "FlagResetYLDO"); m_fieldMap["FlagResetYLDO"] = &AMACv2RegMap::FlagResetYLDO;
-  // 33 - LogicReset
-  LogicReset.initReg(m_cfg, WO, 0, 32, 0, 33, "LogicReset"); m_fieldMap["LogicReset"] = &AMACv2RegMap::LogicReset;
-  // 34 - HardReset
-  HardReset.initReg(m_cfg, WO, 0, 32, 0, 34, "HardReset"); m_fieldMap["HardReset"] = &AMACv2RegMap::HardReset;
-  // 40 - CntSet
-  CntSetHV3frq.initReg(m_cfg, RW, 3, 2, 29, 40, "CntSetHV3frq"); m_fieldMap["CntSetHV3frq"] = &AMACv2RegMap::CntSetHV3frq;
-  CntSetHV3en.initReg(m_cfg, RW, 0, 1, 28, 40, "CntSetHV3en"); m_fieldMap["CntSetHV3en"] = &AMACv2RegMap::CntSetHV3en;
-  CntSetHV2frq.initReg(m_cfg, RW, 3, 2, 25, 40, "CntSetHV2frq"); m_fieldMap["CntSetHV2frq"] = &AMACv2RegMap::CntSetHV2frq;
-  CntSetHV2en.initReg(m_cfg, RW, 0, 1, 24, 40, "CntSetHV2en"); m_fieldMap["CntSetHV2en"] = &AMACv2RegMap::CntSetHV2en;
-  CntSetHV1frq.initReg(m_cfg, RW, 3, 2, 21, 40, "CntSetHV1frq"); m_fieldMap["CntSetHV1frq"] = &AMACv2RegMap::CntSetHV1frq;
-  CntSetHV1en.initReg(m_cfg, RW, 0, 1, 20, 40, "CntSetHV1en"); m_fieldMap["CntSetHV1en"] = &AMACv2RegMap::CntSetHV1en;
-  CntSetHV0frq.initReg(m_cfg, RW, 3, 2, 17, 40, "CntSetHV0frq"); m_fieldMap["CntSetHV0frq"] = &AMACv2RegMap::CntSetHV0frq;
-  CntSetHV0en.initReg(m_cfg, RW, 0, 1, 16, 40, "CntSetHV0en"); m_fieldMap["CntSetHV0en"] = &AMACv2RegMap::CntSetHV0en;
-  CntSetHyLDO2en.initReg(m_cfg, RW, 0, 1, 14, 40, "CntSetHyLDO2en"); m_fieldMap["CntSetHyLDO2en"] = &AMACv2RegMap::CntSetHyLDO2en;
-  CntSetHyLDO1en.initReg(m_cfg, RW, 0, 1, 13, 40, "CntSetHyLDO1en"); m_fieldMap["CntSetHyLDO1en"] = &AMACv2RegMap::CntSetHyLDO1en;
-  CntSetHyLDO0en.initReg(m_cfg, RW, 0, 1, 12, 40, "CntSetHyLDO0en"); m_fieldMap["CntSetHyLDO0en"] = &AMACv2RegMap::CntSetHyLDO0en;
-  CntSetHxLDO2en.initReg(m_cfg, RW, 0, 1, 10, 40, "CntSetHxLDO2en"); m_fieldMap["CntSetHxLDO2en"] = &AMACv2RegMap::CntSetHxLDO2en;
-  CntSetHxLDO1en.initReg(m_cfg, RW, 0, 1, 9, 40, "CntSetHxLDO1en"); m_fieldMap["CntSetHxLDO1en"] = &AMACv2RegMap::CntSetHxLDO1en;
-  CntSetHxLDO0en.initReg(m_cfg, RW, 0, 1, 8, 40, "CntSetHxLDO0en"); m_fieldMap["CntSetHxLDO0en"] = &AMACv2RegMap::CntSetHxLDO0en;
-  CntSetWARN.initReg(m_cfg, RW, 0, 1, 4, 40, "CntSetWARN"); m_fieldMap["CntSetWARN"] = &AMACv2RegMap::CntSetWARN;
-  // 41 - CntSetC
-  CntSetCHV3frq.initReg(m_cfg, RW, 3, 2, 29, 41, "CntSetCHV3frq"); m_fieldMap["CntSetCHV3frq"] = &AMACv2RegMap::CntSetCHV3frq;
-  CntSetCHV3en.initReg(m_cfg, RW, 0, 1, 28, 41, "CntSetCHV3en"); m_fieldMap["CntSetCHV3en"] = &AMACv2RegMap::CntSetCHV3en;
-  CntSetCHV2frq.initReg(m_cfg, RW, 3, 2, 25, 41, "CntSetCHV2frq"); m_fieldMap["CntSetCHV2frq"] = &AMACv2RegMap::CntSetCHV2frq;
-  CntSetCHV2en.initReg(m_cfg, RW, 0, 1, 24, 41, "CntSetCHV2en"); m_fieldMap["CntSetCHV2en"] = &AMACv2RegMap::CntSetCHV2en;
-  CntSetCHV1frq.initReg(m_cfg, RW, 3, 2, 21, 41, "CntSetCHV1frq"); m_fieldMap["CntSetCHV1frq"] = &AMACv2RegMap::CntSetCHV1frq;
-  CntSetCHV1en.initReg(m_cfg, RW, 0, 1, 20, 41, "CntSetCHV1en"); m_fieldMap["CntSetCHV1en"] = &AMACv2RegMap::CntSetCHV1en;
-  CntSetCHV0frq.initReg(m_cfg, RW, 3, 2, 17, 41, "CntSetCHV0frq"); m_fieldMap["CntSetCHV0frq"] = &AMACv2RegMap::CntSetCHV0frq;
-  CntSetCHV0en.initReg(m_cfg, RW, 0, 1, 16, 41, "CntSetCHV0en"); m_fieldMap["CntSetCHV0en"] = &AMACv2RegMap::CntSetCHV0en;
-  CntSetCHyLDO2en.initReg(m_cfg, RW, 0, 1, 14, 41, "CntSetCHyLDO2en"); m_fieldMap["CntSetCHyLDO2en"] = &AMACv2RegMap::CntSetCHyLDO2en;
-  CntSetCHyLDO1en.initReg(m_cfg, RW, 0, 1, 13, 41, "CntSetCHyLDO1en"); m_fieldMap["CntSetCHyLDO1en"] = &AMACv2RegMap::CntSetCHyLDO1en;
-  CntSetCHyLDO0en.initReg(m_cfg, RW, 0, 1, 12, 41, "CntSetCHyLDO0en"); m_fieldMap["CntSetCHyLDO0en"] = &AMACv2RegMap::CntSetCHyLDO0en;
-  CntSetCHxLDO2en.initReg(m_cfg, RW, 0, 1, 10, 41, "CntSetCHxLDO2en"); m_fieldMap["CntSetCHxLDO2en"] = &AMACv2RegMap::CntSetCHxLDO2en;
-  CntSetCHxLDO1en.initReg(m_cfg, RW, 0, 1, 9, 41, "CntSetCHxLDO1en"); m_fieldMap["CntSetCHxLDO1en"] = &AMACv2RegMap::CntSetCHxLDO1en;
-  CntSetCHxLDO0en.initReg(m_cfg, RW, 0, 1, 8, 41, "CntSetCHxLDO0en"); m_fieldMap["CntSetCHxLDO0en"] = &AMACv2RegMap::CntSetCHxLDO0en;
-  CntSetCWARN.initReg(m_cfg, RW, 0, 1, 4, 41, "CntSetCWARN"); m_fieldMap["CntSetCWARN"] = &AMACv2RegMap::CntSetCWARN;
-  // 42 - DCDCen
-  DCDCAdj.initReg(m_cfg, RW, 0, 2, 4, 42, "DCDCAdj"); m_fieldMap["DCDCAdj"] = &AMACv2RegMap::DCDCAdj;
-  DCDCen.initReg(m_cfg, RW, 0, 1, 0, 42, "DCDCen"); m_fieldMap["DCDCen"] = &AMACv2RegMap::DCDCen;
-  // 43 - DCDCenC
-  DCDCAdjC.initReg(m_cfg, RW, 0, 2, 4, 43, "DCDCAdjC"); m_fieldMap["DCDCAdjC"] = &AMACv2RegMap::DCDCAdjC;
-  DCDCenC.initReg(m_cfg, RW, 0, 1, 0, 43, "DCDCenC"); m_fieldMap["DCDCenC"] = &AMACv2RegMap::DCDCenC;
-  // 44 - Ilock
-  IlockWRN.initReg(m_cfg, RW, 0, 1, 5, 44, "IlockWRN"); m_fieldMap["IlockWRN"] = &AMACv2RegMap::IlockWRN;
-  IlockDCDC.initReg(m_cfg, RW, 0, 1, 4, 44, "IlockDCDC"); m_fieldMap["IlockDCDC"] = &AMACv2RegMap::IlockDCDC;
-  IlockHV2.initReg(m_cfg, RW, 0, 1, 3, 44, "IlockHV2"); m_fieldMap["IlockHV2"] = &AMACv2RegMap::IlockHV2;
-  IlockHV2.initReg(m_cfg, RW, 0, 1, 2, 44, "IlockHV2"); m_fieldMap["IlockHV2"] = &AMACv2RegMap::IlockHV2;
-  IlockHy.initReg(m_cfg, RW, 0, 1, 1, 44, "IlockHy"); m_fieldMap["IlockHy"] = &AMACv2RegMap::IlockHy;
-  IlockHx.initReg(m_cfg, RW, 0, 1, 0, 44, "IlockHx"); m_fieldMap["IlockHx"] = &AMACv2RegMap::IlockHx;
-  // 45 - IlockC
-  IlockCWRN.initReg(m_cfg, RW, 0, 1, 5, 45, "IlockCWRN"); m_fieldMap["IlockCWRN"] = &AMACv2RegMap::IlockCWRN;
-  IlockCDCDC.initReg(m_cfg, RW, 0, 1, 4, 45, "IlockCDCDC"); m_fieldMap["IlockCDCDC"] = &AMACv2RegMap::IlockCDCDC;
-  IlockCHV2.initReg(m_cfg, RW, 0, 1, 3, 45, "IlockCHV2"); m_fieldMap["IlockCHV2"] = &AMACv2RegMap::IlockCHV2;
-  IlockCHV2.initReg(m_cfg, RW, 0, 1, 2, 45, "IlockCHV2"); m_fieldMap["IlockCHV2"] = &AMACv2RegMap::IlockCHV2;
-  IlockCHy.initReg(m_cfg, RW, 0, 1, 1, 45, "IlockCHy"); m_fieldMap["IlockCHy"] = &AMACv2RegMap::IlockCHy;
-  IlockCHx.initReg(m_cfg, RW, 0, 1, 0, 45, "IlockCHx"); m_fieldMap["IlockCHx"] = &AMACv2RegMap::IlockCHx;
-  // 46 - RstCnt
-  RstCntHyHCCresetB.initReg(m_cfg, RW, 0, 1, 16, 46, "RstCntHyHCCresetB"); m_fieldMap["RstCntHyHCCresetB"] = &AMACv2RegMap::RstCntHyHCCresetB;
-  RstCntHxHCCresetB.initReg(m_cfg, RW, 0, 1, 8, 46, "RstCntHxHCCresetB"); m_fieldMap["RstCntHxHCCresetB"] = &AMACv2RegMap::RstCntHxHCCresetB;
-  RstCntOF.initReg(m_cfg, RW, 0, 1, 0, 46, "RstCntOF"); m_fieldMap["RstCntOF"] = &AMACv2RegMap::RstCntOF;
-  // 47 - RstCntC
-  RstCntCHyHCCresetB.initReg(m_cfg, RW, 0, 1, 16, 47, "RstCntCHyHCCresetB"); m_fieldMap["RstCntCHyHCCresetB"] = &AMACv2RegMap::RstCntCHyHCCresetB;
-  RstCntCHxHCCresetB.initReg(m_cfg, RW, 0, 1, 8, 47, "RstCntCHxHCCresetB"); m_fieldMap["RstCntCHxHCCresetB"] = &AMACv2RegMap::RstCntCHxHCCresetB;
-  RstCntCOF.initReg(m_cfg, RW, 0, 1, 0, 47, "RstCntCOF"); m_fieldMap["RstCntCOF"] = &AMACv2RegMap::RstCntCOF;
-  // 48 - AMen
-  AMzeroCalib.initReg(m_cfg, RW, 0, 1, 8, 48, "AMzeroCalib"); m_fieldMap["AMzeroCalib"] = &AMACv2RegMap::AMzeroCalib;
-  AMen.initReg(m_cfg, RW, 1, 1, 0, 48, "AMen"); m_fieldMap["AMen"] = &AMACv2RegMap::AMen;
-  // 49 - AMenC
-  AMzeroCalibC.initReg(m_cfg, RW, 0, 1, 8, 49, "AMzeroCalibC"); m_fieldMap["AMzeroCalibC"] = &AMACv2RegMap::AMzeroCalibC;
-  AMenC.initReg(m_cfg, RW, 1, 1, 0, 49, "AMenC"); m_fieldMap["AMenC"] = &AMACv2RegMap::AMenC;
-  // 50 - AMpwr
-  ReqDCDCPGOOD.initReg(m_cfg, RW, 1, 1, 8, 50, "ReqDCDCPGOOD"); m_fieldMap["ReqDCDCPGOOD"] = &AMACv2RegMap::ReqDCDCPGOOD;
-  DCDCenToPwrAMAC.initReg(m_cfg, RW, 0, 1, 0, 50, "DCDCenToPwrAMAC"); m_fieldMap["DCDCenToPwrAMAC"] = &AMACv2RegMap::DCDCenToPwrAMAC;
-  // 51 - AMpwrC
-  ReqDCDCPGOODC.initReg(m_cfg, RW, 1, 1, 8, 51, "ReqDCDCPGOODC"); m_fieldMap["ReqDCDCPGOODC"] = &AMACv2RegMap::ReqDCDCPGOODC;
-  DCDCenToPwrAMACC.initReg(m_cfg, RW, 0, 1, 0, 51, "DCDCenToPwrAMACC"); m_fieldMap["DCDCenToPwrAMACC"] = &AMACv2RegMap::DCDCenToPwrAMACC;
-  // 52 - BgCnt
-  AMbgen .initReg(m_cfg, RW, 0, 1, 15, 52, "AMbgen" ); m_fieldMap["AMbgen" ] = &AMACv2RegMap::AMbgen;
-  AMbg   .initReg(m_cfg, RW, 0, 5,  8, 52, "AMbg"   ); m_fieldMap["AMbg"   ] = &AMACv2RegMap::AMbg;
-  VDDbgen.initReg(m_cfg, RW, 0, 1,  7, 52, "VDDbgen"); m_fieldMap["VDDbgen"] = &AMACv2RegMap::VDDbgen;
-  VDDbg  .initReg(m_cfg, RW, 0, 5,  0, 52, "VDDbg"  ); m_fieldMap["VDDbg"  ] = &AMACv2RegMap::VDDbg;
-  // 53 - AMcnt
-  AMintCalib.initReg(m_cfg, RW, 0, 4, 24, 53, "AMintCalib"); m_fieldMap["AMintCalib"] = &AMACv2RegMap::AMintCalib;
-  Ch13Mux.initReg(m_cfg, RW, 0, 2, 20, 53, "Ch13Mux"); m_fieldMap["Ch13Mux"] = &AMACv2RegMap::Ch13Mux;
-  Ch12Mux.initReg(m_cfg, RW, 0, 2, 16, 53, "Ch12Mux"); m_fieldMap["Ch12Mux"] = &AMACv2RegMap::Ch12Mux;
-  Ch5Mux.initReg(m_cfg, RW, 0, 2, 13, 53, "Ch5Mux"); m_fieldMap["Ch5Mux"] = &AMACv2RegMap::Ch5Mux;
-  Ch4Mux.initReg(m_cfg, RW, 0, 2, 8, 53, "Ch4Mux"); m_fieldMap["Ch4Mux"] = &AMACv2RegMap::Ch4Mux;
-  Ch3Mux.initReg(m_cfg, RW, 0, 2, 4, 53, "Ch3Mux"); m_fieldMap["Ch3Mux"] = &AMACv2RegMap::Ch3Mux;
-  // 54 - Dacs0
-  DACShunty.initReg(m_cfg, RW, 0, 8, 24, 54, "DACShunty"); m_fieldMap["DACShunty"] = &AMACv2RegMap::DACShunty;
-  DACShuntx.initReg(m_cfg, RW, 0, 8, 16, 54, "DACShuntx"); m_fieldMap["DACShuntx"] = &AMACv2RegMap::DACShuntx;
-  DACCALy.initReg(m_cfg, RW, 0, 8, 8, 54, "DACCALy"); m_fieldMap["DACCALy"] = &AMACv2RegMap::DACCALy;
-  DACCalx.initReg(m_cfg, RW, 0, 8, 0, 54, "DACCalx"); m_fieldMap["DACCalx"] = &AMACv2RegMap::DACCalx;
-  // 55 - DACbias
-  DACbias.initReg(m_cfg, RW, 0xD, 5, 0, 55, "DACbias"); m_fieldMap["DACbias"] = &AMACv2RegMap::DACbias;
-  // 56 - AMACcnt
-  HVcurGain .initReg(m_cfg, RW, 0, 4, 16, 56, "HVcurGain" ); m_fieldMap["HVcurGain" ] = &AMACv2RegMap::HVcurGain;
-  DRcomMode .initReg(m_cfg, RW, 0, 2, 12, 56, "DRcomMode" ); m_fieldMap["DRcomMode" ] = &AMACv2RegMap::DRcomMode;
-  DRcurr    .initReg(m_cfg, RW, 4, 3,  8, 56, "DRcurr"    ); m_fieldMap["DRcurr"    ] = &AMACv2RegMap::DRcurr;
-  RingOscFrq.initReg(m_cfg, RW, 4, 3,  0, 56, "RingOscFrq"); m_fieldMap["RingOscFrq"] = &AMACv2RegMap::RingOscFrq;
-  // 57 - NTC
-  CTAToffset     .initReg(m_cfg, RW, 0, 4, 20, 57, "CTAToffset"     ); m_fieldMap["CTAToffset"     ] = &AMACv2RegMap::CTAToffset;
-  NTCpbCal       .initReg(m_cfg, RW, 1, 1, 19, 57, "NTCpbCal"       ); m_fieldMap["NTCpbCal"       ] = &AMACv2RegMap::NTCpbCal;
-  NTCpbSenseRange.initReg(m_cfg, RW, 4, 3, 16, 57, "NTCpbSenseRange"); m_fieldMap["NTCpbSenseRange"] = &AMACv2RegMap::NTCpbSenseRange;
-  NTCy0Cal       .initReg(m_cfg, RW, 1, 1, 11, 57, "NTCy0Cal"       ); m_fieldMap["NTCy0Cal"       ] = &AMACv2RegMap::NTCy0Cal;
-  NTCy0SenseRange.initReg(m_cfg, RW, 4, 3,  8, 57, "NTCy0SenseRange"); m_fieldMap["NTCy0SenseRange"] = &AMACv2RegMap::NTCy0SenseRange;
-  NTCx0Cal       .initReg(m_cfg, RW, 1, 1,  3, 57, "NTCx0Cal"       ); m_fieldMap["NTCx0Cal"       ] = &AMACv2RegMap::NTCx0Cal;
-  NTCx0SenseRange.initReg(m_cfg, RW, 4, 3,  0, 57, "NTCx0SenseRange"); m_fieldMap["NTCx0SenseRange"] = &AMACv2RegMap::NTCx0SenseRange;
-  // 58 - LvCurCal
-  DCDCoOffset     .initReg(m_cfg, RW, 4, 4, 20, 58, "DCDCoOffset"     ); m_fieldMap["DCDCoOffset"     ] = &AMACv2RegMap::DCDCoOffset;
-  DCDCoZeroReading.initReg(m_cfg, RW, 0, 1, 19, 58, "DCDCoZeroReading"); m_fieldMap["DCDCoZeroReading"] = &AMACv2RegMap::DCDCoZeroReading;
-  DCDCoN          .initReg(m_cfg, RW, 0, 1, 17, 58, "DCDCoN"          ); m_fieldMap["DCDCoN"          ] = &AMACv2RegMap::DCDCoN;
-  DCDCoP          .initReg(m_cfg, RW, 0, 1, 16, 58, "DCDCoP"          ); m_fieldMap["DCDCoP"          ] = &AMACv2RegMap::DCDCoP;
-  DCDCiZeroReading.initReg(m_cfg, RW, 0, 1, 15, 58, "DCDCiZeroReading"); m_fieldMap["DCDCiZeroReading"] = &AMACv2RegMap::DCDCiZeroReading;
-  DCDCiRangeSW    .initReg(m_cfg, RW, 1, 1, 12, 58, "DCDCiRangeSW"    ); m_fieldMap["DCDCiRangeSW"    ] = &AMACv2RegMap::DCDCiRangeSW;
-  DCDCiOffset     .initReg(m_cfg, RW, 8, 4,  8, 58, "DCDCiOffset"     ); m_fieldMap["DCDCiOffset"     ] = &AMACv2RegMap::DCDCiOffset;
-  DCDCiP          .initReg(m_cfg, RW, 0, 3,  4, 58, "DCDCiP"          ); m_fieldMap["DCDCiP"          ] = &AMACv2RegMap::DCDCiP;
-  DCDCiN          .initReg(m_cfg, RW, 0, 3,  0, 58, "DCDCiN"          ); m_fieldMap["DCDCiN"          ] = &AMACv2RegMap::DCDCiN;
-  // 60 - HxICm_cfg
-  HxLAM.initReg(m_cfg, RW, 0, 1, 16, 60, "HxLAM"); m_fieldMap["HxLAM"] = &AMACv2RegMap::HxLAM;
-  HxFlagsLatch.initReg(m_cfg, RW, 1, 1, 12, 60, "HxFlagsLatch"); m_fieldMap["HxFlagsLatch"] = &AMACv2RegMap::HxFlagsLatch;
-  HxFlagsLogic.initReg(m_cfg, RW, 0, 1, 8, 60, "HxFlagsLogic"); m_fieldMap["HxFlagsLogic"] = &AMACv2RegMap::HxFlagsLogic;
-  HxFlagValid.initReg(m_cfg, RW, 0, 1, 4, 60, "HxFlagValid"); m_fieldMap["HxFlagValid"] = &AMACv2RegMap::HxFlagsLogic;
-  HxFlagsValidConf.initReg(m_cfg, RW, 0, 2, 0, 60, "HxFlagValid"); m_fieldMap["HxFlagValid"] = &AMACv2RegMap::HxFlagsLogic;
-  // 61 - HyICm_cfg
-  HyLAM.initReg(m_cfg, RW, 0, 1, 16, 61, "HyLAM"); m_fieldMap["HyLAM"] = &AMACv2RegMap::HyLAM;
-  HyFlagsLatch.initReg(m_cfg, RW, 1, 1, 12, 61, "HyFlagsLatch"); m_fieldMap["HyFlagsLatch"] = &AMACv2RegMap::HyFlagsLatch;
-  HyFlagsLogic.initReg(m_cfg, RW, 0, 1, 8, 61, "HyFlagsLogic"); m_fieldMap["HyFlagsLogic"] = &AMACv2RegMap::HyFlagsLogic;
-  HyFlagValid.initReg(m_cfg, RW, 0, 1, 4, 61, "HyFlagValid"); m_fieldMap["HyFlagValid"] = &AMACv2RegMap::HyFlagsLogic;
-  HyFlagsValidConf.initReg(m_cfg, RW, 0, 2, 0, 61, "HyFlagValid"); m_fieldMap["HyFlagValid"] = &AMACv2RegMap::HyFlagsLogic;
-  // 62 - HV0ICm_cfg
-  HV0LAM.initReg(m_cfg, RW, 0, 1, 16, 62, "HV0LAM"); m_fieldMap["HV0LAM"] = &AMACv2RegMap::HV0LAM;
-  HV0FlagsLatch.initReg(m_cfg, RW, 1, 1, 12, 62, "HV0FlagsLatch"); m_fieldMap["HV0FlagsLatch"] = &AMACv2RegMap::HV0FlagsLatch;
-  HV0FlagsLogic.initReg(m_cfg, RW, 0, 1, 8, 62, "HV0FlagsLogic"); m_fieldMap["HV0FlagsLogic"] = &AMACv2RegMap::HV0FlagsLogic;
-  HV0FlagValid.initReg(m_cfg, RW, 0, 1, 4, 62, "HV0FlagValid"); m_fieldMap["HV0FlagValid"] = &AMACv2RegMap::HV0FlagsLogic;
-  HV0FlagsValidConf.initReg(m_cfg, RW, 0, 2, 0, 62, "HV0FlagValid"); m_fieldMap["HV0FlagValid"] = &AMACv2RegMap::HV0FlagsLogic;
-  // 63 - HV2ICm_cfg
-  HV2LAM.initReg(m_cfg, RW, 0, 1, 16, 63, "HV2LAM"); m_fieldMap["HV2LAM"] = &AMACv2RegMap::HV2LAM;
-  HV2FlagsLatch.initReg(m_cfg, RW, 1, 1, 12, 63, "HV2FlagsLatch"); m_fieldMap["HV2FlagsLatch"] = &AMACv2RegMap::HV2FlagsLatch;
-  HV2FlagsLogic.initReg(m_cfg, RW, 0, 1, 8, 63, "HV2FlagsLogic"); m_fieldMap["HV2FlagsLogic"] = &AMACv2RegMap::HV2FlagsLogic;
-  HV2FlagValid.initReg(m_cfg, RW, 0, 1, 4, 63, "HV2FlagValid"); m_fieldMap["HV2FlagValid"] = &AMACv2RegMap::HV2FlagsLogic;
-  HV2FlagsValidConf.initReg(m_cfg, RW, 0, 2, 0, 63, "HV2FlagValid"); m_fieldMap["HV2FlagValid"] = &AMACv2RegMap::HV2FlagsLogic;
-  // 64 - DCDCICm_cfg
-  DCDCLAM.initReg(m_cfg, RW, 0, 1, 16, 64, "DCDCLAM"); m_fieldMap["DCDCLAM"] = &AMACv2RegMap::DCDCLAM;
-  DCDCFlagsLatch.initReg(m_cfg, RW, 1, 1, 12, 64, "DCDCFlagsLatch"); m_fieldMap["DCDCFlagsLatch"] = &AMACv2RegMap::DCDCFlagsLatch;
-  DCDCFlagsLogic.initReg(m_cfg, RW, 0, 1, 8, 64, "DCDCFlagsLogic"); m_fieldMap["DCDCFlagsLogic"] = &AMACv2RegMap::DCDCFlagsLogic;
-  DCDCFlagValid.initReg(m_cfg, RW, 0, 1, 4, 64, "DCDCFlagValid"); m_fieldMap["DCDCFlagValid"] = &AMACv2RegMap::DCDCFlagsLogic;
-  DCDCFlagsValidConf.initReg(m_cfg, RW, 0, 2, 0, 64, "DCDCFlagValid"); m_fieldMap["DCDCFlagValid"] = &AMACv2RegMap::DCDCFlagsLogic;
-  // 65 - WRNICm_cfg
-  WRNLAM.initReg(m_cfg, RW, 0, 1, 16, 65, "WRNLAM"); m_fieldMap["WRNLAM"] = &AMACv2RegMap::WRNLAM;
-  WRNFlagsLatch.initReg(m_cfg, RW, 1, 1, 12, 65, "WRNFlagsLatch"); m_fieldMap["WRNFlagsLatch"] = &AMACv2RegMap::WRNFlagsLatch;
-  WRNFlagsLogic.initReg(m_cfg, RW, 0, 1, 8, 65, "WRNFlagsLogic"); m_fieldMap["WRNFlagsLogic"] = &AMACv2RegMap::WRNFlagsLogic;
-  WRNFlagValid.initReg(m_cfg, RW, 0, 1, 4, 65, "WRNFlagValid"); m_fieldMap["WRNFlagValid"] = &AMACv2RegMap::WRNFlagsLogic;
-  WRNFlagsValidConf.initReg(m_cfg, RW, 0, 2, 0, 65, "WRNFlagValid"); m_fieldMap["WRNFlagValid"] = &AMACv2RegMap::WRNFlagsLogic;
-  // 70 - HxTlut
-  HxTlut.initReg(m_cfg, RW, 0, 8, 0, 70, "HxTlut"); m_fieldMap["HxTlut"] = &AMACv2RegMap::HxTlut;
-  // 71 - HxModlut1
-  HxModlut1.initReg(m_cfg, RW, 0, 32, 0, 71, "HxModlut1"); m_fieldMap["HxModlut1"] = &AMACv2RegMap::HxModlut1;
-  // 72 - HxModlut2
-  HxModlut2.initReg(m_cfg, RW, 0, 32, 0, 72, "HxModlut2"); m_fieldMap["HxModlut2"] = &AMACv2RegMap::HxModlut2;
-  // 73 - HyTlut
-  HyTlut.initReg(m_cfg, RW, 0, 8, 0, 73, "HyTlut"); m_fieldMap["HyTlut"] = &AMACv2RegMap::HyTlut;
-  // 74 - HyModlut1
-  HyModlut1.initReg(m_cfg, RW, 0, 32, 0, 74, "HyModlut1"); m_fieldMap["HyModlut1"] = &AMACv2RegMap::HyModlut1;
-  // 75 - HyModlut2
-  HyModlut2.initReg(m_cfg, RW, 0, 32, 0, 75, "HyModlut2"); m_fieldMap["HyModlut2"] = &AMACv2RegMap::HyModlut2;
-  // 76 - HV0Tlut;
-  HV0Tlut.initReg(m_cfg, RW, 0, 8, 0, 76, "HV0Tlut"); m_fieldMap["HV0Tlut"] = &AMACv2RegMap::HV0Tlut;
-  // 77 - HV0Modlut1
-  HV0Modlut1.initReg(m_cfg, RW, 0, 32, 0, 77, "HV0Modlut1"); m_fieldMap["HV0Modlut1"] = &AMACv2RegMap::HV0Modlut1;
-  // 78 - HV0Modlut2
-  HV0Modlut2.initReg(m_cfg, RW, 0, 32, 0, 78, "HV0Modlut2"); m_fieldMap["HV0Modlut2"] = &AMACv2RegMap::HV0Modlut2;
-  // 79 - HV2Tlut
-  HV2Tlut.initReg(m_cfg, RW, 0, 8, 0, 79, "HV2Tlut"); m_fieldMap["HV2Tlut"] = &AMACv2RegMap::HV2Tlut;
-  // 80 - HV2Modlut1
-  HV2Modlut1.initReg(m_cfg, RW, 0, 32, 0, 80, "HV2Modlut1"); m_fieldMap["HV2Modlut1"] = &AMACv2RegMap::HV2Modlut1;
-  // 81 - HV2Modlut2
-  HV2Modlut2.initReg(m_cfg, RW, 0, 32, 0, 81, "HV2Modlut2"); m_fieldMap["HV2Modlut2"] = &AMACv2RegMap::HV2Modlut2;
-  // 82 - DCDCTlut
-  DCDCTlut.initReg(m_cfg, RW, 0, 8, 0, 82, "DCDCTlut"); m_fieldMap["DCDCTlut"] = &AMACv2RegMap::DCDCTlut;
-  // 83 - DCDCModlut1
-  DCDCModlut1.initReg(m_cfg, RW, 0, 32, 0, 83, "DCDCModlut1"); m_fieldMap["DCDCModlut1"] = &AMACv2RegMap::DCDCModlut1;
-  // 84 - DCDCModlut2
-  DCDCModlut2.initReg(m_cfg, RW, 0, 32, 0, 84, "DCDCModlut2"); m_fieldMap["DCDCModlut2"] = &AMACv2RegMap::DCDCModlut2;
-  // 85 - WRNTlut
-  WRNTlut.initReg(m_cfg, RW, 0, 8, 0, 85, "WRNTlut"); m_fieldMap["WRNTlut"] = &AMACv2RegMap::WRNTlut;
-  // 86 - WRNModlut1
-  WRNModlut1.initReg(m_cfg, RW, 0, 32, 0, 86, "WRNModlut1"); m_fieldMap["WRNModlut1"] = &AMACv2RegMap::WRNModlut1;
-  // 87 - WRNModlut2
-  WRNModlut2.initReg(m_cfg, RW, 0, 32, 0, 87, "WRNModlut2"); m_fieldMap["WRNModlut2"] = &AMACv2RegMap::WRNModlut2;
-  // 90 - HxFlagEn
-  HxFlagsEnHi.initReg(m_cfg, RW, 0, 16, 16, 90, "HxFlagsEnHi"); m_fieldMap["HxFlagsEnHi"] = &AMACv2RegMap::HxFlagsEnHi;
-  HxFlagsEnLo.initReg(m_cfg, RW, 0, 16, 16, 90, "HxFlagsEnLo"); m_fieldMap["HxFlagsEnLo"] = &AMACv2RegMap::HxFlagsEnLo;
-  // 91 - HyFlagEn
-  HyFlagsEnHi.initReg(m_cfg, RW, 0, 16, 16, 91, "HyFlagsEnHi"); m_fieldMap["HyFlagsEnHi"] = &AMACv2RegMap::HyFlagsEnHi;
-  HyFlagsEnLo.initReg(m_cfg, RW, 0, 16, 16, 91, "HyFlagsEnLo"); m_fieldMap["HyFlagsEnLo"] = &AMACv2RegMap::HyFlagsEnLo;
-  // 92 - HV0FlagEn
-  HV0FlagsEnHi.initReg(m_cfg, RW, 0, 16, 16, 92, "HV0FlagsEnHi"); m_fieldMap["HV0FlagsEnHi"] = &AMACv2RegMap::HV0FlagsEnHi;
-  HV0FlagsEnLo.initReg(m_cfg, RW, 0, 16, 16, 92, "HV0FlagsEnLo"); m_fieldMap["HV0FlagsEnLo"] = &AMACv2RegMap::HV0FlagsEnLo;
-  // 93 - HV2FlagEn
-  HV2FlagsEnHi.initReg(m_cfg, RW, 0, 16, 16, 93, "HxFlagsEnHi"); m_fieldMap["HxFlagsEnHi"] = &AMACv2RegMap::HxFlagsEnHi;
-  HV2FlagsEnLo.initReg(m_cfg, RW, 0, 16, 16, 93, "HxFlagsEnLo"); m_fieldMap["HxFlagsEnLo"] = &AMACv2RegMap::HxFlagsEnLo;
-  // 94 - DCDCFlagEn
-  DCDCFlagsEnHi.initReg(m_cfg, RW, 0, 16, 16, 94, "DCDCFlagsEnHi"); m_fieldMap["DCDCFlagsEnHi"] = &AMACv2RegMap::DCDCFlagsEnHi;
-  DCDCFlagsEnLo.initReg(m_cfg, RW, 0, 16, 16, 94, "DCDCFlagsEnLo"); m_fieldMap["DCDCFlagsEnLo"] = &AMACv2RegMap::DCDCFlagsEnLo;
-  // 94 - WRNFlagEn
-  WRNFlagsEnHi.initReg(m_cfg, RW, 0, 16, 16, 95, "WRNFlagsEnHi"); m_fieldMap["WRNFlagsEnHi"] = &AMACv2RegMap::WRNFlagsEnHi;
-  WRNFlagsEnLo.initReg(m_cfg, RW, 0, 16, 16, 95, "WRNFlagsEnLo"); m_fieldMap["WRNFlagsEnLo"] = &AMACv2RegMap::WRNFlagsEnLo;
-  // 95 - SynFlagEn
-  WRNsynFlagEnHi.initReg(m_cfg, RW, 0, 1, 21, 95, "WRNsynFlagEnHi"); m_fieldMap["WRNsynFlagEnHi"] = &AMACv2RegMap::WRNsynFlagEnHi;
-  WRNsynFlagEnLo.initReg(m_cfg, RW, 0, 1, 20, 95, "WRNsynFlagEnLo"); m_fieldMap["WRNsynFlagEnLo"] = &AMACv2RegMap::WRNsynFlagEnLo;
-  DCDCsynFlagEnHi.initReg(m_cfg, RW, 0, 1, 17, 95, "DCDCsynFlagEnHi"); m_fieldMap["DCDCsynFlagEnHi"] = &AMACv2RegMap::DCDCsynFlagEnHi;
-  DCDCsynFlagEnLo.initReg(m_cfg, RW, 0, 1, 16, 95, "DCDCsynFlagEnLo"); m_fieldMap["DCDCsynFlagEnLo"] = &AMACv2RegMap::DCDCsynFlagEnLo;
-  HV2synFlagEnHi.initReg(m_cfg, RW, 0, 1, 13, 95, "HV2synFlagEnHi"); m_fieldMap["HV2synFlagEnHi"] = &AMACv2RegMap::HV2synFlagEnHi;
-  HV2synFlagEnLo.initReg(m_cfg, RW, 0, 1, 12, 95, "HV2synFlagEnLo"); m_fieldMap["HV2synFlagEnLo"] = &AMACv2RegMap::HV2synFlagEnLo;
-  HV0synFlagEnHi.initReg(m_cfg, RW, 0, 1, 9, 95, "HV0synFlagEnHi"); m_fieldMap["HV0synFlagEnHi"] = &AMACv2RegMap::HV0synFlagEnHi;
-  HV0synFlagEnLo.initReg(m_cfg, RW, 0, 1, 8, 95, "HV0synFlagEnLo"); m_fieldMap["HV0synFlagEnLo"] = &AMACv2RegMap::HV0synFlagEnLo;
-  HysynFlagEnHi.initReg(m_cfg, RW, 0, 1, 5, 95, "HysynFlagEnHi"); m_fieldMap["HysynFlagEnHi"] = &AMACv2RegMap::HysynFlagEnHi;
-  HysynFlagEnLo.initReg(m_cfg, RW, 0, 1, 4, 95, "HysynFlagEnLo"); m_fieldMap["HysynFlagEnLo"] = &AMACv2RegMap::HysynFlagEnLo;
-  HxsynFlagEnHi.initReg(m_cfg, RW, 0, 1, 1, 95, "HxsynFlagEnHi"); m_fieldMap["HxsynFlagEnHi"] = &AMACv2RegMap::HxsynFlagEnHi;
-  HxsynFlagEnLo.initReg(m_cfg, RW, 0, 1, 0, 95, "HxsynFlagEnLo"); m_fieldMap["HxsynFlagEnLo"] = &AMACv2RegMap::HxsynFlagEnLo;
-  // 100 - HxLoTh0
-  HxLoThCh0.initReg(m_cfg, RW, 0, 10, 0, 100, "HxLoThCh0"); m_fieldMap["HxLoThCh0"] = &AMACv2RegMap::HxLoThCh0;
-  HxLoThCh1.initReg(m_cfg, RW, 0, 10, 10, 100, "HxLoThCh1"); m_fieldMap["HxLoThCh1"] = &AMACv2RegMap::HxLoThCh1;
-  HxLoThCh2.initReg(m_cfg, RW, 0, 10, 20, 100, "HxLoThCh2"); m_fieldMap["HxLoThCh2"] = &AMACv2RegMap::HxLoThCh2;
-  // 101 - HxLoTh1
-  HxLoThCh3.initReg(m_cfg, RW, 0, 10, 0, 101, "HxLoThCh3"); m_fieldMap["HxLoThCh3"] = &AMACv2RegMap::HxLoThCh3;
-  HxLoThCh4.initReg(m_cfg, RW, 0, 10, 10, 101, "HxLoThCh4"); m_fieldMap["HxLoThCh4"] = &AMACv2RegMap::HxLoThCh4;
-  HxLoThCh5.initReg(m_cfg, RW, 0, 10, 20, 101, "HxLoThCh5"); m_fieldMap["HxLoThCh5"] = &AMACv2RegMap::HxLoThCh5;
-  // 102 - HxLoTh2
-  HxLoThCh6.initReg(m_cfg, RW, 0, 10, 0, 102, "HxLoThCh6"); m_fieldMap["HxLoThCh6"] = &AMACv2RegMap::HxLoThCh6;
-  HxLoThCh7.initReg(m_cfg, RW, 0, 10, 10, 102, "HxLoThCh7"); m_fieldMap["HxLoThCh7"] = &AMACv2RegMap::HxLoThCh7;
-  HxLoThCh8.initReg(m_cfg, RW, 0, 10, 20, 102, "HxLoThCh8"); m_fieldMap["HxLoThCh8"] = &AMACv2RegMap::HxLoThCh8;
-  // 103 - HxLoTh3
-  HxLoThCh9.initReg(m_cfg, RW, 0, 10, 0, 103, "HxLoThCh9"); m_fieldMap["HxLoThCh9"] = &AMACv2RegMap::HxLoThCh9;
-  HxLoThCh10.initReg(m_cfg, RW, 0, 10, 10, 103, "HxLoThCh10"); m_fieldMap["HxLoThCh10"] = &AMACv2RegMap::HxLoThCh10;
-  HxLoThCh11.initReg(m_cfg, RW, 0, 10, 20, 103, "HxLoThCh11"); m_fieldMap["HxLoThCh11"] = &AMACv2RegMap::HxLoThCh11;
-  // 104 - HxLoTh4
-  HxLoThCh12.initReg(m_cfg, RW, 0, 10, 0, 104, "HxLoThCh12"); m_fieldMap["HxLoThCh12"] = &AMACv2RegMap::HxLoThCh12;
-  HxLoThCh13.initReg(m_cfg, RW, 0, 10, 10, 104, "HxLoThCh13"); m_fieldMap["HxLoThCh13"] = &AMACv2RegMap::HxLoThCh13;
-  HxLoThCh14.initReg(m_cfg, RW, 0, 10, 20, 104, "HxLoThCh14"); m_fieldMap["HxLoThCh14"] = &AMACv2RegMap::HxLoThCh14;
-  // 105 - HxLoTh5
-  HxLoThCh15.initReg(m_cfg, RW, 0, 10, 0, 105, "HxLoThCh15"); m_fieldMap["HxLoThCh15"] = &AMACv2RegMap::HxLoThCh15;
-  // 106 - HxHiTh0
-  HxHiThCh0.initReg(m_cfg, RW, 0x3FF, 10, 0, 106, "HxLoThCh0"); m_fieldMap["HxLoThCh0"] = &AMACv2RegMap::HxLoThCh0;
-  HxHiThCh1.initReg(m_cfg, RW, 0x3FF, 10, 10, 106, "HxLoThCh1"); m_fieldMap["HxLoThCh1"] = &AMACv2RegMap::HxLoThCh1;
-  HxHiThCh2.initReg(m_cfg, RW, 0x3FF, 10, 20, 106, "HxLoThCh2"); m_fieldMap["HxLoThCh2"] = &AMACv2RegMap::HxLoThCh2;
-  // 107 - HxHiTh1
-  HxHiThCh3.initReg(m_cfg, RW, 0x3FF, 10, 0, 107, "HxHiThCh3"); m_fieldMap["HxHiThCh3"] = &AMACv2RegMap::HxHiThCh3;
-  HxHiThCh4.initReg(m_cfg, RW, 0x3FF, 10, 10, 107, "HxHiThCh4"); m_fieldMap["HxHiThCh4"] = &AMACv2RegMap::HxHiThCh4;
-  HxHiThCh5.initReg(m_cfg, RW, 0x3FF, 10, 20, 107, "HxHiThCh5"); m_fieldMap["HxHiThCh5"] = &AMACv2RegMap::HxHiThCh5;
-  // 108 - HxHiTh2
-  HxHiThCh6.initReg(m_cfg, RW, 0x3FF, 10, 0, 108, "HxHiThCh6"); m_fieldMap["HxHiThCh6"] = &AMACv2RegMap::HxHiThCh6;
-  HxHiThCh7.initReg(m_cfg, RW, 0x3FF, 10, 10, 108, "HxHiThCh7"); m_fieldMap["HxHiThCh7"] = &AMACv2RegMap::HxHiThCh7;
-  HxHiThCh8.initReg(m_cfg, RW, 0x3FF, 10, 20, 108, "HxHiThCh8"); m_fieldMap["HxHiThCh8"] = &AMACv2RegMap::HxHiThCh8;
-  // 109 - HxHiTh3
-  HxHiThCh9.initReg(m_cfg, RW, 0x3FF, 10, 0, 109, "HxHiThCh9"); m_fieldMap["HxHiThCh9"] = &AMACv2RegMap::HxHiThCh9;
-  HxHiThCh10.initReg(m_cfg, RW, 0x3FF, 10, 10, 109, "HxHiThCh10"); m_fieldMap["HxHiThCh10"] = &AMACv2RegMap::HxHiThCh10;
-  HxHiThCh11.initReg(m_cfg, RW, 0x3FF, 10, 20, 109, "HxHiThCh11"); m_fieldMap["HxHiThCh11"] = &AMACv2RegMap::HxHiThCh11;
-  // 110 - HxHiTh4
-  HxHiThCh12.initReg(m_cfg, RW, 0x3FF, 10, 0, 110, "HxHiThCh12"); m_fieldMap["HxHiThCh12"] = &AMACv2RegMap::HxHiThCh12;
-  HxHiThCh13.initReg(m_cfg, RW, 0x3FF, 10, 10, 110, "HxHiThCh13"); m_fieldMap["HxHiThCh13"] = &AMACv2RegMap::HxHiThCh13;
-  HxHiThCh14.initReg(m_cfg, RW, 0x3FF, 10, 20, 110, "HxHiThCh14"); m_fieldMap["HxHiThCh14"] = &AMACv2RegMap::HxHiThCh14;
-  // 111 - HxHiTh5
-  HxHiThCh15.initReg(m_cfg, RW, 0x3FF, 10, 0, 111, "HxHiThCh15"); m_fieldMap["HxHiThCh15"] = &AMACv2RegMap::HxHiThCh15;
-  // 112 - HyLoTh0
-  HyLoThCh0.initReg(m_cfg, RW, 0, 10, 0, 112, "HyLoThCh0"); m_fieldMap["HyLoThCh0"] = &AMACv2RegMap::HyLoThCh0;
-  HyLoThCh1.initReg(m_cfg, RW, 0, 10, 10, 112, "HyLoThCh1"); m_fieldMap["HyLoThCh1"] = &AMACv2RegMap::HyLoThCh1;
-  HyLoThCh2.initReg(m_cfg, RW, 0, 10, 20, 112, "HyLoThCh2"); m_fieldMap["HyLoThCh2"] = &AMACv2RegMap::HyLoThCh2;
-  // 113 - HyLoTh1
-  HyLoThCh3.initReg(m_cfg, RW, 0, 10, 0, 113, "HyLoThCh3"); m_fieldMap["HyLoThCh3"] = &AMACv2RegMap::HyLoThCh3;
-  HyLoThCh4.initReg(m_cfg, RW, 0, 10, 10, 113, "HyLoThCh4"); m_fieldMap["HyLoThCh4"] = &AMACv2RegMap::HyLoThCh4;
-  HyLoThCh5.initReg(m_cfg, RW, 0, 10, 20, 113, "HyLoThCh5"); m_fieldMap["HyLoThCh5"] = &AMACv2RegMap::HyLoThCh5;
-  // 114 - HyLoTh2
-  HyLoThCh6.initReg(m_cfg, RW, 0, 10, 0, 114, "HyLoThCh6"); m_fieldMap["HyLoThCh6"] = &AMACv2RegMap::HyLoThCh6;
-  HyLoThCh7.initReg(m_cfg, RW, 0, 10, 10, 114, "HyLoThCh7"); m_fieldMap["HyLoThCh7"] = &AMACv2RegMap::HyLoThCh7;
-  HyLoThCh8.initReg(m_cfg, RW, 0, 10, 20, 114, "HyLoThCh8"); m_fieldMap["HyLoThCh8"] = &AMACv2RegMap::HyLoThCh8;
-  // 115 - HyLoTh3
-  HyLoThCh9.initReg(m_cfg, RW, 0, 10, 0, 115, "HyLoThCh9"); m_fieldMap["HyLoThCh9"] = &AMACv2RegMap::HyLoThCh9;
-  HyLoThCh10.initReg(m_cfg, RW, 0, 10, 10, 115, "HyLoThCh10"); m_fieldMap["HyLoThCh10"] = &AMACv2RegMap::HyLoThCh10;
-  HyLoThCh11.initReg(m_cfg, RW, 0, 10, 20, 115, "HyLoThCh11"); m_fieldMap["HyLoThCh11"] = &AMACv2RegMap::HyLoThCh11;
-  // 116 - HyLoTh4
-  HyLoThCh12.initReg(m_cfg, RW, 0, 10, 0, 116, "HyLoThCh12"); m_fieldMap["HyLoThCh12"] = &AMACv2RegMap::HyLoThCh12;
-  HyLoThCh13.initReg(m_cfg, RW, 0, 10, 10, 116, "HyLoThCh13"); m_fieldMap["HyLoThCh13"] = &AMACv2RegMap::HyLoThCh13;
-  HyLoThCh14.initReg(m_cfg, RW, 0, 10, 20, 116, "HyLoThCh14"); m_fieldMap["HyLoThCh14"] = &AMACv2RegMap::HyLoThCh14;
-  // 117 - HyLoTh5
-  HyLoThCh15.initReg(m_cfg, RW, 0, 10, 0, 117, "HyLoThCh15"); m_fieldMap["HyLoThCh15"] = &AMACv2RegMap::HyLoThCh15;
-  // 118 - HyHiTh0
-  HyHiThCh0.initReg(m_cfg, RW, 0x3FF, 10, 0, 118, "HyLoThCh0"); m_fieldMap["HyLoThCh0"] = &AMACv2RegMap::HyLoThCh0;
-  HyHiThCh1.initReg(m_cfg, RW, 0x3FF, 10, 10, 118, "HyLoThCh1"); m_fieldMap["HyLoThCh1"] = &AMACv2RegMap::HyLoThCh1;
-  HyHiThCh2.initReg(m_cfg, RW, 0x3FF, 10, 20, 118, "HyLoThCh2"); m_fieldMap["HyLoThCh2"] = &AMACv2RegMap::HyLoThCh2;
-  // 119 - HyHiTh1
-  HyHiThCh3.initReg(m_cfg, RW, 0x3FF, 10, 0, 119, "HyHiThCh3"); m_fieldMap["HyHiThCh3"] = &AMACv2RegMap::HyHiThCh3;
-  HyHiThCh4.initReg(m_cfg, RW, 0x3FF, 10, 10, 119, "HyHiThCh4"); m_fieldMap["HyHiThCh4"] = &AMACv2RegMap::HyHiThCh4;
-  HyHiThCh5.initReg(m_cfg, RW, 0x3FF, 10, 20, 119, "HyHiThCh5"); m_fieldMap["HyHiThCh5"] = &AMACv2RegMap::HyHiThCh5;
-  // 120 - HyHiTh2
-  HyHiThCh6.initReg(m_cfg, RW, 0x3FF, 10, 0, 120, "HyHiThCh6"); m_fieldMap["HyHiThCh6"] = &AMACv2RegMap::HyHiThCh6;
-  HyHiThCh7.initReg(m_cfg, RW, 0x3FF, 10, 10, 120, "HyHiThCh7"); m_fieldMap["HyHiThCh7"] = &AMACv2RegMap::HyHiThCh7;
-  HyHiThCh8.initReg(m_cfg, RW, 0x3FF, 10, 20, 120, "HyHiThCh8"); m_fieldMap["HyHiThCh8"] = &AMACv2RegMap::HyHiThCh8;
-  // 121 - HyHiTh3
-  HyHiThCh9.initReg(m_cfg, RW, 0x3FF, 10, 0, 121, "HyHiThCh9"); m_fieldMap["HyHiThCh9"] = &AMACv2RegMap::HyHiThCh9;
-  HyHiThCh10.initReg(m_cfg, RW, 0x3FF, 10, 10, 121, "HyHiThCh10"); m_fieldMap["HyHiThCh10"] = &AMACv2RegMap::HyHiThCh10;
-  HyHiThCh11.initReg(m_cfg, RW, 0x3FF, 10, 20, 121, "HyHiThCh11"); m_fieldMap["HyHiThCh11"] = &AMACv2RegMap::HyHiThCh11;
-  // 122 - HyHiTh4
-  HyHiThCh12.initReg(m_cfg, RW, 0x3FF, 10, 0, 122, "HyHiThCh12"); m_fieldMap["HyHiThCh12"] = &AMACv2RegMap::HyHiThCh12;
-  HyHiThCh13.initReg(m_cfg, RW, 0x3FF, 10, 10, 122, "HyHiThCh13"); m_fieldMap["HyHiThCh13"] = &AMACv2RegMap::HyHiThCh13;
-  HyHiThCh14.initReg(m_cfg, RW, 0x3FF, 10, 20, 122, "HyHiThCh14"); m_fieldMap["HyHiThCh14"] = &AMACv2RegMap::HyHiThCh14;
-  // 123 - HyHiTh5
-  HyHiThCh15.initReg(m_cfg, RW, 0x3FF, 10, 0, 123, "HyHiThCh15"); m_fieldMap["HyHiThCh15"] = &AMACv2RegMap::HyHiThCh15;
-  // 124 - HV0LoTh0
-  HV0LoThCh0.initReg(m_cfg, RW, 0, 10, 0, 124, "HV0LoThCh0"); m_fieldMap["HV0LoThCh0"] = &AMACv2RegMap::HV0LoThCh0;
-  HV0LoThCh1.initReg(m_cfg, RW, 0, 10, 10, 124, "HV0LoThCh1"); m_fieldMap["HV0LoThCh1"] = &AMACv2RegMap::HV0LoThCh1;
-  HV0LoThCh2.initReg(m_cfg, RW, 0, 10, 20, 124, "HV0LoThCh2"); m_fieldMap["HV0LoThCh2"] = &AMACv2RegMap::HV0LoThCh2;
-  // 125 - HV0LoTh1
-  HV0LoThCh3.initReg(m_cfg, RW, 0, 10, 0, 125, "HV0LoThCh3"); m_fieldMap["HV0LoThCh3"] = &AMACv2RegMap::HV0LoThCh3;
-  HV0LoThCh4.initReg(m_cfg, RW, 0, 10, 10, 125, "HV0LoThCh4"); m_fieldMap["HV0LoThCh4"] = &AMACv2RegMap::HV0LoThCh4;
-  HV0LoThCh5.initReg(m_cfg, RW, 0, 10, 20, 125, "HV0LoThCh5"); m_fieldMap["HV0LoThCh5"] = &AMACv2RegMap::HV0LoThCh5;
-  // 126 - HV0LoTh2
-  HV0LoThCh6.initReg(m_cfg, RW, 0, 10, 0, 126, "HV0LoThCh6"); m_fieldMap["HV0LoThCh6"] = &AMACv2RegMap::HV0LoThCh6;
-  HV0LoThCh7.initReg(m_cfg, RW, 0, 10, 10, 126, "HV0LoThCh7"); m_fieldMap["HV0LoThCh7"] = &AMACv2RegMap::HV0LoThCh7;
-  HV0LoThCh8.initReg(m_cfg, RW, 0, 10, 20, 126, "HV0LoThCh8"); m_fieldMap["HV0LoThCh8"] = &AMACv2RegMap::HV0LoThCh8;
-  // 127 - HV0LoTh3
-  HV0LoThCh9.initReg(m_cfg, RW, 0, 10, 0, 127, "HV0LoThCh9"); m_fieldMap["HV0LoThCh9"] = &AMACv2RegMap::HV0LoThCh9;
-  HV0LoThCh10.initReg(m_cfg, RW, 0, 10, 10, 127, "HV0LoThCh10"); m_fieldMap["HV0LoThCh10"] = &AMACv2RegMap::HV0LoThCh10;
-  HV0LoThCh11.initReg(m_cfg, RW, 0, 10, 20, 127, "HV0LoThCh11"); m_fieldMap["HV0LoThCh11"] = &AMACv2RegMap::HV0LoThCh11;
-  // 128 - HV0LoTh4
-  HV0LoThCh12.initReg(m_cfg, RW, 0, 10, 0, 128, "HV0LoThCh12"); m_fieldMap["HV0LoThCh12"] = &AMACv2RegMap::HV0LoThCh12;
-  HV0LoThCh13.initReg(m_cfg, RW, 0, 10, 10, 128, "HV0LoThCh13"); m_fieldMap["HV0LoThCh13"] = &AMACv2RegMap::HV0LoThCh13;
-  HV0LoThCh14.initReg(m_cfg, RW, 0, 10, 20, 128, "HV0LoThCh14"); m_fieldMap["HV0LoThCh14"] = &AMACv2RegMap::HV0LoThCh14;
-  // 129 - HV0LoTh5
-  HV0LoThCh15.initReg(m_cfg, RW, 0, 10, 0, 129, "HV0LoThCh15"); m_fieldMap["HV0LoThCh15"] = &AMACv2RegMap::HV0LoThCh15;
-  // 130 - HV0HiTh0
-  HV0HiThCh0.initReg(m_cfg, RW, 0x3FF, 10, 0, 130, "HV0LoThCh0"); m_fieldMap["HV0LoThCh0"] = &AMACv2RegMap::HV0LoThCh0;
-  HV0HiThCh1.initReg(m_cfg, RW, 0x3FF, 10, 10, 130, "HV0LoThCh1"); m_fieldMap["HV0LoThCh1"] = &AMACv2RegMap::HV0LoThCh1;
-  HV0HiThCh2.initReg(m_cfg, RW, 0x3FF, 10, 20, 130, "HV0LoThCh2"); m_fieldMap["HV0LoThCh2"] = &AMACv2RegMap::HV0LoThCh2;
-  // 131 - HV0HiTh1
-  HV0HiThCh3.initReg(m_cfg, RW, 0x3FF, 10, 0, 131, "HV0HiThCh3"); m_fieldMap["HV0HiThCh3"] = &AMACv2RegMap::HV0HiThCh3;
-  HV0HiThCh4.initReg(m_cfg, RW, 0x3FF, 10, 10, 131, "HV0HiThCh4"); m_fieldMap["HV0HiThCh4"] = &AMACv2RegMap::HV0HiThCh4;
-  HV0HiThCh5.initReg(m_cfg, RW, 0x3FF, 10, 20, 131, "HV0HiThCh5"); m_fieldMap["HV0HiThCh5"] = &AMACv2RegMap::HV0HiThCh5;
-  // 132 - HV0HiTh2
-  HV0HiThCh6.initReg(m_cfg, RW, 0x3FF, 10, 0, 132, "HV0HiThCh6"); m_fieldMap["HV0HiThCh6"] = &AMACv2RegMap::HV0HiThCh6;
-  HV0HiThCh7.initReg(m_cfg, RW, 0x3FF, 10, 10, 132, "HV0HiThCh7"); m_fieldMap["HV0HiThCh7"] = &AMACv2RegMap::HV0HiThCh7;
-  HV0HiThCh8.initReg(m_cfg, RW, 0x3FF, 10, 20, 132, "HV0HiThCh8"); m_fieldMap["HV0HiThCh8"] = &AMACv2RegMap::HV0HiThCh8;
-  // 133 - HV0HiTh3
-  HV0HiThCh9.initReg(m_cfg, RW, 0x3FF, 10, 0, 133, "HV0HiThCh9"); m_fieldMap["HV0HiThCh9"] = &AMACv2RegMap::HV0HiThCh9;
-  HV0HiThCh10.initReg(m_cfg, RW, 0x3FF, 10, 10, 133, "HV0HiThCh10"); m_fieldMap["HV0HiThCh10"] = &AMACv2RegMap::HV0HiThCh10;
-  HV0HiThCh11.initReg(m_cfg, RW, 0x3FF, 10, 20, 133, "HV0HiThCh11"); m_fieldMap["HV0HiThCh11"] = &AMACv2RegMap::HV0HiThCh11;
-  // 134 - HV0HiTh4
-  HV0HiThCh12.initReg(m_cfg, RW, 0x3FF, 10, 0, 134, "HV0HiThCh12"); m_fieldMap["HV0HiThCh12"] = &AMACv2RegMap::HV0HiThCh12;
-  HV0HiThCh13.initReg(m_cfg, RW, 0x3FF, 10, 10, 134, "HV0HiThCh13"); m_fieldMap["HV0HiThCh13"] = &AMACv2RegMap::HV0HiThCh13;
-  HV0HiThCh14.initReg(m_cfg, RW, 0x3FF, 10, 20, 134, "HV0HiThCh14"); m_fieldMap["HV0HiThCh14"] = &AMACv2RegMap::HV0HiThCh14;
-  // 135 - HV0HiTh5
-  HV0HiThCh15.initReg(m_cfg, RW, 0x3FF, 10, 0, 135, "HV0HiThCh15"); m_fieldMap["HV0HiThCh15"] = &AMACv2RegMap::HV0HiThCh15;
-  // 136 - HV2LoTh0
-  HV2LoThCh0.initReg(m_cfg, RW, 0, 10, 0, 136, "HV2LoThCh0"); m_fieldMap["HV2LoThCh0"] = &AMACv2RegMap::HV2LoThCh0;
-  HV2LoThCh1.initReg(m_cfg, RW, 0, 10, 10, 136, "HV2LoThCh1"); m_fieldMap["HV2LoThCh1"] = &AMACv2RegMap::HV2LoThCh1;
-  HV2LoThCh2.initReg(m_cfg, RW, 0, 10, 20, 136, "HV2LoThCh2"); m_fieldMap["HV2LoThCh2"] = &AMACv2RegMap::HV2LoThCh2;
-  // 137 - HV2LoTh1
-  HV2LoThCh3.initReg(m_cfg, RW, 0, 10, 0, 137, "HV2LoThCh3"); m_fieldMap["HV2LoThCh3"] = &AMACv2RegMap::HV2LoThCh3;
-  HV2LoThCh4.initReg(m_cfg, RW, 0, 10, 10, 137, "HV2LoThCh4"); m_fieldMap["HV2LoThCh4"] = &AMACv2RegMap::HV2LoThCh4;
-  HV2LoThCh5.initReg(m_cfg, RW, 0, 10, 20, 137, "HV2LoThCh5"); m_fieldMap["HV2LoThCh5"] = &AMACv2RegMap::HV2LoThCh5;
-  // 138 - HV2LoTh2
-  HV2LoThCh6.initReg(m_cfg, RW, 0, 10, 0, 138, "HV2LoThCh6"); m_fieldMap["HV2LoThCh6"] = &AMACv2RegMap::HV2LoThCh6;
-  HV2LoThCh7.initReg(m_cfg, RW, 0, 10, 10, 138, "HV2LoThCh7"); m_fieldMap["HV2LoThCh7"] = &AMACv2RegMap::HV2LoThCh7;
-  HV2LoThCh8.initReg(m_cfg, RW, 0, 10, 20, 138, "HV2LoThCh8"); m_fieldMap["HV2LoThCh8"] = &AMACv2RegMap::HV2LoThCh8;
-  // 139 - HV2LoTh3
-  HV2LoThCh9.initReg(m_cfg, RW, 0, 10, 0, 139, "HV2LoThCh9"); m_fieldMap["HV2LoThCh9"] = &AMACv2RegMap::HV2LoThCh9;
-  HV2LoThCh10.initReg(m_cfg, RW, 0, 10, 10, 139, "HV2LoThCh10"); m_fieldMap["HV2LoThCh10"] = &AMACv2RegMap::HV2LoThCh10;
-  HV2LoThCh11.initReg(m_cfg, RW, 0, 10, 20, 139, "HV2LoThCh11"); m_fieldMap["HV2LoThCh11"] = &AMACv2RegMap::HV2LoThCh11;
-  // 140 - HV2LoTh4
-  HV2LoThCh12.initReg(m_cfg, RW, 0, 10, 0, 140, "HV2LoThCh12"); m_fieldMap["HV2LoThCh12"] = &AMACv2RegMap::HV2LoThCh12;
-  HV2LoThCh13.initReg(m_cfg, RW, 0, 10, 10, 140, "HV2LoThCh13"); m_fieldMap["HV2LoThCh13"] = &AMACv2RegMap::HV2LoThCh13;
-  HV2LoThCh14.initReg(m_cfg, RW, 0, 10, 20, 140, "HV2LoThCh14"); m_fieldMap["HV2LoThCh14"] = &AMACv2RegMap::HV2LoThCh14;
-  // 141 - HV2LoTh5
-  HV2LoThCh15.initReg(m_cfg, RW, 0, 10, 0, 141, "HV2LoThCh15"); m_fieldMap["HV2LoThCh15"] = &AMACv2RegMap::HV2LoThCh15;
-  // 142 - HV2HiTh0
-  HV2HiThCh0.initReg(m_cfg, RW, 0x3FF, 10, 0, 142, "HV2LoThCh0"); m_fieldMap["HV2LoThCh0"] = &AMACv2RegMap::HV2LoThCh0;
-  HV2HiThCh1.initReg(m_cfg, RW, 0x3FF, 10, 10, 142, "HV2LoThCh1"); m_fieldMap["HV2LoThCh1"] = &AMACv2RegMap::HV2LoThCh1;
-  HV2HiThCh2.initReg(m_cfg, RW, 0x3FF, 10, 20, 142, "HV2LoThCh2"); m_fieldMap["HV2LoThCh2"] = &AMACv2RegMap::HV2LoThCh2;
-  // 143 - HV2HiTh1
-  HV2HiThCh3.initReg(m_cfg, RW, 0x3FF, 10, 0, 143, "HV2HiThCh3"); m_fieldMap["HV2HiThCh3"] = &AMACv2RegMap::HV2HiThCh3;
-  HV2HiThCh4.initReg(m_cfg, RW, 0x3FF, 10, 10, 143, "HV2HiThCh4"); m_fieldMap["HV2HiThCh4"] = &AMACv2RegMap::HV2HiThCh4;
-  HV2HiThCh5.initReg(m_cfg, RW, 0x3FF, 10, 20, 143, "HV2HiThCh5"); m_fieldMap["HV2HiThCh5"] = &AMACv2RegMap::HV2HiThCh5;
-  // 144 - HV2HiTh2
-  HV2HiThCh6.initReg(m_cfg, RW, 0x3FF, 10, 0, 144, "HV2HiThCh6"); m_fieldMap["HV2HiThCh6"] = &AMACv2RegMap::HV2HiThCh6;
-  HV2HiThCh7.initReg(m_cfg, RW, 0x3FF, 10, 10, 144, "HV2HiThCh7"); m_fieldMap["HV2HiThCh7"] = &AMACv2RegMap::HV2HiThCh7;
-  HV2HiThCh8.initReg(m_cfg, RW, 0x3FF, 10, 20, 144, "HV2HiThCh8"); m_fieldMap["HV2HiThCh8"] = &AMACv2RegMap::HV2HiThCh8;
-  // 145 - HV2HiTh3
-  HV2HiThCh9.initReg(m_cfg, RW, 0x3FF, 10, 0, 145, "HV2HiThCh9"); m_fieldMap["HV2HiThCh9"] = &AMACv2RegMap::HV2HiThCh9;
-  HV2HiThCh10.initReg(m_cfg, RW, 0x3FF, 10, 10, 145, "HV2HiThCh10"); m_fieldMap["HV2HiThCh10"] = &AMACv2RegMap::HV2HiThCh10;
-  HV2HiThCh11.initReg(m_cfg, RW, 0x3FF, 10, 20, 145, "HV2HiThCh11"); m_fieldMap["HV2HiThCh11"] = &AMACv2RegMap::HV2HiThCh11;
-  // 146 - HV2HiTh4
-  HV2HiThCh12.initReg(m_cfg, RW, 0x3FF, 10, 0, 146, "HV2HiThCh12"); m_fieldMap["HV2HiThCh12"] = &AMACv2RegMap::HV2HiThCh12;
-  HV2HiThCh13.initReg(m_cfg, RW, 0x3FF, 10, 10, 146, "HV2HiThCh13"); m_fieldMap["HV2HiThCh13"] = &AMACv2RegMap::HV2HiThCh13;
-  HV2HiThCh14.initReg(m_cfg, RW, 0x3FF, 10, 20, 146, "HV2HiThCh14"); m_fieldMap["HV2HiThCh14"] = &AMACv2RegMap::HV2HiThCh14;
-  // 147 - HV2HiTh5
-  HV2HiThCh15.initReg(m_cfg, RW, 0x3FF, 10, 0, 147, "HV2HiThCh15"); m_fieldMap["HV2HiThCh15"] = &AMACv2RegMap::HV2HiThCh15;
-  // 148 - DCDCLoTh0
-  DCDCLoThCh0.initReg(m_cfg, RW, 0, 10, 0, 148, "DCDCLoThCh0"); m_fieldMap["DCDCLoThCh0"] = &AMACv2RegMap::DCDCLoThCh0;
-  DCDCLoThCh1.initReg(m_cfg, RW, 0, 10, 10, 148, "DCDCLoThCh1"); m_fieldMap["DCDCLoThCh1"] = &AMACv2RegMap::DCDCLoThCh1;
-  DCDCLoThCh2.initReg(m_cfg, RW, 0, 10, 20, 148, "DCDCLoThCh2"); m_fieldMap["DCDCLoThCh2"] = &AMACv2RegMap::DCDCLoThCh2;
-  // 149 - DCDCLoTh1
-  DCDCLoThCh3.initReg(m_cfg, RW, 0, 10, 0, 149, "DCDCLoThCh3"); m_fieldMap["DCDCLoThCh3"] = &AMACv2RegMap::DCDCLoThCh3;
-  DCDCLoThCh4.initReg(m_cfg, RW, 0, 10, 10, 149, "DCDCLoThCh4"); m_fieldMap["DCDCLoThCh4"] = &AMACv2RegMap::DCDCLoThCh4;
-  DCDCLoThCh5.initReg(m_cfg, RW, 0, 10, 20, 149, "DCDCLoThCh5"); m_fieldMap["DCDCLoThCh5"] = &AMACv2RegMap::DCDCLoThCh5;
-  // 150 - DCDCLoTh2
-  DCDCLoThCh6.initReg(m_cfg, RW, 0, 10, 0, 150, "DCDCLoThCh6"); m_fieldMap["DCDCLoThCh6"] = &AMACv2RegMap::DCDCLoThCh6;
-  DCDCLoThCh7.initReg(m_cfg, RW, 0, 10, 10, 150, "DCDCLoThCh7"); m_fieldMap["DCDCLoThCh7"] = &AMACv2RegMap::DCDCLoThCh7;
-  DCDCLoThCh8.initReg(m_cfg, RW, 0, 10, 20, 150, "DCDCLoThCh8"); m_fieldMap["DCDCLoThCh8"] = &AMACv2RegMap::DCDCLoThCh8;
-  // 151 - DCDCLoTh3
-  DCDCLoThCh9.initReg(m_cfg, RW, 0, 10, 0, 151, "DCDCLoThCh9"); m_fieldMap["DCDCLoThCh9"] = &AMACv2RegMap::DCDCLoThCh9;
-  DCDCLoThCh10.initReg(m_cfg, RW, 0, 10, 10, 151, "DCDCLoThCh10"); m_fieldMap["DCDCLoThCh10"] = &AMACv2RegMap::DCDCLoThCh10;
-  DCDCLoThCh11.initReg(m_cfg, RW, 0, 10, 20, 151, "DCDCLoThCh11"); m_fieldMap["DCDCLoThCh11"] = &AMACv2RegMap::DCDCLoThCh11;
-  // 152 - DCDCLoTh4
-  DCDCLoThCh12.initReg(m_cfg, RW, 0, 10, 0, 152, "DCDCLoThCh12"); m_fieldMap["DCDCLoThCh12"] = &AMACv2RegMap::DCDCLoThCh12;
-  DCDCLoThCh13.initReg(m_cfg, RW, 0, 10, 10, 152, "DCDCLoThCh13"); m_fieldMap["DCDCLoThCh13"] = &AMACv2RegMap::DCDCLoThCh13;
-  DCDCLoThCh14.initReg(m_cfg, RW, 0, 10, 20, 152, "DCDCLoThCh14"); m_fieldMap["DCDCLoThCh14"] = &AMACv2RegMap::DCDCLoThCh14;
-  // 153 - DCDCLoTh5
-  DCDCLoThCh15.initReg(m_cfg, RW, 0, 10, 0, 153, "DCDCLoThCh15"); m_fieldMap["DCDCLoThCh15"] = &AMACv2RegMap::DCDCLoThCh15;
-  // 154 - DCDCHiTh0
-  DCDCHiThCh0.initReg(m_cfg, RW, 0x3FF, 10, 0, 154, "DCDCLoThCh0"); m_fieldMap["DCDCLoThCh0"] = &AMACv2RegMap::DCDCLoThCh0;
-  DCDCHiThCh1.initReg(m_cfg, RW, 0x3FF, 10, 10, 154, "DCDCLoThCh1"); m_fieldMap["DCDCLoThCh1"] = &AMACv2RegMap::DCDCLoThCh1;
-  DCDCHiThCh2.initReg(m_cfg, RW, 0x3FF, 10, 20, 154, "DCDCLoThCh2"); m_fieldMap["DCDCLoThCh2"] = &AMACv2RegMap::DCDCLoThCh2;
-  // 155 - DCDCHiTh1
-  DCDCHiThCh3.initReg(m_cfg, RW, 0x3FF, 10, 0, 155, "DCDCHiThCh3"); m_fieldMap["DCDCHiThCh3"] = &AMACv2RegMap::DCDCHiThCh3;
-  DCDCHiThCh4.initReg(m_cfg, RW, 0x3FF, 10, 10, 155, "DCDCHiThCh4"); m_fieldMap["DCDCHiThCh4"] = &AMACv2RegMap::DCDCHiThCh4;
-  DCDCHiThCh5.initReg(m_cfg, RW, 0x3FF, 10, 20, 155, "DCDCHiThCh5"); m_fieldMap["DCDCHiThCh5"] = &AMACv2RegMap::DCDCHiThCh5;
-  // 156 - DCDCHiTh2
-  DCDCHiThCh6.initReg(m_cfg, RW, 0x3FF, 10, 0, 156, "DCDCHiThCh6"); m_fieldMap["DCDCHiThCh6"] = &AMACv2RegMap::DCDCHiThCh6;
-  DCDCHiThCh7.initReg(m_cfg, RW, 0x3FF, 10, 10, 156, "DCDCHiThCh7"); m_fieldMap["DCDCHiThCh7"] = &AMACv2RegMap::DCDCHiThCh7;
-  DCDCHiThCh8.initReg(m_cfg, RW, 0x3FF, 10, 20, 156, "DCDCHiThCh8"); m_fieldMap["DCDCHiThCh8"] = &AMACv2RegMap::DCDCHiThCh8;
-  // 157 - DCDCHiTh3
-  DCDCHiThCh9.initReg(m_cfg, RW, 0x3FF, 10, 0, 157, "DCDCHiThCh9"); m_fieldMap["DCDCHiThCh9"] = &AMACv2RegMap::DCDCHiThCh9;
-  DCDCHiThCh10.initReg(m_cfg, RW, 0x3FF, 10, 10, 157, "DCDCHiThCh10"); m_fieldMap["DCDCHiThCh10"] = &AMACv2RegMap::DCDCHiThCh10;
-  DCDCHiThCh11.initReg(m_cfg, RW, 0x3FF, 10, 20, 157, "DCDCHiThCh11"); m_fieldMap["DCDCHiThCh11"] = &AMACv2RegMap::DCDCHiThCh11;
-  // 158 - DCDCHiTh4
-  DCDCHiThCh12.initReg(m_cfg, RW, 0x3FF, 10, 0, 158, "DCDCHiThCh12"); m_fieldMap["DCDCHiThCh12"] = &AMACv2RegMap::DCDCHiThCh12;
-  DCDCHiThCh13.initReg(m_cfg, RW, 0x3FF, 10, 10, 158, "DCDCHiThCh13"); m_fieldMap["DCDCHiThCh13"] = &AMACv2RegMap::DCDCHiThCh13;
-  DCDCHiThCh14.initReg(m_cfg, RW, 0x3FF, 10, 20, 158, "DCDCHiThCh14"); m_fieldMap["DCDCHiThCh14"] = &AMACv2RegMap::DCDCHiThCh14;
-  // 159 - DCDCHiTh5
-  DCDCHiThCh15.initReg(m_cfg, RW, 0x3FF, 10, 0, 159, "DCDCHiThCh15"); m_fieldMap["DCDCHiThCh15"] = &AMACv2RegMap::DCDCHiThCh15;
-  // 160 - WRNLoTh0
-  WRNLoThCh0.initReg(m_cfg, RW, 0, 10, 0, 160, "WRNLoThCh0"); m_fieldMap["WRNLoThCh0"] = &AMACv2RegMap::WRNLoThCh0;
-  WRNLoThCh1.initReg(m_cfg, RW, 0, 10, 10, 160, "WRNLoThCh1"); m_fieldMap["WRNLoThCh1"] = &AMACv2RegMap::WRNLoThCh1;
-  WRNLoThCh2.initReg(m_cfg, RW, 0, 10, 20, 160, "WRNLoThCh2"); m_fieldMap["WRNLoThCh2"] = &AMACv2RegMap::WRNLoThCh2;
-  // 161 - WRNLoTh1
-  WRNLoThCh3.initReg(m_cfg, RW, 0, 10, 0, 161, "WRNLoThCh3"); m_fieldMap["WRNLoThCh3"] = &AMACv2RegMap::WRNLoThCh3;
-  WRNLoThCh4.initReg(m_cfg, RW, 0, 10, 10, 161, "WRNLoThCh4"); m_fieldMap["WRNLoThCh4"] = &AMACv2RegMap::WRNLoThCh4;
-  WRNLoThCh5.initReg(m_cfg, RW, 0, 10, 20, 161, "WRNLoThCh5"); m_fieldMap["WRNLoThCh5"] = &AMACv2RegMap::WRNLoThCh5;
-  // 162 - WRNLoTh2
-  WRNLoThCh6.initReg(m_cfg, RW, 0, 10, 0, 162, "WRNLoThCh6"); m_fieldMap["WRNLoThCh6"] = &AMACv2RegMap::WRNLoThCh6;
-  WRNLoThCh7.initReg(m_cfg, RW, 0, 10, 10, 162, "WRNLoThCh7"); m_fieldMap["WRNLoThCh7"] = &AMACv2RegMap::WRNLoThCh7;
-  WRNLoThCh8.initReg(m_cfg, RW, 0, 10, 20, 162, "WRNLoThCh8"); m_fieldMap["WRNLoThCh8"] = &AMACv2RegMap::WRNLoThCh8;
-  // 163 - WRNLoTh3
-  WRNLoThCh9.initReg(m_cfg, RW, 0, 10, 0, 163, "WRNLoThCh9"); m_fieldMap["WRNLoThCh9"] = &AMACv2RegMap::WRNLoThCh9;
-  WRNLoThCh10.initReg(m_cfg, RW, 0, 10, 10, 163, "WRNLoThCh10"); m_fieldMap["WRNLoThCh10"] = &AMACv2RegMap::WRNLoThCh10;
-  WRNLoThCh11.initReg(m_cfg, RW, 0, 10, 20, 163, "WRNLoThCh11"); m_fieldMap["WRNLoThCh11"] = &AMACv2RegMap::WRNLoThCh11;
-  // 164 - WRNLoTh4
-  WRNLoThCh12.initReg(m_cfg, RW, 0, 10, 0, 164, "WRNLoThCh12"); m_fieldMap["WRNLoThCh12"] = &AMACv2RegMap::WRNLoThCh12;
-  WRNLoThCh13.initReg(m_cfg, RW, 0, 10, 10, 164, "WRNLoThCh13"); m_fieldMap["WRNLoThCh13"] = &AMACv2RegMap::WRNLoThCh13;
-  WRNLoThCh14.initReg(m_cfg, RW, 0, 10, 20, 164, "WRNLoThCh14"); m_fieldMap["WRNLoThCh14"] = &AMACv2RegMap::WRNLoThCh14;
-  // 165 - WRNLoTh5
-  WRNLoThCh15.initReg(m_cfg, RW, 0, 10, 0, 165, "WRNLoThCh15"); m_fieldMap["WRNLoThCh15"] = &AMACv2RegMap::WRNLoThCh15;
-  // 166 - WRNHiTh0
-  WRNHiThCh0.initReg(m_cfg, RW, 0x3FF, 10, 0, 166, "WRNLoThCh0"); m_fieldMap["WRNLoThCh0"] = &AMACv2RegMap::WRNLoThCh0;
-  WRNHiThCh1.initReg(m_cfg, RW, 0x3FF, 10, 10, 166, "WRNLoThCh1"); m_fieldMap["WRNLoThCh1"] = &AMACv2RegMap::WRNLoThCh1;
-  WRNHiThCh2.initReg(m_cfg, RW, 0x3FF, 10, 20, 166, "WRNLoThCh2"); m_fieldMap["WRNLoThCh2"] = &AMACv2RegMap::WRNLoThCh2;
-  // 167 - WRNHiTh1
-  WRNHiThCh3.initReg(m_cfg, RW, 0x3FF, 10, 0, 167, "WRNHiThCh3"); m_fieldMap["WRNHiThCh3"] = &AMACv2RegMap::WRNHiThCh3;
-  WRNHiThCh4.initReg(m_cfg, RW, 0x3FF, 10, 10, 167, "WRNHiThCh4"); m_fieldMap["WRNHiThCh4"] = &AMACv2RegMap::WRNHiThCh4;
-  WRNHiThCh5.initReg(m_cfg, RW, 0x3FF, 10, 20, 167, "WRNHiThCh5"); m_fieldMap["WRNHiThCh5"] = &AMACv2RegMap::WRNHiThCh5;
-  // 168 - WRNHiTh2
-  WRNHiThCh6.initReg(m_cfg, RW, 0x3FF, 10, 0, 168, "WRNHiThCh6"); m_fieldMap["WRNHiThCh6"] = &AMACv2RegMap::WRNHiThCh6;
-  WRNHiThCh7.initReg(m_cfg, RW, 0x3FF, 10, 10, 168, "WRNHiThCh7"); m_fieldMap["WRNHiThCh7"] = &AMACv2RegMap::WRNHiThCh7;
-  WRNHiThCh8.initReg(m_cfg, RW, 0x3FF, 10, 20, 168, "WRNHiThCh8"); m_fieldMap["WRNHiThCh8"] = &AMACv2RegMap::WRNHiThCh8;
-  // 169 - WRNHiTh3
-  WRNHiThCh9.initReg(m_cfg, RW, 0x3FF, 10, 0, 169, "WRNHiThCh9"); m_fieldMap["WRNHiThCh9"] = &AMACv2RegMap::WRNHiThCh9;
-  WRNHiThCh10.initReg(m_cfg, RW, 0x3FF, 10, 10, 169, "WRNHiThCh10"); m_fieldMap["WRNHiThCh10"] = &AMACv2RegMap::WRNHiThCh10;
-  WRNHiThCh11.initReg(m_cfg, RW, 0x3FF, 10, 20, 169, "WRNHiThCh11"); m_fieldMap["WRNHiThCh11"] = &AMACv2RegMap::WRNHiThCh11;
-  // 170 - WRNHiTh4
-  WRNHiThCh12.initReg(m_cfg, RW, 0x3FF, 10, 0, 170, "WRNHiThCh12"); m_fieldMap["WRNHiThCh12"] = &AMACv2RegMap::WRNHiThCh12;
-  WRNHiThCh13.initReg(m_cfg, RW, 0x3FF, 10, 10, 170, "WRNHiThCh13"); m_fieldMap["WRNHiThCh13"] = &AMACv2RegMap::WRNHiThCh13;
-  WRNHiThCh14.initReg(m_cfg, RW, 0x3FF, 10, 20, 170, "WRNHiThCh14"); m_fieldMap["WRNHiThCh14"] = &AMACv2RegMap::WRNHiThCh14;
-  // 171 - WRNHiTh5
-  WRNHiThCh15.initReg(m_cfg, RW, 0x3FF, 10, 0, 171, "WRNHiThCh15"); m_fieldMap["WRNHiThCh15"] = &AMACv2RegMap::WRNHiThCh15;
+  //
+  // Create register maps
+  m_registers = {
+    &AMACv2RegMap::RegisterStatus, &AMACv2RegMap::RegisterHxFlags, &AMACv2RegMap::RegisterHyFlags, &AMACv2RegMap::RegisterHV0Flags, &AMACv2RegMap::RegisterHV2Flags, &AMACv2RegMap::RegisterDCDCFlags, &AMACv2RegMap::RegisterWRNHxFlags, &AMACv2RegMap::RegisterSynFlags,
+    &AMACv2RegMap::RegisterValue0,&AMACv2RegMap::RegisterValue1,&AMACv2RegMap::RegisterValue2,&AMACv2RegMap::RegisterValue3,&AMACv2RegMap::RegisterValue4,&AMACv2RegMap::RegisterValue5,
+    &AMACv2RegMap::RegisterSerNum,
+    &AMACv2RegMap::RegisterFlagResets,&AMACv2RegMap::RegisterLogicReset,&AMACv2RegMap::RegisterHardReset,
+    &AMACv2RegMap::RegisterCntSet,&AMACv2RegMap::RegisterCntSetC,&AMACv2RegMap::RegisterDCDCen,&AMACv2RegMap::RegisterDCDCenC,&AMACv2RegMap::RegisterIlock,&AMACv2RegMap::RegisterIlockC,&AMACv2RegMap::RegisterRstCnt,&AMACv2RegMap::RegisterRstCntC,&AMACv2RegMap::RegisterAMen,&AMACv2RegMap::RegisterAMenC,&AMACv2RegMap::RegisterAMpwr,&AMACv2RegMap::RegisterAMpwrC,&AMACv2RegMap::RegisterBgCnt,&AMACv2RegMap::RegisterAMCnt,&AMACv2RegMap::RegisterDACs0,&AMACv2RegMap::RegisterDACbias,&AMACv2RegMap::RegisterAMACCnt,&AMACv2RegMap::RegisterNTCRange,&AMACv2RegMap::RegisterLVCurCal,
+    &AMACv2RegMap::RegisterHxICfg,&AMACv2RegMap::RegisterHyICfg,&AMACv2RegMap::RegisterHV0ICfg,&AMACv2RegMap::RegisterHV2ICfg,&AMACv2RegMap::RegisterDCDCICfg,&AMACv2RegMap::RegisterWRNICfg,
+    &AMACv2RegMap::RegisterHxTLUT,&AMACv2RegMap::RegisterHxModLUT1,&AMACv2RegMap::RegisterHxModLUT2,
+    &AMACv2RegMap::RegisterHyTLUT,&AMACv2RegMap::RegisterHyModLUT1,&AMACv2RegMap::RegisterHyModLUT2,
+    &AMACv2RegMap::RegisterHV0TLUT,&AMACv2RegMap::RegisterHV0ModLUT1,&AMACv2RegMap::RegisterHV0ModLUT2,
+    &AMACv2RegMap::RegisterHV2TLUT,&AMACv2RegMap::RegisterHV2ModLUT1,&AMACv2RegMap::RegisterHV2ModLUT2,
+    &AMACv2RegMap::RegisterDCDCTLUT,&AMACv2RegMap::RegisterDCDCModLUT1,&AMACv2RegMap::RegisterDCDCModLUT2,
+    &AMACv2RegMap::RegisterWRNTLUT,&AMACv2RegMap::RegisterWRNModLUT1,&AMACv2RegMap::RegisterWRNModLUT2,
+    &AMACv2RegMap::RegisterHxFlagEn,&AMACv2RegMap::RegisterHyFlagEn,&AMACv2RegMap::RegisterHV0FlagEn,&AMACv2RegMap::RegisterHV2FlagEn,&AMACv2RegMap::RegisterDCDCFlagEn,&AMACv2RegMap::RegisterSynFlagEn,
+    //AMACv2&AMACv2RegMap::Register&AMACv2RegMap::RegisterWRNFlagEn,
+    &AMACv2RegMap::RegisterHxLoTh0,&AMACv2RegMap::RegisterHxLoTh1,&AMACv2RegMap::RegisterHxLoTh2,&AMACv2RegMap::RegisterHxLoTh3,&AMACv2RegMap::RegisterHxLoTh4,&AMACv2RegMap::RegisterHxLoTh5,
+    &AMACv2RegMap::RegisterHxHiTh0,&AMACv2RegMap::RegisterHxHiTh1,&AMACv2RegMap::RegisterHxHiTh2,&AMACv2RegMap::RegisterHxHiTh3,&AMACv2RegMap::RegisterHxHiTh4,&AMACv2RegMap::RegisterHxHiTh5,
+    &AMACv2RegMap::RegisterHyLoTh0,&AMACv2RegMap::RegisterHyLoTh1,&AMACv2RegMap::RegisterHyLoTh2,&AMACv2RegMap::RegisterHyLoTh3,&AMACv2RegMap::RegisterHyLoTh4,&AMACv2RegMap::RegisterHyLoTh5,
+    &AMACv2RegMap::RegisterHyHiTh0,&AMACv2RegMap::RegisterHyHiTh1,&AMACv2RegMap::RegisterHyHiTh2,&AMACv2RegMap::RegisterHyHiTh3,&AMACv2RegMap::RegisterHyHiTh4,&AMACv2RegMap::RegisterHyHiTh5,
+    &AMACv2RegMap::RegisterHV0LoTh0,&AMACv2RegMap::RegisterHV0LoTh1,&AMACv2RegMap::RegisterHV0LoTh2,&AMACv2RegMap::RegisterHV0LoTh3,&AMACv2RegMap::RegisterHV0LoTh4,&AMACv2RegMap::RegisterHV0LoTh5,
+    &AMACv2RegMap::RegisterHV0HiTh0,&AMACv2RegMap::RegisterHV0HiTh1,&AMACv2RegMap::RegisterHV0HiTh2,&AMACv2RegMap::RegisterHV0HiTh3,&AMACv2RegMap::RegisterHV0HiTh4,&AMACv2RegMap::RegisterHV0HiTh5,
+    &AMACv2RegMap::RegisterHV2LoTh0,&AMACv2RegMap::RegisterHV2LoTh1,&AMACv2RegMap::RegisterHV2LoTh2,&AMACv2RegMap::RegisterHV2LoTh3,&AMACv2RegMap::RegisterHV2LoTh4,&AMACv2RegMap::RegisterHV2LoTh5,
+    &AMACv2RegMap::RegisterHV2HiTh0,&AMACv2RegMap::RegisterHV2HiTh1,&AMACv2RegMap::RegisterHV2HiTh2,&AMACv2RegMap::RegisterHV2HiTh3,&AMACv2RegMap::RegisterHV2HiTh4,&AMACv2RegMap::RegisterHV2HiTh5,
+    &AMACv2RegMap::RegisterDCDCLoTh0,&AMACv2RegMap::RegisterDCDCLoTh1,&AMACv2RegMap::RegisterDCDCLoTh2,&AMACv2RegMap::RegisterDCDCLoTh3,&AMACv2RegMap::RegisterDCDCLoTh4,&AMACv2RegMap::RegisterDCDCLoTh5,
+    &AMACv2RegMap::RegisterDCDCHiTh0,&AMACv2RegMap::RegisterDCDCHiTh1,&AMACv2RegMap::RegisterDCDCHiTh2,&AMACv2RegMap::RegisterDCDCHiTh3,&AMACv2RegMap::RegisterDCDCHiTh4,&AMACv2RegMap::RegisterDCDCHiTh5,
+    &AMACv2RegMap::RegisterWRNLoTh0,&AMACv2RegMap::RegisterWRNLoTh1,&AMACv2RegMap::RegisterWRNLoTh2,&AMACv2RegMap::RegisterWRNLoTh3,&AMACv2RegMap::RegisterWRNLoTh4,&AMACv2RegMap::RegisterWRNLoTh5,
+    &AMACv2RegMap::RegisterWRNHiTh0,&AMACv2RegMap::RegisterWRNHiTh1,&AMACv2RegMap::RegisterWRNHiTh2,&AMACv2RegMap::RegisterWRNHiTh3,&AMACv2RegMap::RegisterWRNHiTh4,&AMACv2RegMap::RegisterWRNHiTh5,
+  };
+
+  for(AMACv2Register AMACv2RegMap::* reg : m_registers)
+    {
+      m_regAddrMap[(this->*reg).getAddress()]=reg;
+      m_regMap    [(this->*reg).getName   ()]=reg;
+    }
+  
+
+  //
+  //
+  m_fields =
+    {
+      // 0 - Status
+      &AMACv2RegMap::StatusAM, &AMACv2RegMap::StatusWARN, &AMACv2RegMap::StatusDCDC, &AMACv2RegMap::StatusHV3, &AMACv2RegMap::StatusHV2, &AMACv2RegMap::StatusHV1, &AMACv2RegMap::StatusHV0, &AMACv2RegMap::StatusY2LDO, &AMACv2RegMap::StatusY1LDO, &AMACv2RegMap::StatusY0LDO, &AMACv2RegMap::StatusX2LDO, &AMACv2RegMap::StatusX1LDO, &AMACv2RegMap::StatusX0LDO, &AMACv2RegMap::StatusGPI, &AMACv2RegMap::StatusPGOOD, &AMACv2RegMap::StatusILockWARN, &AMACv2RegMap::StatusILockDCDC, &AMACv2RegMap::StatusILockHV2, &AMACv2RegMap::StatusILockHV2, &AMACv2RegMap::StatusILockYLDO, &AMACv2RegMap::StatusILockxLDO,
+      // 1 - HxFlags
+      &AMACv2RegMap::HxFlagsHi, &AMACv2RegMap::HxFlagsLo,
+      // 2 - HyFlags
+      &AMACv2RegMap::HyFlagsHi, &AMACv2RegMap::HyFlagsLo,
+      // 3 - HV0Flags
+      &AMACv2RegMap::HV0FlagsHi, &AMACv2RegMap::HV0FlagsLo,
+      // 4 - HV2Flags
+      &AMACv2RegMap::HV2FlagsHi, &AMACv2RegMap::HV2FlagsLo,
+      // 5 - DCDCflags
+      &AMACv2RegMap::DCDCflagsHi, &AMACv2RegMap::DCDCflagsLo,
+      // 6 - WRNflags
+      &AMACv2RegMap::WRNflagsHi, &AMACv2RegMap::WRNflagsLo,
+      // 7 - SynFlags
+      &AMACv2RegMap::SynFlagsWRN, &AMACv2RegMap::SynFlagsDCDC, &AMACv2RegMap::SynFlagsHV2, &AMACv2RegMap::SynFlagsHV2, &AMACv2RegMap::SynFlagsHy, &AMACv2RegMap::SynFlagsHx,
+      // 10 - Value0
+      &AMACv2RegMap::Value0AMen, &AMACv2RegMap::Ch0Value, &AMACv2RegMap::Ch1Value, &AMACv2RegMap::Ch2Value,
+      // 11 - Value1
+      &AMACv2RegMap::Value1AMen, &AMACv2RegMap::Ch3Value, &AMACv2RegMap::Ch4Value, &AMACv2RegMap::Ch5Value,
+      // 12 - Value2
+      &AMACv2RegMap::Value2AMen, &AMACv2RegMap::Ch6Value, &AMACv2RegMap::Ch7Value, &AMACv2RegMap::Ch8Value,
+      // 13 - Value3
+      &AMACv2RegMap::Value3AMen, &AMACv2RegMap::Ch9Value, &AMACv2RegMap::Ch10Value, &AMACv2RegMap::Ch11Value,
+      // 14 - Value4
+      &AMACv2RegMap::Value4AMen, &AMACv2RegMap::Ch12Value, &AMACv2RegMap::Ch13Value, &AMACv2RegMap::Ch14Value,
+      // 15 - Value5
+      &AMACv2RegMap::Value5AMen, &AMACv2RegMap::Ch15Value,
+      // 31 - SerNum
+      &AMACv2RegMap::PadID, &AMACv2RegMap::SerNum,
+      // 32 - FlagResets
+      &AMACv2RegMap::FlagResetWRN, &AMACv2RegMap::FlagResetDCDC, &AMACv2RegMap::FlagResetHV2, &AMACv2RegMap::FlagResetHV0, &AMACv2RegMap::FlagResetXLDO, &AMACv2RegMap::FlagResetYLDO,
+      // 33 - LogicReset
+      &AMACv2RegMap::LogicReset,
+      // 34 - HardReset
+      &AMACv2RegMap::HardReset,
+      // 40 - CntSet
+      &AMACv2RegMap::CntSetHV3frq, &AMACv2RegMap::CntSetHV3en, &AMACv2RegMap::CntSetHV2frq, &AMACv2RegMap::CntSetHV2en, &AMACv2RegMap::CntSetHV1frq, &AMACv2RegMap::CntSetHV1en, &AMACv2RegMap::CntSetHV0frq, &AMACv2RegMap::CntSetHV0en, &AMACv2RegMap::CntSetHyLDO2en, &AMACv2RegMap::CntSetHyLDO1en, &AMACv2RegMap::CntSetHyLDO0en, &AMACv2RegMap::CntSetHxLDO2en, &AMACv2RegMap::CntSetHxLDO1en, &AMACv2RegMap::CntSetHxLDO0en, &AMACv2RegMap::CntSetWARN,
+      // 41 - CntSetC
+      &AMACv2RegMap::CntSetCHV3frq, &AMACv2RegMap::CntSetCHV3en, &AMACv2RegMap::CntSetCHV2frq, &AMACv2RegMap::CntSetCHV2en, &AMACv2RegMap::CntSetCHV1frq, &AMACv2RegMap::CntSetCHV1en, &AMACv2RegMap::CntSetCHV0frq, &AMACv2RegMap::CntSetCHV0en, &AMACv2RegMap::CntSetCHyLDO2en, &AMACv2RegMap::CntSetCHyLDO1en, &AMACv2RegMap::CntSetCHyLDO0en, &AMACv2RegMap::CntSetCHxLDO2en, &AMACv2RegMap::CntSetCHxLDO1en, &AMACv2RegMap::CntSetCHxLDO0en, &AMACv2RegMap::CntSetCWARN,
+      // 42 - DCDCen
+      &AMACv2RegMap::DCDCAdj, &AMACv2RegMap::DCDCen,
+      // 43 - DCDCenC
+      &AMACv2RegMap::DCDCAdjC, &AMACv2RegMap::DCDCenC,
+      // 44 - Ilock
+      &AMACv2RegMap::IlockWRN, &AMACv2RegMap::IlockDCDC, &AMACv2RegMap::IlockHV2, &AMACv2RegMap::IlockHV2, &AMACv2RegMap::IlockHy, &AMACv2RegMap::IlockHx,
+      // 45 - IlockC
+      &AMACv2RegMap::IlockCWRN, &AMACv2RegMap::IlockCDCDC, &AMACv2RegMap::IlockCHV2, &AMACv2RegMap::IlockCHV2, &AMACv2RegMap::IlockCHy, &AMACv2RegMap::IlockCHx,
+      // 46 - RstCnt
+      &AMACv2RegMap::RstCntHyHCCresetB, &AMACv2RegMap::RstCntHxHCCresetB, &AMACv2RegMap::RstCntOF,
+      // 47 - RstCntC
+      &AMACv2RegMap::RstCntCHyHCCresetB, &AMACv2RegMap::RstCntCHxHCCresetB, &AMACv2RegMap::RstCntCOF,
+      // 48 - AMen
+      &AMACv2RegMap::AMzeroCalib, &AMACv2RegMap::AMen,
+      // 49 - AMenC
+      &AMACv2RegMap::AMzeroCalibC, &AMACv2RegMap::AMenC,
+      // 50 - AMpwr
+      &AMACv2RegMap::ReqDCDCPGOOD, &AMACv2RegMap::DCDCenToPwrAMAC,
+      // 51 - AMpwrC
+      &AMACv2RegMap::ReqDCDCPGOODC, &AMACv2RegMap::DCDCenToPwrAMACC,
+      // 52 - BgCnt
+      &AMACv2RegMap::AMbgen, &AMACv2RegMap::AMbg, &AMACv2RegMap::VDDbgen, &AMACv2RegMap::VDDbg,
+      // 53 - AMcnt
+      &AMACv2RegMap::AMintCalib, &AMACv2RegMap::Ch13Mux, &AMACv2RegMap::Ch12Mux, &AMACv2RegMap::Ch5Mux, &AMACv2RegMap::Ch4Mux, &AMACv2RegMap::Ch3Mux,
+      // 54 - Dacs0
+      &AMACv2RegMap::DACShunty, &AMACv2RegMap::DACShuntx, &AMACv2RegMap::DACCALy, &AMACv2RegMap::DACCalx,
+      // 55 - DACbias
+      &AMACv2RegMap::DACbias,
+      // 56 - AMACcnt
+      &AMACv2RegMap::HVcurGain, &AMACv2RegMap::DRcomMode, &AMACv2RegMap::DRcurr, &AMACv2RegMap::RingOscFrq,
+      // 57 - NTC
+      &AMACv2RegMap::CTAToffset, &AMACv2RegMap::NTCpbCal, &AMACv2RegMap::NTCpbSenseRange, &AMACv2RegMap::NTCy0Cal, &AMACv2RegMap::NTCy0SenseRange, &AMACv2RegMap::NTCx0Cal, &AMACv2RegMap::NTCx0SenseRange,
+      // 58 - LvCurCal
+      &AMACv2RegMap::DCDCoOffset, &AMACv2RegMap::DCDCoZeroReading, &AMACv2RegMap::DCDCoN, &AMACv2RegMap::DCDCoP, &AMACv2RegMap::DCDCiZeroReading, &AMACv2RegMap::DCDCiRangeSW, &AMACv2RegMap::DCDCiOffset, &AMACv2RegMap::DCDCiP, &AMACv2RegMap::DCDCiN,
+      // 60 - HxICm_cfg
+      &AMACv2RegMap::HxLAM, &AMACv2RegMap::HxFlagsLatch, &AMACv2RegMap::HxFlagsLogic, &AMACv2RegMap::HxFlagsLogic, &AMACv2RegMap::HxFlagsLogic,
+      // 61 - HyICm_cfg
+      &AMACv2RegMap::HyLAM, &AMACv2RegMap::HyFlagsLatch, &AMACv2RegMap::HyFlagsLogic, &AMACv2RegMap::HyFlagsLogic, &AMACv2RegMap::HyFlagsLogic,
+      // 62 - HV0ICm_cfg
+      &AMACv2RegMap::HV0LAM, &AMACv2RegMap::HV0FlagsLatch, &AMACv2RegMap::HV0FlagsLogic, &AMACv2RegMap::HV0FlagsLogic, &AMACv2RegMap::HV0FlagsLogic,
+      // 63 - HV2ICm_cfg
+      &AMACv2RegMap::HV2LAM, &AMACv2RegMap::HV2FlagsLatch, &AMACv2RegMap::HV2FlagsLogic, &AMACv2RegMap::HV2FlagsLogic, &AMACv2RegMap::HV2FlagsLogic,
+      // 64 - DCDCICm_cfg
+      &AMACv2RegMap::DCDCLAM, &AMACv2RegMap::DCDCFlagsLatch, &AMACv2RegMap::DCDCFlagsLogic, &AMACv2RegMap::DCDCFlagsLogic, &AMACv2RegMap::DCDCFlagsLogic,
+      // 65 - WRNICm_cfg
+      &AMACv2RegMap::WRNLAM, &AMACv2RegMap::WRNFlagsLatch, &AMACv2RegMap::WRNFlagsLogic, &AMACv2RegMap::WRNFlagsLogic, &AMACv2RegMap::WRNFlagsLogic,
+      // 70 - HxTlut
+      &AMACv2RegMap::HxTlut,
+      // 71 - HxModlut1
+      &AMACv2RegMap::HxModlut1,
+      // 72 - HxModlut2
+      &AMACv2RegMap::HxModlut2,
+      // 73 - HyTlut
+      &AMACv2RegMap::HyTlut,
+      // 74 - HyModlut1
+      &AMACv2RegMap::HyModlut1,
+      // 75 - HyModlut2
+      &AMACv2RegMap::HyModlut2,
+      // 76 - HV0Tlut,
+      &AMACv2RegMap::HV0Tlut,
+      // 77 - HV0Modlut1
+      &AMACv2RegMap::HV0Modlut1,
+      // 78 - HV0Modlut2
+      &AMACv2RegMap::HV0Modlut2,
+      // 79 - HV2Tlut
+      &AMACv2RegMap::HV2Tlut,
+      // 80 - HV2Modlut1
+      &AMACv2RegMap::HV2Modlut1,
+      // 81 - HV2Modlut2
+      &AMACv2RegMap::HV2Modlut2,
+      // 82 - DCDCTlut
+      &AMACv2RegMap::DCDCTlut,
+      // 83 - DCDCModlut1
+      &AMACv2RegMap::DCDCModlut1,
+      // 84 - DCDCModlut2
+      &AMACv2RegMap::DCDCModlut2,
+      // 85 - WRNTlut
+      &AMACv2RegMap::WRNTlut,
+      // 86 - WRNModlut1
+      &AMACv2RegMap::WRNModlut1,
+      // 87 - WRNModlut2
+      &AMACv2RegMap::WRNModlut2,
+      // 90 - HxFlagEn
+      &AMACv2RegMap::HxFlagsEnHi, &AMACv2RegMap::HxFlagsEnLo,
+      // 91 - HyFlagEn
+      &AMACv2RegMap::HyFlagsEnHi, &AMACv2RegMap::HyFlagsEnLo,
+      // 92 - HV0FlagEn
+      &AMACv2RegMap::HV0FlagsEnHi, &AMACv2RegMap::HV0FlagsEnLo,
+      // 93 - HV2FlagEn
+      &AMACv2RegMap::HxFlagsEnHi, &AMACv2RegMap::HxFlagsEnLo,
+      // 94 - DCDCFlagEn
+      &AMACv2RegMap::DCDCFlagsEnHi, &AMACv2RegMap::DCDCFlagsEnLo,
+      // 94 - WRNFlagEn
+      &AMACv2RegMap::WRNFlagsEnHi, &AMACv2RegMap::WRNFlagsEnLo,
+      // 95 - SynFlagEn
+      &AMACv2RegMap::WRNsynFlagEnHi, &AMACv2RegMap::WRNsynFlagEnLo, &AMACv2RegMap::DCDCsynFlagEnHi, &AMACv2RegMap::DCDCsynFlagEnLo, &AMACv2RegMap::HV2synFlagEnHi, &AMACv2RegMap::HV2synFlagEnLo, &AMACv2RegMap::HV0synFlagEnHi, &AMACv2RegMap::HV0synFlagEnLo, &AMACv2RegMap::HysynFlagEnHi, &AMACv2RegMap::HysynFlagEnLo, &AMACv2RegMap::HxsynFlagEnHi, &AMACv2RegMap::HxsynFlagEnLo,
+      // 100 - HxLoTh0
+      &AMACv2RegMap::HxLoThCh0, &AMACv2RegMap::HxLoThCh1, &AMACv2RegMap::HxLoThCh2,
+      // 101 - HxLoTh1
+      &AMACv2RegMap::HxLoThCh3, &AMACv2RegMap::HxLoThCh4, &AMACv2RegMap::HxLoThCh5,
+      // 102 - HxLoTh2
+      &AMACv2RegMap::HxLoThCh6, &AMACv2RegMap::HxLoThCh7, &AMACv2RegMap::HxLoThCh8,
+      // 103 - HxLoTh3
+      &AMACv2RegMap::HxLoThCh9, &AMACv2RegMap::HxLoThCh10, &AMACv2RegMap::HxLoThCh11,
+      // 104 - HxLoTh4
+      &AMACv2RegMap::HxLoThCh12, &AMACv2RegMap::HxLoThCh13, &AMACv2RegMap::HxLoThCh14,
+      // 105 - HxLoTh5
+      &AMACv2RegMap::HxLoThCh15,
+      // 106 - HxHiTh0
+      &AMACv2RegMap::HxHiThCh0, &AMACv2RegMap::HxHiThCh1, &AMACv2RegMap::HxHiThCh2,
+      // 107 - HxHiTh1
+      &AMACv2RegMap::HxHiThCh3, &AMACv2RegMap::HxHiThCh4, &AMACv2RegMap::HxHiThCh5,
+      // 108 - HxHiTh2
+      &AMACv2RegMap::HxHiThCh6, &AMACv2RegMap::HxHiThCh7, &AMACv2RegMap::HxHiThCh8,
+      // 109 - HxHiTh3
+      &AMACv2RegMap::HxHiThCh9, &AMACv2RegMap::HxHiThCh10, &AMACv2RegMap::HxHiThCh11,
+      // 110 - HxHiTh4
+      &AMACv2RegMap::HxHiThCh12, &AMACv2RegMap::HxHiThCh13, &AMACv2RegMap::HxHiThCh14,
+      // 111 - HxHiTh5
+      &AMACv2RegMap::HxHiThCh15,
+      // 112 - HyLoTh0
+      &AMACv2RegMap::HyLoThCh0, &AMACv2RegMap::HyLoThCh1, &AMACv2RegMap::HyLoThCh2,
+      // 113 - HyLoTh1
+      &AMACv2RegMap::HyLoThCh3, &AMACv2RegMap::HyLoThCh4, &AMACv2RegMap::HyLoThCh5,
+      // 114 - HyLoTh2
+      &AMACv2RegMap::HyLoThCh6, &AMACv2RegMap::HyLoThCh7, &AMACv2RegMap::HyLoThCh8,
+      // 115 - HyLoTh3
+      &AMACv2RegMap::HyLoThCh9, &AMACv2RegMap::HyLoThCh10, &AMACv2RegMap::HyLoThCh11,
+      // 116 - HyLoTh4
+      &AMACv2RegMap::HyLoThCh12, &AMACv2RegMap::HyLoThCh13, &AMACv2RegMap::HyLoThCh14,
+      // 117 - HyLoTh5
+      &AMACv2RegMap::HyLoThCh15,
+      // 118 - HyHiTh0
+      &AMACv2RegMap::HyLoThCh0, &AMACv2RegMap::HyLoThCh1, &AMACv2RegMap::HyLoThCh2,
+      // 119 - HyHiTh1
+      &AMACv2RegMap::HyHiThCh3, &AMACv2RegMap::HyHiThCh4, &AMACv2RegMap::HyHiThCh5,
+      // 120 - HyHiTh2
+      &AMACv2RegMap::HyHiThCh6, &AMACv2RegMap::HyHiThCh7, &AMACv2RegMap::HyHiThCh8,
+      // 121 - HyHiTh3
+      &AMACv2RegMap::HyHiThCh9, &AMACv2RegMap::HyHiThCh10, &AMACv2RegMap::HyHiThCh11,
+      // 122 - HyHiTh4
+      &AMACv2RegMap::HyHiThCh12, &AMACv2RegMap::HyHiThCh13, &AMACv2RegMap::HyHiThCh14,
+      // 123 - HyHiTh5
+      &AMACv2RegMap::HyHiThCh15,
+      // 124 - HV0LoTh0
+      &AMACv2RegMap::HV0LoThCh0, &AMACv2RegMap::HV0LoThCh1, &AMACv2RegMap::HV0LoThCh2,
+      // 125 - HV0LoTh1
+      &AMACv2RegMap::HV0LoThCh3, &AMACv2RegMap::HV0LoThCh4, &AMACv2RegMap::HV0LoThCh5,
+      // 126 - HV0LoTh2
+      &AMACv2RegMap::HV0LoThCh6, &AMACv2RegMap::HV0LoThCh7, &AMACv2RegMap::HV0LoThCh8,
+      // 127 - HV0LoTh3
+      &AMACv2RegMap::HV0LoThCh9, &AMACv2RegMap::HV0LoThCh10, &AMACv2RegMap::HV0LoThCh11,
+      // 128 - HV0LoTh4
+      &AMACv2RegMap::HV0LoThCh12, &AMACv2RegMap::HV0LoThCh13, &AMACv2RegMap::HV0LoThCh14,
+      // 129 - HV0LoTh5
+      &AMACv2RegMap::HV0LoThCh15,
+      // 130 - HV0HiTh0
+      &AMACv2RegMap::HV0LoThCh0, &AMACv2RegMap::HV0LoThCh1, &AMACv2RegMap::HV0LoThCh2,
+      // 131 - HV0HiTh1
+      &AMACv2RegMap::HV0HiThCh3, &AMACv2RegMap::HV0HiThCh4, &AMACv2RegMap::HV0HiThCh5,
+      // 132 - HV0HiTh2
+      &AMACv2RegMap::HV0HiThCh6, &AMACv2RegMap::HV0HiThCh7, &AMACv2RegMap::HV0HiThCh8,
+      // 133 - HV0HiTh3
+      &AMACv2RegMap::HV0HiThCh9, &AMACv2RegMap::HV0HiThCh10, &AMACv2RegMap::HV0HiThCh11,
+      // 134 - HV0HiTh4
+      &AMACv2RegMap::HV0HiThCh12, &AMACv2RegMap::HV0HiThCh13, &AMACv2RegMap::HV0HiThCh14,
+      // 135 - HV0HiTh5
+      &AMACv2RegMap::HV0HiThCh15,
+      // 136 - HV2LoTh0
+      &AMACv2RegMap::HV2LoThCh0, &AMACv2RegMap::HV2LoThCh1, &AMACv2RegMap::HV2LoThCh2,
+      // 137 - HV2LoTh1
+      &AMACv2RegMap::HV2LoThCh3, &AMACv2RegMap::HV2LoThCh4, &AMACv2RegMap::HV2LoThCh5,
+      // 138 - HV2LoTh2
+      &AMACv2RegMap::HV2LoThCh6, &AMACv2RegMap::HV2LoThCh7, &AMACv2RegMap::HV2LoThCh8,
+      // 139 - HV2LoTh3
+      &AMACv2RegMap::HV2LoThCh9, &AMACv2RegMap::HV2LoThCh10, &AMACv2RegMap::HV2LoThCh11,
+      // 140 - HV2LoTh4
+      &AMACv2RegMap::HV2LoThCh12, &AMACv2RegMap::HV2LoThCh13, &AMACv2RegMap::HV2LoThCh14,
+      // 141 - HV2LoTh5
+      &AMACv2RegMap::HV2LoThCh15,
+      // 142 - HV2HiTh0
+      &AMACv2RegMap::HV2LoThCh0, &AMACv2RegMap::HV2LoThCh1, &AMACv2RegMap::HV2LoThCh2,
+      // 143 - HV2HiTh1
+      &AMACv2RegMap::HV2HiThCh3, &AMACv2RegMap::HV2HiThCh4, &AMACv2RegMap::HV2HiThCh5,
+      // 144 - HV2HiTh2
+      &AMACv2RegMap::HV2HiThCh6, &AMACv2RegMap::HV2HiThCh7, &AMACv2RegMap::HV2HiThCh8,
+      // 145 - HV2HiTh3
+      &AMACv2RegMap::HV2HiThCh9, &AMACv2RegMap::HV2HiThCh10, &AMACv2RegMap::HV2HiThCh11,
+      // 146 - HV2HiTh4
+      &AMACv2RegMap::HV2HiThCh12, &AMACv2RegMap::HV2HiThCh13, &AMACv2RegMap::HV2HiThCh14,
+      // 147 - HV2HiTh5
+      &AMACv2RegMap::HV2HiThCh15,
+      // 148 - DCDCLoTh0
+      &AMACv2RegMap::DCDCLoThCh0, &AMACv2RegMap::DCDCLoThCh1, &AMACv2RegMap::DCDCLoThCh2,
+      // 149 - DCDCLoTh1
+      &AMACv2RegMap::DCDCLoThCh3, &AMACv2RegMap::DCDCLoThCh4, &AMACv2RegMap::DCDCLoThCh5,
+      // 150 - DCDCLoTh2
+      &AMACv2RegMap::DCDCLoThCh6, &AMACv2RegMap::DCDCLoThCh7, &AMACv2RegMap::DCDCLoThCh8,
+      // 151 - DCDCLoTh3
+      &AMACv2RegMap::DCDCLoThCh9, &AMACv2RegMap::DCDCLoThCh10, &AMACv2RegMap::DCDCLoThCh11,
+      // 152 - DCDCLoTh4
+      &AMACv2RegMap::DCDCLoThCh12, &AMACv2RegMap::DCDCLoThCh13, &AMACv2RegMap::DCDCLoThCh14,
+      // 153 - DCDCLoTh5
+      &AMACv2RegMap::DCDCLoThCh15,
+      // 154 - DCDCHiTh0
+      &AMACv2RegMap::DCDCLoThCh0, &AMACv2RegMap::DCDCLoThCh1, &AMACv2RegMap::DCDCLoThCh2,
+      // 155 - DCDCHiTh1
+      &AMACv2RegMap::DCDCHiThCh3, &AMACv2RegMap::DCDCHiThCh4, &AMACv2RegMap::DCDCHiThCh5,
+      // 156 - DCDCHiTh2
+      &AMACv2RegMap::DCDCHiThCh6, &AMACv2RegMap::DCDCHiThCh7, &AMACv2RegMap::DCDCHiThCh8,
+      // 157 - DCDCHiTh3
+      &AMACv2RegMap::DCDCHiThCh9, &AMACv2RegMap::DCDCHiThCh10, &AMACv2RegMap::DCDCHiThCh11,
+      // 158 - DCDCHiTh4
+      &AMACv2RegMap::DCDCHiThCh12, &AMACv2RegMap::DCDCHiThCh13, &AMACv2RegMap::DCDCHiThCh14,
+      // 159 - DCDCHiTh5
+      &AMACv2RegMap::DCDCHiThCh15,
+      // 160 - WRNLoTh0
+      &AMACv2RegMap::WRNLoThCh0, &AMACv2RegMap::WRNLoThCh1, &AMACv2RegMap::WRNLoThCh2,
+      // 161 - WRNLoTh1
+      &AMACv2RegMap::WRNLoThCh3, &AMACv2RegMap::WRNLoThCh4, &AMACv2RegMap::WRNLoThCh5,
+      // 162 - WRNLoTh2
+      &AMACv2RegMap::WRNLoThCh6, &AMACv2RegMap::WRNLoThCh7, &AMACv2RegMap::WRNLoThCh8,
+      // 163 - WRNLoTh3
+      &AMACv2RegMap::WRNLoThCh9, &AMACv2RegMap::WRNLoThCh10, &AMACv2RegMap::WRNLoThCh11,
+      // 164 - WRNLoTh4
+      &AMACv2RegMap::WRNLoThCh12, &AMACv2RegMap::WRNLoThCh13, &AMACv2RegMap::WRNLoThCh14,
+      // 165 - WRNLoTh5
+      &AMACv2RegMap::WRNLoThCh15,
+      // 166 - WRNHiTh0
+      &AMACv2RegMap::WRNHiThCh0, &AMACv2RegMap::WRNHiThCh1, &AMACv2RegMap::WRNHiThCh2,
+      // 167 - WRNHiTh1
+      &AMACv2RegMap::WRNHiThCh3, &AMACv2RegMap::WRNHiThCh4, &AMACv2RegMap::WRNHiThCh5,
+      // 168 - WRNHiTh2
+      &AMACv2RegMap::WRNHiThCh6, &AMACv2RegMap::WRNHiThCh7, &AMACv2RegMap::WRNHiThCh8,
+      // 169 - WRNHiTh3
+      &AMACv2RegMap::WRNHiThCh9, &AMACv2RegMap::WRNHiThCh10, &AMACv2RegMap::WRNHiThCh11,
+      // 170 - WRNHiTh4
+      &AMACv2RegMap::WRNHiThCh12, &AMACv2RegMap::WRNHiThCh13, &AMACv2RegMap::WRNHiThCh14,
+      // 171 - WRNHiTh5
+      &AMACv2RegMap::WRNHiThCh15
+    };
+
+    for(AMACv2Field AMACv2RegMap::* field : m_fields)
+      m_fieldMap[(this->*field).getName()]=field;
+}
+
+std::vector<const AMACv2Register*> AMACv2RegMap::getRegisters() const
+{
+  std::vector<const AMACv2Register*> registers(m_registers.size(), nullptr);
+  std::transform(m_registers.cbegin(), m_registers.cend(),
+		 registers.begin(),
+		 [this](AMACv2Register AMACv2RegMap::* reg)
+		 { return (&(this->*reg)); });
+  return registers;
 }
 
 std::vector<const AMACv2Field*> AMACv2RegMap::getFields() const
 {
   std::vector<const AMACv2Field*> fields;
   fields.reserve(m_fieldMap.size());
-  for(const auto kv : m_fieldMap) fields.push_back(&(this->*kv.second));
+  for(AMACv2Field AMACv2RegMap::* field : m_fields) fields.push_back(&(this->*field));
   return fields;
 }
 
@@ -769,24 +384,12 @@ uint32_t AMACv2RegMap::getField(const std::string& fieldName)
 
 uint32_t AMACv2RegMap::getReg(uint32_t reg)
 {
-  if(reg<numRegs)
-    return m_cfg[reg];
-  else
-    return 0;
-}
-
-uint32_t AMACv2RegMap::getReg(AMACv2Field AMACv2RegMap::* ref)
-{
-  return (this->*ref).readRaw();
+  return (this->*m_regAddrMap[reg]).getValue();
 }
 
-uint32_t AMACv2RegMap::getReg(const std::string& fieldName)
+uint32_t AMACv2RegMap::getReg(AMACv2Register AMACv2RegMap::* ref)
 {
-  if(m_fieldMap.find(fieldName) != m_fieldMap.end())
-    return(this->*m_fieldMap[fieldName]).readRaw();
-  else
-    std::cerr << " --> Error: Could not find register \""<< fieldName << "\"" << std::endl;
-  return 0;
+  return (this->*ref).getValue();
 }
 
 void AMACv2RegMap::setField(AMACv2Field AMACv2RegMap::* ref, uint32_t value)
@@ -805,23 +408,23 @@ void AMACv2RegMap::setField(const std::string& fieldName, uint32_t value)
 
 void AMACv2RegMap::setReg(uint32_t reg, uint32_t value)
 {
-  m_cfg[reg]=value;
+  (this->*(m_regAddrMap[reg])).setValue(value);
 }
 
-void AMACv2RegMap::setReg(AMACv2Field AMACv2RegMap::* ref, uint32_t value)
+void AMACv2RegMap::setReg(AMACv2Register AMACv2RegMap::* ref, uint32_t value)
 {
-  (this->*ref).writeRaw(value);
+  (this->*ref).setValue(value);
 }
 
 uint8_t AMACv2RegMap::getAddr(AMACv2Field AMACv2RegMap::* ref)
 {
-  return (this->*ref).addr();
+  return (this->*ref).getRegister()->getAddress();
 }
 
 uint8_t AMACv2RegMap::getAddr(const std::string& fieldName)
 {
   if(m_fieldMap.find(fieldName) != m_fieldMap.end())
-    return (this->*m_fieldMap[fieldName]).addr();
+    return (this->*m_fieldMap[fieldName]).getRegister()->getAddress();
   else
     std::cerr << " --> Error: Could not find register \""<< fieldName << "\"" << std::endl;
   return 0;
diff --git a/pbv3/AMACv2RegMap.h b/pbv3/AMACv2RegMap.h
index 7e7a0041..becf0b57 100644
--- a/pbv3/AMACv2RegMap.h
+++ b/pbv3/AMACv2RegMap.h
@@ -22,8 +22,8 @@ private:
 public:
   AMACv2RegMap();
 
-  std::vector<const AMACv2Register*> getRegisters() const;
-  std::vector<const AMACv2Field*   > getFields() const;
+  std::vector<const AMACv2Register *> getRegisters() const;
+  std::vector<const AMACv2Field    *> getFields() const;
 
   AMACv2Field* findField(AMACv2Field AMACv2RegMap::* ref);
   AMACv2Field* findField(const std::string& fieldName);
@@ -32,592 +32,756 @@ public:
   uint32_t getField(const std::string& fieldName);
 
   uint32_t getReg(uint32_t reg);
-  uint32_t getReg(AMACv2Field AMACv2RegMap::* ref);
-  uint32_t getReg(const std::string& fieldName);
+  uint32_t getReg(AMACv2Register AMACv2RegMap::* ref);
 
   void setField(AMACv2Field AMACv2RegMap::* ref, uint32_t value);
   void setField(const std::string& fieldName, uint32_t value);
 
   void setReg(uint32_t reg, uint32_t value);
-  void setReg(AMACv2Field AMACv2RegMap::* ref, uint32_t value);
+  void setReg(AMACv2Register AMACv2RegMap::* ref, uint32_t value);
 
   uint8_t getAddr(AMACv2Field AMACv2RegMap::* ref);
   uint8_t getAddr(const std::string& fieldName);
 
   bool canBeWritten(AMACv2Field AMACv2RegMap::* ref);
 
+  /** \name Registers
+   * @{ */
+  AMACv2Register RegisterStatus    ={"Status"    ,  0, RO};
+  AMACv2Register RegisterHxFlags   ={"HxFlags"   ,  1, RO};
+  AMACv2Register RegisterHyFlags   ={"HyFlags"   ,  2, RO};
+  AMACv2Register RegisterHV0Flags  ={"HV0Flags"  ,  3, RO};
+  AMACv2Register RegisterHV2Flags  ={"HV2Flags"  ,  4, RO};
+  AMACv2Register RegisterDCDCFlags ={"DCDCFlags" ,  5, RO};
+  AMACv2Register RegisterWRNHxFlags={"WRNHxFlags",  6, RO};
+  AMACv2Register RegisterSynFlags  ={"SynFlags"  ,  7, RO};
+
+  AMACv2Register RegisterValue0={"Value0", 10, RO};
+  AMACv2Register RegisterValue1={"Value1", 11, RO};
+  AMACv2Register RegisterValue2={"Value2", 12, RO};
+  AMACv2Register RegisterValue3={"Value3", 13, RO};
+  AMACv2Register RegisterValue4={"Value4", 14, RO};
+  AMACv2Register RegisterValue5={"Value5", 15, RO};
+
+  AMACv2Register RegisterSerNum={"SerNum", 31, RO};
+
+  AMACv2Register RegisterFlagResets={"FlagResets", 32, WO};
+  AMACv2Register RegisterLogicReset={"LogicReset", 33, WO};
+  AMACv2Register RegisterHardReset ={"HardReset" , 34, WO};
+
+  AMACv2Register RegisterCntSet  ={"CntSet"  , 40, RW};
+  AMACv2Register RegisterCntSetC ={"CntSetC" , 41, RW};
+  AMACv2Register RegisterDCDCen  ={"DCDCen"  , 42, RW};
+  AMACv2Register RegisterDCDCenC ={"DCDCenC" , 43, RW};
+  AMACv2Register RegisterIlock   ={"Ilock"   , 44, RW};
+  AMACv2Register RegisterIlockC  ={"IlockC"  , 45, RW};
+  AMACv2Register RegisterRstCnt  ={"RstCnt"  , 46, RW};
+  AMACv2Register RegisterRstCntC ={"RstCntC" , 47, RW};
+  AMACv2Register RegisterAMen    ={"AMen"    , 48, RW};
+  AMACv2Register RegisterAMenC   ={"AMenC"   , 49, RW};
+  AMACv2Register RegisterAMpwr   ={"AMpwr"   , 50, RW};
+  AMACv2Register RegisterAMpwrC  ={"AMpwrC"  , 51, RW};
+  AMACv2Register RegisterBgCnt   ={"BgCnt"   , 52, RW};
+  AMACv2Register RegisterAMCnt   ={"AMCnt"   , 53, RW};
+  AMACv2Register RegisterDACs0   ={"DACs0"   , 54, RW};
+  AMACv2Register RegisterDACbias ={"DACbias" , 55, RW};
+  AMACv2Register RegisterAMACCnt ={"AMACCnt" , 56, RW};
+  AMACv2Register RegisterNTCRange={"NTCRange", 57, RW};
+  AMACv2Register RegisterLVCurCal={"LVCurCal", 58, RW};
+
+  AMACv2Register RegisterHxICfg  ={"HxICfg"  , 60, RW};
+  AMACv2Register RegisterHyICfg  ={"HyICfg"  , 61, RW};
+  AMACv2Register RegisterHV0ICfg ={"HV0ICfg" , 62, RW};
+  AMACv2Register RegisterHV2ICfg ={"HV2ICfg" , 63, RW};
+  AMACv2Register RegisterDCDCICfg={"DCDCICfg", 64, RW};
+  AMACv2Register RegisterWRNICfg ={"WRNICfg" , 65, RW};
+
+  AMACv2Register RegisterHxTLUT     ={"HxTLUT"     , 70, RW};
+  AMACv2Register RegisterHxModLUT1  ={"HxModLUT1"  , 71, RW};
+  AMACv2Register RegisterHxModLUT2  ={"HxModLUT2"  , 72, RW};
+  AMACv2Register RegisterHyTLUT     ={"HyTLUT"     , 73, RW};
+  AMACv2Register RegisterHyModLUT1  ={"HyModLUT1"  , 74, RW};
+  AMACv2Register RegisterHyModLUT2  ={"HyModLUT2"  , 75, RW};
+  AMACv2Register RegisterHV0TLUT    ={"HV0TLUT"    , 76, RW};
+  AMACv2Register RegisterHV0ModLUT1 ={"HV0ModLUT1" , 77, RW};
+  AMACv2Register RegisterHV0ModLUT2 ={"HV0ModLUT2" , 78, RW};
+  AMACv2Register RegisterHV2TLUT    ={"HV2TLUT"    , 79, RW};
+  AMACv2Register RegisterHV2ModLUT1 ={"HV2ModLUT1" , 80, RW};
+  AMACv2Register RegisterHV2ModLUT2 ={"HV2ModLUT2" , 81, RW};
+  AMACv2Register RegisterDCDCTLUT   ={"DCDCTLUT"   , 82, RW};
+  AMACv2Register RegisterDCDCModLUT1={"DCDCModLUT1", 83, RW};
+  AMACv2Register RegisterDCDCModLUT2={"DCDCModLUT2", 84, RW};
+  AMACv2Register RegisterWRNTLUT    ={"WRNTLUT"    , 85, RW};
+  AMACv2Register RegisterWRNModLUT1 ={"WRNModLUT1" , 86, RW};
+  AMACv2Register RegisterWRNModLUT2 ={"WRNModLUT2" , 87, RW};
+
+  AMACv2Register RegisterHxFlagEn  ={"HxFlagEn"  , 90, RW};
+  AMACv2Register RegisterHyFlagEn  ={"HyFlagEn"  , 91, RW};
+  AMACv2Register RegisterHV0FlagEn ={"HV0FlagEn" , 92, RW};
+  AMACv2Register RegisterHV2FlagEn ={"HV2FlagEn" , 93, RW};
+  AMACv2Register RegisterDCDCFlagEn={"DCDCFlagEn", 94, RW};
+  AMACv2Register RegisterSynFlagEn ={"SynFlagEn" , 95, RW};
+  //AMACv2Register RegisterWRNFlagEn={"", 95, RW};
+
+  AMACv2Register RegisterHxLoTh0  ={"HxLoTh0"  ,100, RW};
+  AMACv2Register RegisterHxLoTh1  ={"HxLoTh1"  ,101, RW};
+  AMACv2Register RegisterHxLoTh2  ={"HxLoTh2"  ,102, RW};
+  AMACv2Register RegisterHxLoTh3  ={"HxLoTh3"  ,103, RW};
+  AMACv2Register RegisterHxLoTh4  ={"HxLoTh4"  ,104, RW};
+  AMACv2Register RegisterHxLoTh5  ={"HxLoTh5"  ,105, RW};
+  AMACv2Register RegisterHxHiTh0  ={"HxHiTh0"  ,106, RW};
+  AMACv2Register RegisterHxHiTh1  ={"HxHiTh1"  ,107, RW};
+  AMACv2Register RegisterHxHiTh2  ={"HxHiTh2"  ,108, RW};
+  AMACv2Register RegisterHxHiTh3  ={"HxHiTh3"  ,109, RW};
+  AMACv2Register RegisterHxHiTh4  ={"HxHiTh4"  ,110, RW};
+  AMACv2Register RegisterHxHiTh5  ={"HxHiTh5"  ,111, RW};
+  AMACv2Register RegisterHyLoTh0  ={"HyLoTh0"  ,112, RW};
+  AMACv2Register RegisterHyLoTh1  ={"HyLoTh1"  ,113, RW};
+  AMACv2Register RegisterHyLoTh2  ={"HyLoTh2"  ,114, RW};
+  AMACv2Register RegisterHyLoTh3  ={"HyLoTh3"  ,115, RW};
+  AMACv2Register RegisterHyLoTh4  ={"HyLoTh4"  ,116, RW};
+  AMACv2Register RegisterHyLoTh5  ={"HyLoTh5"  ,117, RW};
+  AMACv2Register RegisterHyHiTh0  ={"HyHiTh0"  ,118, RW};
+  AMACv2Register RegisterHyHiTh1  ={"HyHiTh1"  ,119, RW};
+  AMACv2Register RegisterHyHiTh2  ={"HyHiTh2"  ,120, RW};
+  AMACv2Register RegisterHyHiTh3  ={"HyHiTh3"  ,121, RW};
+  AMACv2Register RegisterHyHiTh4  ={"HyHiTh4"  ,122, RW};
+  AMACv2Register RegisterHyHiTh5  ={"HyHiTh5"  ,123, RW};
+  AMACv2Register RegisterHV0LoTh0 ={"HV0LoTh0" ,124, RW};
+  AMACv2Register RegisterHV0LoTh1 ={"HV0LoTh1" ,125, RW};
+  AMACv2Register RegisterHV0LoTh2 ={"HV0LoTh2" ,126, RW};
+  AMACv2Register RegisterHV0LoTh3 ={"HV0LoTh3" ,127, RW};
+  AMACv2Register RegisterHV0LoTh4 ={"HV0LoTh4" ,128, RW};
+  AMACv2Register RegisterHV0LoTh5 ={"HV0LoTh5" ,129, RW};
+  AMACv2Register RegisterHV0HiTh0 ={"HV0HiTh0" ,130, RW};
+  AMACv2Register RegisterHV0HiTh1 ={"HV0HiTh1" ,131, RW};
+  AMACv2Register RegisterHV0HiTh2 ={"HV0HiTh2" ,132, RW};
+  AMACv2Register RegisterHV0HiTh3 ={"HV0HiTh3" ,133, RW};
+  AMACv2Register RegisterHV0HiTh4 ={"HV0HiTh4" ,134, RW};
+  AMACv2Register RegisterHV0HiTh5 ={"HV0HiTh5" ,135, RW};
+  AMACv2Register RegisterHV2LoTh0 ={"HV2LoTh0" ,136, RW};
+  AMACv2Register RegisterHV2LoTh1 ={"HV2LoTh1" ,137, RW};
+  AMACv2Register RegisterHV2LoTh2 ={"HV2LoTh2" ,138, RW};
+  AMACv2Register RegisterHV2LoTh3 ={"HV2LoTh3" ,139, RW};
+  AMACv2Register RegisterHV2LoTh4 ={"HV2LoTh4" ,140, RW};
+  AMACv2Register RegisterHV2LoTh5 ={"HV2LoTh5" ,141, RW};
+  AMACv2Register RegisterHV2HiTh0 ={"HV2HiTh0" ,142, RW};
+  AMACv2Register RegisterHV2HiTh1 ={"HV2HiTh1" ,143, RW};
+  AMACv2Register RegisterHV2HiTh2 ={"HV2HiTh2" ,144, RW};
+  AMACv2Register RegisterHV2HiTh3 ={"HV2HiTh3" ,145, RW};
+  AMACv2Register RegisterHV2HiTh4 ={"HV2HiTh4" ,146, RW};
+  AMACv2Register RegisterHV2HiTh5 ={"HV2HiTh5" ,147, RW};
+  AMACv2Register RegisterDCDCLoTh0={"DCDCLoTh0",148, RW};
+  AMACv2Register RegisterDCDCLoTh1={"DCDCLoTh1",149, RW};
+  AMACv2Register RegisterDCDCLoTh2={"DCDCLoTh2",150, RW};
+  AMACv2Register RegisterDCDCLoTh3={"DCDCLoTh3",151, RW};
+  AMACv2Register RegisterDCDCLoTh4={"DCDCLoTh4",152, RW};
+  AMACv2Register RegisterDCDCLoTh5={"DCDCLoTh5",153, RW};
+  AMACv2Register RegisterDCDCHiTh0={"DCDCHiTh0",154, RW};
+  AMACv2Register RegisterDCDCHiTh1={"DCDCHiTh1",155, RW};
+  AMACv2Register RegisterDCDCHiTh2={"DCDCHiTh2",156, RW};
+  AMACv2Register RegisterDCDCHiTh3={"DCDCHiTh3",157, RW};
+  AMACv2Register RegisterDCDCHiTh4={"DCDCHiTh4",158, RW};
+  AMACv2Register RegisterDCDCHiTh5={"DCDCHiTh5",159, RW};
+  AMACv2Register RegisterWRNLoTh0 ={"WRNLoTh0" ,160, RW};
+  AMACv2Register RegisterWRNLoTh1 ={"WRNLoTh1" ,161, RW};
+  AMACv2Register RegisterWRNLoTh2 ={"WRNLoTh2" ,162, RW};
+  AMACv2Register RegisterWRNLoTh3 ={"WRNLoTh3" ,163, RW};
+  AMACv2Register RegisterWRNLoTh4 ={"WRNLoTh4" ,164, RW};
+  AMACv2Register RegisterWRNLoTh5 ={"WRNLoTh5" ,165, RW};
+  AMACv2Register RegisterWRNHiTh0 ={"WRNHiTh0" ,166, RW};
+  AMACv2Register RegisterWRNHiTh1 ={"WRNHiTh1" ,167, RW};
+  AMACv2Register RegisterWRNHiTh2 ={"WRNHiTh2" ,168, RW};
+  AMACv2Register RegisterWRNHiTh3 ={"WRNHiTh3" ,169, RW};
+  AMACv2Register RegisterWRNHiTh4 ={"WRNHiTh4" ,170, RW};
+  AMACv2Register RegisterWRNHiTh5 ={"WRNHiTh5" ,171, RW};
+
+  /** @} */
+  
+  /** \name Fields
+   * @{ */
   // 0 - Status register
-  AMACv2Field StatusAM;
-  AMACv2Field StatusWARN;
-  AMACv2Field StatusDCDC;
-  AMACv2Field StatusHV3;
-  AMACv2Field StatusHV2;
-  AMACv2Field StatusHV1;
-  AMACv2Field StatusHV0;
-  AMACv2Field StatusY2LDO;
-  AMACv2Field StatusY1LDO;
-  AMACv2Field StatusY0LDO;
-  AMACv2Field StatusX2LDO;
-  AMACv2Field StatusX1LDO;
-  AMACv2Field StatusX0LDO;
-  AMACv2Field StatusGPI;
-  AMACv2Field StatusPGOOD;
-  AMACv2Field StatusILockWARN;
-  AMACv2Field StatusILockDCDC;
-  AMACv2Field StatusILockHV2;
-  AMACv2Field StatusILockHV0;
-  AMACv2Field StatusILockYLDO;
-  AMACv2Field StatusILockxLDO;
+  AMACv2Field StatusAM       ={"StatusAM"       , &RegisterStatus, 31, 1, 0};
+  AMACv2Field StatusWARN     ={"StatusWARN"     , &RegisterStatus, 29, 1, 0};
+  AMACv2Field StatusDCDC     ={"StatusDCDC"     , &RegisterStatus, 28, 1, 0};
+  AMACv2Field StatusHV3      ={"StatusHV3"      , &RegisterStatus, 27, 1, 0};
+  AMACv2Field StatusHV2      ={"StatusHV2"      , &RegisterStatus, 26, 1, 0};
+  AMACv2Field StatusHV1      ={"StatusHV1"      , &RegisterStatus, 25, 1, 0};
+  AMACv2Field StatusHV0      ={"StatusHV0"      , &RegisterStatus, 24, 1, 0};
+  AMACv2Field StatusY2LDO    ={"StatusY2LDO"    , &RegisterStatus, 22, 1, 0};
+  AMACv2Field StatusY1LDO    ={"StatusY1LDO"    , &RegisterStatus, 21, 1, 0};
+  AMACv2Field StatusY0LDO    ={"StatusY0LDO"    , &RegisterStatus, 20, 1, 0};
+  AMACv2Field StatusX2LDO    ={"StatusX2LDO"    , &RegisterStatus, 18, 1, 0};
+  AMACv2Field StatusX1LDO    ={"StatusX1LDO"    , &RegisterStatus, 17, 1, 0};
+  AMACv2Field StatusX0LDO    ={"StatusX0LDO"    , &RegisterStatus, 16, 1, 0};
+  AMACv2Field StatusGPI      ={"StatusGPI"      , &RegisterStatus, 12, 1, 0};
+  AMACv2Field StatusPGOOD    ={"StatusPGOOD"    , &RegisterStatus,  8, 1, 0};
+  AMACv2Field StatusILockWARN={"StatusILockWARN", &RegisterStatus,  5, 1, 0};
+  AMACv2Field StatusILockDCDC={"StatusILockDCDC", &RegisterStatus,  4, 1, 0};
+  AMACv2Field StatusILockHV2 ={"StatusILockHV2" , &RegisterStatus,  3, 1, 0};
+  AMACv2Field StatusILockHV0 ={"StatusILockHV2" , &RegisterStatus,  2, 1, 0};
+  AMACv2Field StatusILockYLDO={"StatusILockYLDO", &RegisterStatus,  1, 1, 0};
+  AMACv2Field StatusILockxLDO={"StatusILockxLDO", &RegisterStatus,  0, 1, 0};
   // 1 - HxFlags
-  AMACv2Field HxFlagsHi;
-  AMACv2Field HxFlagsLo;
+  AMACv2Field HxFlagsHi ={"HxFlagsHi", &RegisterHxFlags, 16, 16, 0x0};
+  AMACv2Field HxFlagsLo ={"HxFlagsLo", &RegisterHxFlags,  0, 16, 0x0};
   // 2 - HyFlags
-  AMACv2Field HyFlagsHi;
-  AMACv2Field HyFlagsLo;
+  AMACv2Field HyFlagsHi ={"HyFlagsHi", &RegisterHyFlags, 16, 16, 0x0};
+  AMACv2Field HyFlagsLo ={"HyFlagsLo", &RegisterHyFlags, 0, 16, 0x0};
   // 3 - HV0Flags
-  AMACv2Field HV0FlagsHi;
-  AMACv2Field HV0FlagsLo;
+  AMACv2Field HV0FlagsHi ={"HV0FlagsHi", &RegisterHV0Flags, 16, 16, 0x0};
+  AMACv2Field HV0FlagsLo ={"HV0FlagsLo", &RegisterHV0Flags, 0, 16, 0x0};
   // 4 - HV2Flags
-  AMACv2Field HV2FlagsHi;
-  AMACv2Field HV2FlagsLo;
-  // 5 - DCDCflags
-  AMACv2Field DCDCflagsHi;
-  AMACv2Field DCDCflagsLo;
-  // 6 - WRNflags
-  AMACv2Field WRNflagsHi;
-  AMACv2Field WRNflagsLo;
+  AMACv2Field HV2FlagsHi ={"HV2FlagsHi", &RegisterHV2Flags, 16, 16, 0x0};
+  AMACv2Field HV2FlagsLo ={"HV2FlagsLo", &RegisterHV2Flags, 0, 16, 0x0};
+  // 5 - DCDCFlags
+  AMACv2Field DCDCflagsHi ={"DCDCflagsHi", &RegisterDCDCFlags, 16, 16, 0x0};
+  AMACv2Field DCDCflagsLo ={"DCDCflagsLo", &RegisterDCDCFlags, 0, 16, 0x0};
+  // 6 - WRNHxFlags
+  AMACv2Field WRNflagsHi ={"WRNflagsHi", &RegisterWRNHxFlags, 16, 16, 0x0};
+  AMACv2Field WRNflagsLo ={"WRNflagsLo", &RegisterWRNHxFlags, 0, 16, 0x0};
   // 7 - SynFlags
-  AMACv2Field SynFlagsWRN;
-  AMACv2Field SynFlagsDCDC;
-  AMACv2Field SynFlagsHV2;
-  AMACv2Field SynFlagsHV0;
-  AMACv2Field SynFlagsHy;
-  AMACv2Field SynFlagsHx;
+  AMACv2Field SynFlagsHx  ={"SynFlagsHx"  , &RegisterSynFlags,  0, 2, 0x0};
+  AMACv2Field SynFlagsHy  ={"SynFlagsHy"  , &RegisterSynFlags,  4, 2, 0x0};
+  AMACv2Field SynFlagsHV0 ={"SynFlagsHV0" , &RegisterSynFlags,  8, 2, 0x0};
+  AMACv2Field SynFlagsHV2 ={"SynFlagsHV2" , &RegisterSynFlags, 12, 2, 0x0};
+  AMACv2Field SynFlagsDCDC={"SynFlagsDCDC", &RegisterSynFlags, 16, 2, 0x0};
+  AMACv2Field SynFlagsWRN ={"SynFlagsWRN" , &RegisterSynFlags, 20, 2, 0x0};
   // 10 - Value0
-  AMACv2Field Value0AMen;
-  AMACv2Field Ch0Value;
-  AMACv2Field Ch1Value;
-  AMACv2Field Ch2Value;
+  AMACv2Field Value0AMen ={"Value0AMen", &RegisterValue0, 31, 1, 0x0};
+  AMACv2Field Ch0Value ={"Ch0Value", &RegisterValue0, 0, 10, 0x0};
+  AMACv2Field Ch1Value ={"Ch1Value", &RegisterValue0, 10, 10, 0x0};
+  AMACv2Field Ch2Value ={"Ch2Value", &RegisterValue0, 20, 10, 0x0};
   // 11 - Value1
-  AMACv2Field Value1AMen;
-  AMACv2Field Ch3Value;
-  AMACv2Field Ch4Value;
-  AMACv2Field Ch5Value;
+  AMACv2Field Value1AMen ={"Value1AMen", &RegisterValue1, 31, 1, 0x0};
+  AMACv2Field Ch3Value ={"Ch3Value", &RegisterValue1, 0, 10, 0x0};
+  AMACv2Field Ch4Value ={"Ch4Value", &RegisterValue1, 10, 10, 0x0};
+  AMACv2Field Ch5Value ={"Ch5Value", &RegisterValue1, 20, 10, 0x0};
   // 12 - Value2
-  AMACv2Field Value2AMen;
-  AMACv2Field Ch6Value;
-  AMACv2Field Ch7Value;
-  AMACv2Field Ch8Value;
+  AMACv2Field Value2AMen ={"Value2AMen", &RegisterValue2, 31, 1, 0x0};
+  AMACv2Field Ch6Value ={"Ch6Value", &RegisterValue2, 0, 10, 0x0};
+  AMACv2Field Ch7Value ={"Ch7Value", &RegisterValue2, 10, 10, 0x0};
+  AMACv2Field Ch8Value ={"Ch8Value", &RegisterValue2, 20, 10, 0x0};
   // 13 - Value3
-  AMACv2Field Value3AMen;
-  AMACv2Field Ch9Value;
-  AMACv2Field Ch10Value;
-  AMACv2Field Ch11Value;
+  AMACv2Field Value3AMen ={"Value3AMen", &RegisterValue3, 31, 1, 0x0};
+  AMACv2Field Ch9Value ={"Ch9Value", &RegisterValue3, 0, 10, 0x0};
+  AMACv2Field Ch10Value ={"Ch10Value", &RegisterValue3, 10, 10, 0x0};
+  AMACv2Field Ch11Value ={"Ch11Value", &RegisterValue3, 20, 10, 0x0};
   // 14 - Value4
-  AMACv2Field Value4AMen;
-  AMACv2Field Ch12Value;
-  AMACv2Field Ch13Value;
-  AMACv2Field Ch14Value;
+  AMACv2Field Value4AMen ={"Value4AMen", &RegisterValue4, 31, 1, 0x0};
+  AMACv2Field Ch12Value ={"Ch12Value", &RegisterValue4, 0, 10, 0x0};
+  AMACv2Field Ch13Value ={"Ch13Value", &RegisterValue4, 10, 10, 0x0};
+  AMACv2Field Ch14Value ={"Ch14Value", &RegisterValue4, 20, 10, 0x0};
   // 15 - Value5
-  AMACv2Field Value5AMen;
-  AMACv2Field Ch15Value;
+  AMACv2Field Value5AMen ={"Value5AMen", &RegisterValue5, 31, 1, 0x0};
+  AMACv2Field Ch15Value ={"Ch15Value", &RegisterValue5, 0, 10, 0x0};
   // 31 - SerNum
-  AMACv2Field PadID;
-  AMACv2Field SerNum;
+  AMACv2Field PadID ={"PadID", &RegisterSerNum, 24, 5, 0x0};
+  AMACv2Field SerNum ={"SerNum", &RegisterSerNum, 0, 16, 0x0};
   // 32 - FlagResets
-  AMACv2Field FlagResetWRN;
-  AMACv2Field FlagResetDCDC;
-  AMACv2Field FlagResetHV2;
-  AMACv2Field FlagResetHV0;
-  AMACv2Field FlagResetXLDO;
-  AMACv2Field FlagResetYLDO;
+  AMACv2Field FlagResetWRN ={"FlagResetWRN", &RegisterFlagResets, 5, 1, 0x0};
+  AMACv2Field FlagResetDCDC ={"FlagResetDCDC", &RegisterFlagResets, 4, 1, 0x0};
+  AMACv2Field FlagResetHV2 ={"FlagResetHV2", &RegisterFlagResets, 3, 1, 0x0};
+  AMACv2Field FlagResetHV0 ={"FlagResetHV0", &RegisterFlagResets, 2, 1, 0x0};
+  AMACv2Field FlagResetXLDO ={"FlagResetXLDO", &RegisterFlagResets, 1, 1, 0x0};
+  AMACv2Field FlagResetYLDO ={"FlagResetYLDO", &RegisterFlagResets, 0, 1, 0x0};
   // 33 - LogicReset
-  AMACv2Field LogicReset;
+  AMACv2Field LogicReset ={"LogicReset", &RegisterLogicReset, 0, 32, 0x0};
   // 34 - HardReset
-  AMACv2Field HardReset;
+  AMACv2Field HardReset ={"HardReset", &RegisterHardReset, 0, 32, 0x0};
   // 40 - CntSet
-  AMACv2Field CntSetHV3frq;
-  AMACv2Field CntSetHV3en;
-  AMACv2Field CntSetHV2frq;
-  AMACv2Field CntSetHV2en;
-  AMACv2Field CntSetHV1frq;
-  AMACv2Field CntSetHV1en;
-  AMACv2Field CntSetHV0frq;
-  AMACv2Field CntSetHV0en;
-  AMACv2Field CntSetHyLDO2en;
-  AMACv2Field CntSetHyLDO1en;
-  AMACv2Field CntSetHyLDO0en;
-  AMACv2Field CntSetHxLDO2en;
-  AMACv2Field CntSetHxLDO1en;
-  AMACv2Field CntSetHxLDO0en;
-  AMACv2Field CntSetWARN;
+  AMACv2Field CntSetHV3frq ={"CntSetHV3frq", &RegisterCntSet, 29, 2, 0x3};
+  AMACv2Field CntSetHV3en ={"CntSetHV3en", &RegisterCntSet, 28, 1, 0x0};
+  AMACv2Field CntSetHV2frq ={"CntSetHV2frq", &RegisterCntSet, 25, 2, 0x3};
+  AMACv2Field CntSetHV2en ={"CntSetHV2en", &RegisterCntSet, 24, 1, 0x0};
+  AMACv2Field CntSetHV1frq ={"CntSetHV1frq", &RegisterCntSet, 21, 2, 0x3};
+  AMACv2Field CntSetHV1en ={"CntSetHV1en", &RegisterCntSet, 20, 1, 0x0};
+  AMACv2Field CntSetHV0frq ={"CntSetHV0frq", &RegisterCntSet, 17, 2, 0x3};
+  AMACv2Field CntSetHV0en ={"CntSetHV0en", &RegisterCntSet, 16, 1, 0x0};
+  AMACv2Field CntSetHyLDO2en ={"CntSetHyLDO2en", &RegisterCntSet, 14, 1, 0x0};
+  AMACv2Field CntSetHyLDO1en ={"CntSetHyLDO1en", &RegisterCntSet, 13, 1, 0x0};
+  AMACv2Field CntSetHyLDO0en ={"CntSetHyLDO0en", &RegisterCntSet, 12, 1, 0x0};
+  AMACv2Field CntSetHxLDO2en ={"CntSetHxLDO2en", &RegisterCntSet, 10, 1, 0x0};
+  AMACv2Field CntSetHxLDO1en ={"CntSetHxLDO1en", &RegisterCntSet, 9, 1, 0x0};
+  AMACv2Field CntSetHxLDO0en ={"CntSetHxLDO0en", &RegisterCntSet, 8, 1, 0x0};
+  AMACv2Field CntSetWARN ={"CntSetWARN", &RegisterCntSet, 4, 1, 0x0};
   // 41 - CntSetC
-  AMACv2Field CntSetCHV3frq;
-  AMACv2Field CntSetCHV3en;
-  AMACv2Field CntSetCHV2frq;
-  AMACv2Field CntSetCHV2en;
-  AMACv2Field CntSetCHV1frq;
-  AMACv2Field CntSetCHV1en;
-  AMACv2Field CntSetCHV0frq;
-  AMACv2Field CntSetCHV0en;
-  AMACv2Field CntSetCHyLDO2en;
-  AMACv2Field CntSetCHyLDO1en;
-  AMACv2Field CntSetCHyLDO0en;
-  AMACv2Field CntSetCHxLDO2en;
-  AMACv2Field CntSetCHxLDO1en;
-  AMACv2Field CntSetCHxLDO0en;
-  AMACv2Field CntSetCWARN;
+  AMACv2Field CntSetCHV3frq ={"CntSetCHV3frq", &RegisterCntSetC, 29, 2, 0x3};
+  AMACv2Field CntSetCHV3en ={"CntSetCHV3en", &RegisterCntSetC, 28, 1, 0x0};
+  AMACv2Field CntSetCHV2frq ={"CntSetCHV2frq", &RegisterCntSetC, 25, 2, 0x3};
+  AMACv2Field CntSetCHV2en ={"CntSetCHV2en", &RegisterCntSetC, 24, 1, 0x0};
+  AMACv2Field CntSetCHV1frq ={"CntSetCHV1frq", &RegisterCntSetC, 21, 2, 0x3};
+  AMACv2Field CntSetCHV1en ={"CntSetCHV1en", &RegisterCntSetC, 20, 1, 0x0};
+  AMACv2Field CntSetCHV0frq ={"CntSetCHV0frq", &RegisterCntSetC, 17, 2, 0x3};
+  AMACv2Field CntSetCHV0en ={"CntSetCHV0en", &RegisterCntSetC, 16, 1, 0x0};
+  AMACv2Field CntSetCHyLDO2en ={"CntSetCHyLDO2en", &RegisterCntSetC, 14, 1, 0x0};
+  AMACv2Field CntSetCHyLDO1en ={"CntSetCHyLDO1en", &RegisterCntSetC, 13, 1, 0x0};
+  AMACv2Field CntSetCHyLDO0en ={"CntSetCHyLDO0en", &RegisterCntSetC, 12, 1, 0x0};
+  AMACv2Field CntSetCHxLDO2en ={"CntSetCHxLDO2en", &RegisterCntSetC, 10, 1, 0x0};
+  AMACv2Field CntSetCHxLDO1en ={"CntSetCHxLDO1en", &RegisterCntSetC, 9, 1, 0x0};
+  AMACv2Field CntSetCHxLDO0en ={"CntSetCHxLDO0en", &RegisterCntSetC, 8, 1, 0x0};
+  AMACv2Field CntSetCWARN ={"CntSetCWARN", &RegisterCntSetC, 4, 1, 0x0};
   // 42 - DCDCen
-  AMACv2Field DCDCAdj;
-  AMACv2Field DCDCen;
+  AMACv2Field DCDCAdj ={"DCDCAdj", &RegisterDCDCen, 4, 2, 0x0};
+  AMACv2Field DCDCen ={"DCDCen", &RegisterDCDCen, 0, 1, 0x0};
   // 43 - DCDCenC
-  AMACv2Field DCDCAdjC;
-  AMACv2Field DCDCenC;
+  AMACv2Field DCDCAdjC ={"DCDCAdjC", &RegisterDCDCenC, 4, 2, 0x0};
+  AMACv2Field DCDCenC ={"DCDCenC", &RegisterDCDCenC, 0, 1, 0x0};
   // 44 - Ilock
-  AMACv2Field IlockWRN;
-  AMACv2Field IlockDCDC;
-  AMACv2Field IlockHV2;
-  AMACv2Field IlockHV0;
-  AMACv2Field IlockHy;
-  AMACv2Field IlockHx;
+  AMACv2Field IlockHx  ={"IlockHx"  , &RegisterIlock, 0, 1, 0x0};
+  AMACv2Field IlockHy  ={"IlockHy"  , &RegisterIlock, 1, 1, 0x0};
+  AMACv2Field IlockHV0 ={"IlockHV0" , &RegisterIlock, 2, 1, 0x0};
+  AMACv2Field IlockHV2 ={"IlockHV2" , &RegisterIlock, 3, 1, 0x0};
+  AMACv2Field IlockDCDC={"IlockDCDC", &RegisterIlock, 4, 1, 0x0};
+  AMACv2Field IlockWRN ={"IlockWRN" , &RegisterIlock, 5, 1, 0x0};
   // 45 - IlockC
-  AMACv2Field IlockCWRN;
-  AMACv2Field IlockCDCDC;
-  AMACv2Field IlockCHV2;
-  AMACv2Field IlockCHV0;
-  AMACv2Field IlockCHy;
-  AMACv2Field IlockCHx;
+  AMACv2Field IlockCHx  ={"IlockCHx"  , &RegisterIlockC, 0, 1, 0x0};
+  AMACv2Field IlockCHy  ={"IlockCHy"  , &RegisterIlockC, 1, 1, 0x0};
+  AMACv2Field IlockCHV0 ={"IlockCHV0" , &RegisterIlockC, 2, 1, 0x0};
+  AMACv2Field IlockCHV2 ={"IlockCHV2" , &RegisterIlockC, 3, 1, 0x0};
+  AMACv2Field IlockCDCDC={"IlockCDCDC", &RegisterIlockC, 4, 1, 0x0};
+  AMACv2Field IlockCWRN ={"IlockCWRN" , &RegisterIlockC, 5, 1, 0x0};
   // 46 - RstCnt
-  AMACv2Field RstCntHyHCCresetB;
-  AMACv2Field RstCntHxHCCresetB;
-  AMACv2Field RstCntOF;
+  AMACv2Field RstCntHyHCCresetB ={"RstCntHyHCCresetB", &RegisterRstCnt, 16, 1, 0x0};
+  AMACv2Field RstCntHxHCCresetB ={"RstCntHxHCCresetB", &RegisterRstCnt, 8, 1, 0x0};
+  AMACv2Field RstCntOF ={"RstCntOF", &RegisterRstCnt, 0, 1, 0x0};
   // 47 - RstCntC
-  AMACv2Field RstCntCHyHCCresetB;
-  AMACv2Field RstCntCHxHCCresetB;
-  AMACv2Field RstCntCOF;
+  AMACv2Field RstCntCHyHCCresetB ={"RstCntCHyHCCresetB", &RegisterRstCntC, 16, 1, 0x0};
+  AMACv2Field RstCntCHxHCCresetB ={"RstCntCHxHCCresetB", &RegisterRstCntC, 8, 1, 0x0};
+  AMACv2Field RstCntCOF ={"RstCntCOF", &RegisterRstCntC, 0, 1, 0x0};
   // 48 - AMen
-  AMACv2Field AMzeroCalib;
-  AMACv2Field AMen;
+  AMACv2Field AMzeroCalib ={"AMzeroCalib", &RegisterAMen, 8, 1, 0x0};
+  AMACv2Field AMen ={"AMen", &RegisterAMen, 0, 1, 0x1};
   // 49 - AMenC
-  AMACv2Field AMzeroCalibC;
-  AMACv2Field AMenC;
+  AMACv2Field AMzeroCalibC ={"AMzeroCalibC", &RegisterAMenC, 8, 1, 0x0};
+  AMACv2Field AMenC ={"AMenC", &RegisterAMenC, 0, 1, 0x1};
   // 50 - AMpwr
-  AMACv2Field ReqDCDCPGOOD;
-  AMACv2Field DCDCenToPwrAMAC;
+  AMACv2Field ReqDCDCPGOOD ={"ReqDCDCPGOOD", &RegisterAMpwr, 8, 1, 0x1};
+  AMACv2Field DCDCenToPwrAMAC ={"DCDCenToPwrAMAC", &RegisterAMpwr, 0, 1, 0x0};
   // 51 - AMpwrC
-  AMACv2Field ReqDCDCPGOODC;
-  AMACv2Field DCDCenToPwrAMACC;
+  AMACv2Field ReqDCDCPGOODC ={"ReqDCDCPGOODC", &RegisterAMpwrC, 8, 1, 0x1};
+  AMACv2Field DCDCenToPwrAMACC ={"DCDCenToPwrAMACC", &RegisterAMpwrC, 0, 1, 0x0};
   // 52 - BgCnt
-  AMACv2Field AMbgen;
-  AMACv2Field AMbg;
-  AMACv2Field VDDbgen;
-  AMACv2Field VDDbg;
-  // 53 - AMcnt
-  AMACv2Field AMintCalib;
-  AMACv2Field Ch13Mux;
-  AMACv2Field Ch12Mux;
-  AMACv2Field Ch5Mux;
-  AMACv2Field Ch4Mux;
-  AMACv2Field Ch3Mux;
+  AMACv2Field AMbgen ={"AMbgen", &RegisterBgCnt, 15, 1, 0x0};
+  AMACv2Field AMbg ={"AMbg", &RegisterBgCnt, 8, 5, 0x0};
+  AMACv2Field VDDbgen ={"VDDbgen", &RegisterBgCnt, 7, 1, 0x0};
+  AMACv2Field VDDbg ={"VDDbg", &RegisterBgCnt, 0, 5, 0x0};
+  // 53 - AMCnt
+  AMACv2Field AMintCalib ={"AMintCalib", &RegisterAMCnt, 24, 4, 0x0};
+  AMACv2Field Ch13Mux ={"Ch13Mux", &RegisterAMCnt, 20, 2, 0x0};
+  AMACv2Field Ch12Mux ={"Ch12Mux", &RegisterAMCnt, 16, 2, 0x0};
+  AMACv2Field Ch5Mux ={"Ch5Mux", &RegisterAMCnt, 13, 2, 0x0};
+  AMACv2Field Ch4Mux ={"Ch4Mux", &RegisterAMCnt, 8, 2, 0x0};
+  AMACv2Field Ch3Mux ={"Ch3Mux", &RegisterAMCnt, 4, 2, 0x0};
   // 54 - DACs0
-  AMACv2Field DACShunty;
-  AMACv2Field DACShuntx;
-  AMACv2Field DACCALy;
-  AMACv2Field DACCalx;
+  AMACv2Field DACShunty ={"DACShunty", &RegisterDACs0, 24, 8, 0x0};
+  AMACv2Field DACShuntx ={"DACShuntx", &RegisterDACs0, 16, 8, 0x0};
+  AMACv2Field DACCALy ={"DACCALy", &RegisterDACs0, 8, 8, 0x0};
+  AMACv2Field DACCalx ={"DACCalx", &RegisterDACs0, 0, 8, 0x0};
   // 55 - DACbias
-  AMACv2Field DACbias;
-  // 56 - AMACcnt
-  AMACv2Field HVcurGain;
-  AMACv2Field DRcomMode;
-  AMACv2Field DRcurr;
-  AMACv2Field RingOscFrq;
-  // 57 - NTC
-  AMACv2Field CTAToffset;
-  AMACv2Field NTCpbCal;
-  AMACv2Field NTCpbSenseRange;
-  AMACv2Field NTCy0Cal;
-  AMACv2Field NTCy0SenseRange;
-  AMACv2Field NTCx0Cal;
-  AMACv2Field NTCx0SenseRange;
-  // 58 - LvCurCal
-  AMACv2Field DCDCoOffset;
-  AMACv2Field DCDCoZeroReading;
-  AMACv2Field DCDCoP;
-  AMACv2Field DCDCoN;
-  AMACv2Field DCDCiZeroReading;
-  AMACv2Field DCDCiRangeSW;
-  AMACv2Field DCDCiOffset;
-  AMACv2Field DCDCiP;
-  AMACv2Field DCDCiN;
-  // 60 - HxICcfg
-  AMACv2Field HxLAM;
-  AMACv2Field HxFlagsLatch;
-  AMACv2Field HxFlagsLogic;
-  AMACv2Field HxFlagValid;
-  AMACv2Field HxFlagsValidConf;
-  // 61 - HyICcfg
-  AMACv2Field HyLAM;
-  AMACv2Field HyFlagsLatch;
-  AMACv2Field HyFlagsLogic;
-  AMACv2Field HyFlagValid;
-  AMACv2Field HyFlagsValidConf;
-  // 62 - HV0ICcfg
-  AMACv2Field HV0LAM;
-  AMACv2Field HV0FlagsLatch;
-  AMACv2Field HV0FlagsLogic;
-  AMACv2Field HV0FlagValid;
-  AMACv2Field HV0FlagsValidConf;
-  // 63 - HV2ICcfg
-  AMACv2Field HV2LAM;
-  AMACv2Field HV2FlagsLatch;
-  AMACv2Field HV2FlagsLogic;
-  AMACv2Field HV2FlagValid;
-  AMACv2Field HV2FlagsValidConf;
-  // 64 - DCDCICcfg
-  AMACv2Field DCDCLAM;
-  AMACv2Field DCDCFlagsLatch;
-  AMACv2Field DCDCFlagsLogic;
-  AMACv2Field DCDCFlagValid;
-  AMACv2Field DCDCFlagsValidConf;
-  // 65 - WRNICcfg
-  AMACv2Field WRNLAM;
-  AMACv2Field WRNFlagsLatch;
-  AMACv2Field WRNFlagsLogic;
-  AMACv2Field WRNFlagValid;
-  AMACv2Field WRNFlagsValidConf;
-  // 70 - HxTlut
-  AMACv2Field HxTlut;
-  // 71 - HxModlut1
-  AMACv2Field HxModlut1;
-  // 72 - HxModlut2
-  AMACv2Field HxModlut2;
-  // 73 - HyTlut
-  AMACv2Field HyTlut;
-  // 74 - HyModlut1
-  AMACv2Field HyModlut1;
-  // 75 - HyModlut2
-  AMACv2Field HyModlut2;
-  // 76 - HV0Tlut;
-  AMACv2Field HV0Tlut;
-  // 77 - HV0Modlut1
-  AMACv2Field HV0Modlut1;
-  // 78 - HV0Modlut2
-  AMACv2Field HV0Modlut2;
-  // 79 - HV2Tlut
-  AMACv2Field HV2Tlut;
-  // 80 - HV2Modlut1
-  AMACv2Field HV2Modlut1;
-  // 81 - HV2Modlut2
-  AMACv2Field HV2Modlut2;
-  // 82 - DCDCTlut
-  AMACv2Field DCDCTlut;
-  // 83 - DCDCModlut1
-  AMACv2Field DCDCModlut1;
-  // 84 - DCDCModlut2
-  AMACv2Field DCDCModlut2	;
-  // 85 - WRNTlut
-  AMACv2Field WRNTlut;
-  // 86 - WRNModlut1
-  AMACv2Field WRNModlut1;
-  // 87 - WRNModlut2
-  AMACv2Field WRNModlut2;
+  AMACv2Field DACbias ={"DACbias", &RegisterDACbias, 0, 5, 0xD};
+  // 56 - AMACCnt
+  AMACv2Field HVcurGain ={"HVcurGain", &RegisterAMACCnt, 16, 4, 0x0};
+  AMACv2Field DRcomMode ={"DRcomMode", &RegisterAMACCnt, 12, 2, 0x0};
+  AMACv2Field DRcurr ={"DRcurr", &RegisterAMACCnt, 8, 3, 0x4};
+  AMACv2Field RingOscFrq ={"RingOscFrq", &RegisterAMACCnt, 0, 3, 0x4};
+  // 57 - NTCRange
+  AMACv2Field CTAToffset ={"CTAToffset", &RegisterNTCRange, 20, 4, 0x0};
+  AMACv2Field NTCpbCal ={"NTCpbCal", &RegisterNTCRange, 19, 1, 0x1};
+  AMACv2Field NTCpbSenseRange ={"NTCpbSenseRange", &RegisterNTCRange, 16, 3, 0x4};
+  AMACv2Field NTCy0Cal ={"NTCy0Cal", &RegisterNTCRange, 11, 1, 0x1};
+  AMACv2Field NTCy0SenseRange ={"NTCy0SenseRange", &RegisterNTCRange, 8, 3, 0x4};
+  AMACv2Field NTCx0Cal ={"NTCx0Cal", &RegisterNTCRange, 3, 1, 0x1};
+  AMACv2Field NTCx0SenseRange ={"NTCx0SenseRange", &RegisterNTCRange, 0, 3, 0x4};
+  // 58 - LVCurCal
+  AMACv2Field DCDCoOffset ={"DCDCoOffset", &RegisterLVCurCal, 20, 4, 0x4};
+  AMACv2Field DCDCoZeroReading ={"DCDCoZeroReading", &RegisterLVCurCal, 19, 1, 0x0};
+  AMACv2Field DCDCoN ={"DCDCoN", &RegisterLVCurCal, 17, 1, 0x0};
+  AMACv2Field DCDCoP ={"DCDCoP", &RegisterLVCurCal, 16, 1, 0x0};
+  AMACv2Field DCDCiZeroReading ={"DCDCiZeroReading", &RegisterLVCurCal, 15, 1, 0x0};
+  AMACv2Field DCDCiRangeSW ={"DCDCiRangeSW", &RegisterLVCurCal, 12, 1, 0x1};
+  AMACv2Field DCDCiOffset ={"DCDCiOffset", &RegisterLVCurCal, 8, 4, 0x8};
+  AMACv2Field DCDCiP ={"DCDCiP", &RegisterLVCurCal, 4, 3, 0x0};
+  AMACv2Field DCDCiN ={"DCDCiN", &RegisterLVCurCal, 0, 3, 0x0};
+  // 60 - HxICfg
+  AMACv2Field HxFlagValid  ={"HxFlagValid"  , &RegisterHxICfg,  0, 2, 0x0};
+  AMACv2Field HxFlagValidEn={"HxFlagValidEn", &RegisterHxICfg,  4, 1, 0x0};
+  AMACv2Field HxFlagsLogic ={"HxFlagsLogic" , &RegisterHxICfg,  8, 1, 0x0};
+  AMACv2Field HxFlagsLatch ={"HxFlagsLatch" , &RegisterHxICfg, 12, 1, 0x1};
+  AMACv2Field HxLAM        ={"HxLAM"        , &RegisterHxICfg, 16, 1, 0x0};
+  // 61 - HyICfg
+  AMACv2Field HyFlagValid  ={"HyFlagValid"  , &RegisterHyICfg,  0, 2, 0x0};
+  AMACv2Field HyFlagValidEn={"HyFlagValidEn", &RegisterHyICfg,  4, 1, 0x0};
+  AMACv2Field HyFlagsLogic ={"HyFlagsLogic" , &RegisterHyICfg,  8, 1, 0x0};
+  AMACv2Field HyFlagsLatch ={"HyFlagsLatch" , &RegisterHyICfg, 12, 1, 0x1};
+  AMACv2Field HyLAM        ={"HyLAM"        , &RegisterHyICfg, 16, 1, 0x0};
+  // 62 - HV0ICfg
+  AMACv2Field HV0FlagValid  ={"HV0FlagValid"  , &RegisterHV0ICfg,  0, 2, 0x0};
+  AMACv2Field HV0FlagValidEn={"HV0FlagValidEn", &RegisterHV0ICfg,  4, 1, 0x0};
+  AMACv2Field HV0FlagsLogic ={"HV0FlagsLogic" , &RegisterHV0ICfg,  8, 1, 0x0};
+  AMACv2Field HV0FlagsLatch ={"HV0FlagsLatch" , &RegisterHV0ICfg, 12, 1, 0x1};
+  AMACv2Field HV0LAM        ={"HV0LAM"        , &RegisterHV0ICfg, 16, 1, 0x0};
+  // 63 - HV2ICfg
+  AMACv2Field HV2FlagValid  ={"HV2FlagValid"  , &RegisterHV2ICfg,  0, 2, 0x0};
+  AMACv2Field HV2FlagValidEn={"HV2FlagValidEn", &RegisterHV2ICfg,  4, 1, 0x0};
+  AMACv2Field HV2FlagsLogic ={"HV2FlagsLogic" , &RegisterHV2ICfg,  8, 1, 0x0};
+  AMACv2Field HV2FlagsLatch ={"HV2FlagsLatch" , &RegisterHV2ICfg, 12, 1, 0x1};
+  AMACv2Field HV2LAM        ={"HV2LAM"        , &RegisterHV2ICfg, 16, 1, 0x0};
+  // 64 - DCDCICfg
+  AMACv2Field DCDCFlagValid  ={"DCDCFlagValid"  , &RegisterDCDCICfg,  0, 2, 0x0};
+  AMACv2Field DCDCFlagValidEn={"DCDCFlagValidEn", &RegisterDCDCICfg,  4, 1, 0x0};
+  AMACv2Field DCDCFlagsLogic ={"DCDCFlagsLogic" , &RegisterDCDCICfg,  8, 1, 0x0};
+  AMACv2Field DCDCFlagsLatch ={"DCDCFlagsLatch" , &RegisterDCDCICfg, 12, 1, 0x1};
+  AMACv2Field DCDCLAM        ={"DCDCLAM"        , &RegisterDCDCICfg, 16, 1, 0x0};
+  // 65 - WRNICfg
+  AMACv2Field WRNFlagValid  ={"WRNFlagValid"  , &RegisterWRNICfg,  0, 2, 0x0};
+  AMACv2Field WRNFlagValidEn={"WRNFlagValidEn", &RegisterWRNICfg,  4, 1, 0x0};
+  AMACv2Field WRNFlagsLogic ={"WRNFlagsLogic" , &RegisterWRNICfg,  8, 1, 0x0};
+  AMACv2Field WRNFlagsLatch ={"WRNFlagsLatch" , &RegisterWRNICfg, 12, 1, 0x1};
+  AMACv2Field WRNLAM        ={"WRNLAM"        , &RegisterWRNICfg, 16, 1, 0x0};
+  // 70 - HxTLUT
+  AMACv2Field HxTlut ={"HxTlut", &RegisterHxTLUT, 0, 8, 0x0};
+  // 71 - HxModLUT1
+  AMACv2Field HxModlut1 ={"HxModlut1", &RegisterHxModLUT1, 0, 32, 0x0};
+  // 72 - HxModLUT2
+  AMACv2Field HxModlut2 ={"HxModlut2", &RegisterHxModLUT2, 0, 32, 0x0};
+  // 73 - HyTLUT
+  AMACv2Field HyTlut ={"HyTlut", &RegisterHyTLUT, 0, 8, 0x0};
+  // 74 - HyModLUT1
+  AMACv2Field HyModlut1 ={"HyModlut1", &RegisterHyModLUT1, 0, 32, 0x0};
+  // 75 - HyModLUT2
+  AMACv2Field HyModlut2 ={"HyModlut2", &RegisterHyModLUT2, 0, 32, 0x0};
+  // 76 - HV0TLUT
+  AMACv2Field HV0Tlut ={"HV0Tlut", &RegisterHV0TLUT, 0, 8, 0x0};
+  // 77 - HV0ModLUT1
+  AMACv2Field HV0Modlut1 ={"HV0Modlut1", &RegisterHV0ModLUT1, 0, 32, 0x0};
+  // 78 - HV0ModLUT2
+  AMACv2Field HV0Modlut2 ={"HV0Modlut2", &RegisterHV0ModLUT2, 0, 32, 0x0};
+  // 79 - HV2TLUT
+  AMACv2Field HV2Tlut ={"HV2Tlut", &RegisterHV2TLUT, 0, 8, 0x0};
+  // 80 - HV2ModLUT1
+  AMACv2Field HV2Modlut1 ={"HV2Modlut1", &RegisterHV2ModLUT1, 0, 32, 0x0};
+  // 81 - HV2ModLUT2
+  AMACv2Field HV2Modlut2 ={"HV2Modlut2", &RegisterHV2ModLUT2, 0, 32, 0x0};
+  // 82 - DCDCTLUT
+  AMACv2Field DCDCTlut ={"DCDCTlut", &RegisterDCDCTLUT, 0, 8, 0x0};
+  // 83 - DCDCModLUT1
+  AMACv2Field DCDCModlut1 ={"DCDCModlut1", &RegisterDCDCModLUT1, 0, 32, 0x0};
+  // 84 - DCDCModLUT2
+  AMACv2Field DCDCModlut2 ={"DCDCModlut2", &RegisterDCDCModLUT2, 0, 32, 0x0};
+  // 85 - WRNTLUT
+  AMACv2Field WRNTlut ={"WRNTlut", &RegisterWRNTLUT, 0, 8, 0x0};
+  // 86 - WRNModLUT1
+  AMACv2Field WRNModlut1 ={"WRNModlut1", &RegisterWRNModLUT1, 0, 32, 0x0};
+  // 87 - WRNModLUT2
+  AMACv2Field WRNModlut2 ={"WRNModlut2", &RegisterWRNModLUT2, 0, 32, 0x0};
   // 90 - HxFlagEn
-  AMACv2Field HxFlagsEnHi;
-  AMACv2Field HxFlagsEnLo;
+  AMACv2Field HxFlagsEnHi ={"HxFlagsEnHi", &RegisterHxFlagEn, 16, 16, 0x0};
+  AMACv2Field HxFlagsEnLo ={"HxFlagsEnLo", &RegisterHxFlagEn, 16, 16, 0x0};
   // 91 - HyFlagEn
-  AMACv2Field HyFlagsEnHi;
-  AMACv2Field HyFlagsEnLo;
+  AMACv2Field HyFlagsEnHi ={"HyFlagsEnHi", &RegisterHyFlagEn, 16, 16, 0x0};
+  AMACv2Field HyFlagsEnLo ={"HyFlagsEnLo", &RegisterHyFlagEn, 16, 16, 0x0};
   // 92 - HV0FlagEn
-  AMACv2Field HV0FlagsEnHi;
-  AMACv2Field HV0FlagsEnLo;
+  AMACv2Field HV0FlagsEnHi ={"HV0FlagsEnHi", &RegisterHV0FlagEn, 16, 16, 0x0};
+  AMACv2Field HV0FlagsEnLo ={"HV0FlagsEnLo", &RegisterHV0FlagEn, 16, 16, 0x0};
   // 93 - HV2FlagEn
-  AMACv2Field HV2FlagsEnHi;
-  AMACv2Field HV2FlagsEnLo;
+  AMACv2Field HV2FlagsEnHi ={"HV2FlagsEnHi", &RegisterHV2FlagEn, 16, 16, 0x0};
+  AMACv2Field HV2FlagsEnLo ={"HV2FlagsEnLo", &RegisterHV2FlagEn, 16, 16, 0x0};
   // 94 - DCDCFlagEn
-  AMACv2Field DCDCFlagsEnHi;
-  AMACv2Field DCDCFlagsEnLo;
-  // 94 - WRNFlagEn
-  AMACv2Field WRNFlagsEnHi;
-  AMACv2Field WRNFlagsEnLo;
+  AMACv2Field DCDCFlagsEnHi ={"DCDCFlagsEnHi", &RegisterDCDCFlagEn, 16, 16, 0x0};
+  AMACv2Field DCDCFlagsEnLo ={"DCDCFlagsEnLo", &RegisterDCDCFlagEn, 16, 16, 0x0};
   // 95 - SynFlagEn
-  AMACv2Field WRNsynFlagEnHi;
-  AMACv2Field WRNsynFlagEnLo;
-  AMACv2Field DCDCsynFlagEnHi;
-  AMACv2Field DCDCsynFlagEnLo;
-  AMACv2Field HV2synFlagEnHi;
-  AMACv2Field HV2synFlagEnLo;
-  AMACv2Field HV0synFlagEnHi;
-  AMACv2Field HV0synFlagEnLo;
-  AMACv2Field HysynFlagEnHi;
-  AMACv2Field HysynFlagEnLo;
-  AMACv2Field HxsynFlagEnHi;
-  AMACv2Field HxsynFlagEnLo;
+  AMACv2Field WRNFlagsEnHi ={"WRNFlagsEnHi", &RegisterSynFlagEn, 16, 16, 0x0};
+  AMACv2Field WRNFlagsEnLo ={"WRNFlagsEnLo", &RegisterSynFlagEn, 16, 16, 0x0};
+  AMACv2Field WRNsynFlagEnHi ={"WRNsynFlagEnHi", &RegisterSynFlagEn, 21, 1, 0x0};
+  AMACv2Field WRNsynFlagEnLo ={"WRNsynFlagEnLo", &RegisterSynFlagEn, 20, 1, 0x0};
+  AMACv2Field DCDCsynFlagEnHi ={"DCDCsynFlagEnHi", &RegisterSynFlagEn, 17, 1, 0x0};
+  AMACv2Field DCDCsynFlagEnLo ={"DCDCsynFlagEnLo", &RegisterSynFlagEn, 16, 1, 0x0};
+  AMACv2Field HV2synFlagEnHi ={"HV2synFlagEnHi", &RegisterSynFlagEn, 13, 1, 0x0};
+  AMACv2Field HV2synFlagEnLo ={"HV2synFlagEnLo", &RegisterSynFlagEn, 12, 1, 0x0};
+  AMACv2Field HV0synFlagEnHi ={"HV0synFlagEnHi", &RegisterSynFlagEn, 9, 1, 0x0};
+  AMACv2Field HV0synFlagEnLo ={"HV0synFlagEnLo", &RegisterSynFlagEn, 8, 1, 0x0};
+  AMACv2Field HysynFlagEnHi ={"HysynFlagEnHi", &RegisterSynFlagEn, 5, 1, 0x0};
+  AMACv2Field HysynFlagEnLo ={"HysynFlagEnLo", &RegisterSynFlagEn, 4, 1, 0x0};
+  AMACv2Field HxsynFlagEnHi ={"HxsynFlagEnHi", &RegisterSynFlagEn, 1, 1, 0x0};
+  AMACv2Field HxsynFlagEnLo ={"HxsynFlagEnLo", &RegisterSynFlagEn, 0, 1, 0x0};
   // 100 - HxLoTh0
-  AMACv2Field HxLoThCh0;
-  AMACv2Field HxLoThCh1;
-  AMACv2Field HxLoThCh2;
+  AMACv2Field HxLoThCh0  ={"HxLoThCh0", &RegisterHxLoTh0,  0, 10, 0x0};
+  AMACv2Field HxLoThCh1  ={"HxLoThCh1", &RegisterHxLoTh0, 10, 10, 0x0};
+  AMACv2Field HxLoThCh2  ={"HxLoThCh2", &RegisterHxLoTh0, 20, 10, 0x0};
   // 101 - HxLoTh1
-  AMACv2Field HxLoThCh3;
-  AMACv2Field HxLoThCh4;
-  AMACv2Field HxLoThCh5;
+  AMACv2Field HxLoThCh3  ={"HxLoThCh3", &RegisterHxLoTh1,  0, 10, 0x0};
+  AMACv2Field HxLoThCh4  ={"HxLoThCh4", &RegisterHxLoTh1, 10, 10, 0x0};
+  AMACv2Field HxLoThCh5  ={"HxLoThCh5", &RegisterHxLoTh1, 20, 10, 0x0};
   // 102 - HxLoTh2
-  AMACv2Field HxLoThCh6;
-  AMACv2Field HxLoThCh7;
-  AMACv2Field HxLoThCh8;
+  AMACv2Field HxLoThCh6  ={"HxLoThCh6", &RegisterHxLoTh2,  0, 10, 0x0};
+  AMACv2Field HxLoThCh7  ={"HxLoThCh7", &RegisterHxLoTh2, 10, 10, 0x0};
+  AMACv2Field HxLoThCh8  ={"HxLoThCh8", &RegisterHxLoTh2, 20, 10, 0x0};
   // 103 - HxLoTh3
-  AMACv2Field HxLoThCh9;
-  AMACv2Field HxLoThCh10;
-  AMACv2Field HxLoThCh11;
+  AMACv2Field HxLoThCh9  ={"HxLoThCh9" , &RegisterHxLoTh3,  0, 10, 0x0};
+  AMACv2Field HxLoThCh10 ={"HxLoThCh10", &RegisterHxLoTh3, 10, 10, 0x0};
+  AMACv2Field HxLoThCh11 ={"HxLoThCh11", &RegisterHxLoTh3, 20, 10, 0x0};
   // 104 - HxLoTh4
-  AMACv2Field HxLoThCh12;
-  AMACv2Field HxLoThCh13;
-  AMACv2Field HxLoThCh14;
+  AMACv2Field HxLoThCh12 ={"HxLoThCh12", &RegisterHxLoTh4,  0, 10, 0x0};
+  AMACv2Field HxLoThCh13 ={"HxLoThCh13", &RegisterHxLoTh4, 10, 10, 0x0};
+  AMACv2Field HxLoThCh14 ={"HxLoThCh14", &RegisterHxLoTh4, 20, 10, 0x0};
   // 105 - HxLoTh5
-  AMACv2Field HxLoThCh15;
+  AMACv2Field HxLoThCh15 ={"HxLoThCh15", &RegisterHxLoTh5,  0, 10, 0x0};
   // 106 - HxHiTh0
-  AMACv2Field HxHiThCh0;
-  AMACv2Field HxHiThCh1;
-  AMACv2Field HxHiThCh2;
+  AMACv2Field HxHiThCh0  ={"HxHiThCh0" , &RegisterHxHiTh0,  0, 10, 0x3FF};
+  AMACv2Field HxHiThCh1  ={"HxHiThCh1" , &RegisterHxHiTh0, 10, 10, 0x3FF};
+  AMACv2Field HxHiThCh2  ={"HxHiThCh2" , &RegisterHxHiTh0, 20, 10, 0x3FF};
   // 107 - HxHiTh1
-  AMACv2Field HxHiThCh3;
-  AMACv2Field HxHiThCh4;
-  AMACv2Field HxHiThCh5;
+  AMACv2Field HxHiThCh3  ={"HxHiThCh3" , &RegisterHxHiTh1,  0, 10, 0x3FF};
+  AMACv2Field HxHiThCh4  ={"HxHiThCh4" , &RegisterHxHiTh1, 10, 10, 0x3FF};
+  AMACv2Field HxHiThCh5  ={"HxHiThCh5" , &RegisterHxHiTh1, 20, 10, 0x3FF};
   // 108 - HxHiTh2
-  AMACv2Field HxHiThCh6;
-  AMACv2Field HxHiThCh7;
-  AMACv2Field HxHiThCh8;
+  AMACv2Field HxHiThCh6  ={"HxHiThCh6" , &RegisterHxHiTh2,  0, 10, 0x3FF};
+  AMACv2Field HxHiThCh7  ={"HxHiThCh7" , &RegisterHxHiTh2, 10, 10, 0x3FF};
+  AMACv2Field HxHiThCh8  ={"HxHiThCh8" , &RegisterHxHiTh2, 20, 10, 0x3FF};
   // 109 - HxHiTh3
-  AMACv2Field HxHiThCh9;
-  AMACv2Field HxHiThCh10;
-  AMACv2Field HxHiThCh11;
+  AMACv2Field HxHiThCh9  ={"HxHiThCh9" , &RegisterHxHiTh3,  0, 10, 0x3FF};
+  AMACv2Field HxHiThCh10 ={"HxHiThCh10", &RegisterHxHiTh3, 10, 10, 0x3FF};
+  AMACv2Field HxHiThCh11 ={"HxHiThCh11", &RegisterHxHiTh3, 20, 10, 0x3FF};
   // 110 - HxHiTh4
-  AMACv2Field HxHiThCh12;
-  AMACv2Field HxHiThCh13;
-  AMACv2Field HxHiThCh14;
+  AMACv2Field HxHiThCh12 ={"HxHiThCh12", &RegisterHxHiTh4,  0, 10, 0x3FF};
+  AMACv2Field HxHiThCh13 ={"HxHiThCh13", &RegisterHxHiTh4, 10, 10, 0x3FF};
+  AMACv2Field HxHiThCh14 ={"HxHiThCh14", &RegisterHxHiTh4, 20, 10, 0x3FF};
   // 111 - HxHiTh5
-  AMACv2Field HxHiThCh15;
+  AMACv2Field HxHiThCh15 ={"HxHiThCh15", &RegisterHxHiTh5,  0, 10, 0x3FF};
   // 112 - HyLoTh0
-  AMACv2Field HyLoThCh0;
-  AMACv2Field HyLoThCh1;
-  AMACv2Field HyLoThCh2;
+  AMACv2Field HyLoThCh0 ={"HyLoThCh0", &RegisterHyLoTh0, 0, 10, 0x0};
+  AMACv2Field HyLoThCh1 ={"HyLoThCh1", &RegisterHyLoTh0, 10, 10, 0x0};
+  AMACv2Field HyLoThCh2 ={"HyLoThCh2", &RegisterHyLoTh0, 20, 10, 0x0};
   // 113 - HyLoTh1
-  AMACv2Field HyLoThCh3;
-  AMACv2Field HyLoThCh4;
-  AMACv2Field HyLoThCh5;
+  AMACv2Field HyLoThCh3 ={"HyLoThCh3", &RegisterHyLoTh1, 0, 10, 0x0};
+  AMACv2Field HyLoThCh4 ={"HyLoThCh4", &RegisterHyLoTh1, 10, 10, 0x0};
+  AMACv2Field HyLoThCh5 ={"HyLoThCh5", &RegisterHyLoTh1, 20, 10, 0x0};
   // 114 - HyLoTh2
-  AMACv2Field HyLoThCh6;
-  AMACv2Field HyLoThCh7;
-  AMACv2Field HyLoThCh8;
+  AMACv2Field HyLoThCh6 ={"HyLoThCh6", &RegisterHyLoTh2, 0, 10, 0x0};
+  AMACv2Field HyLoThCh7 ={"HyLoThCh7", &RegisterHyLoTh2, 10, 10, 0x0};
+  AMACv2Field HyLoThCh8 ={"HyLoThCh8", &RegisterHyLoTh2, 20, 10, 0x0};
   // 115 - HyLoTh3
-  AMACv2Field HyLoThCh9;
-  AMACv2Field HyLoThCh10;
-  AMACv2Field HyLoThCh11;
+  AMACv2Field HyLoThCh9 ={"HyLoThCh9", &RegisterHyLoTh3, 0, 10, 0x0};
+  AMACv2Field HyLoThCh10 ={"HyLoThCh10", &RegisterHyLoTh3, 10, 10, 0x0};
+  AMACv2Field HyLoThCh11 ={"HyLoThCh11", &RegisterHyLoTh3, 20, 10, 0x0};
   // 116 - HyLoTh4
-  AMACv2Field HyLoThCh12;
-  AMACv2Field HyLoThCh13;
-  AMACv2Field HyLoThCh14;
+  AMACv2Field HyLoThCh12 ={"HyLoThCh12", &RegisterHyLoTh4, 0, 10, 0x0};
+  AMACv2Field HyLoThCh13 ={"HyLoThCh13", &RegisterHyLoTh4, 10, 10, 0x0};
+  AMACv2Field HyLoThCh14 ={"HyLoThCh14", &RegisterHyLoTh4, 20, 10, 0x0};
   // 117 - HyLoTh5
-  AMACv2Field HyLoThCh15;
+  AMACv2Field HyLoThCh15 ={"HyLoThCh15", &RegisterHyLoTh5, 0, 10, 0x0};
   // 118 - HyHiTh0
-  AMACv2Field HyHiThCh0;
-  AMACv2Field HyHiThCh1;
-  AMACv2Field HyHiThCh2;
+  AMACv2Field HyHiThCh0 ={"HyHiThCh0", &RegisterHyHiTh0, 0, 10, 0x3FF};
+  AMACv2Field HyHiThCh1 ={"HyHiThCh1", &RegisterHyHiTh0, 10, 10, 0x3FF};
+  AMACv2Field HyHiThCh2 ={"HyHiThCh2", &RegisterHyHiTh0, 20, 10, 0x3FF};
   // 119 - HyHiTh1
-  AMACv2Field HyHiThCh3;
-  AMACv2Field HyHiThCh4;
-  AMACv2Field HyHiThCh5;
+  AMACv2Field HyHiThCh3 ={"HyHiThCh3", &RegisterHyHiTh1, 0, 10, 0x3FF};
+  AMACv2Field HyHiThCh4 ={"HyHiThCh4", &RegisterHyHiTh1, 10, 10, 0x3FF};
+  AMACv2Field HyHiThCh5 ={"HyHiThCh5", &RegisterHyHiTh1, 20, 10, 0x3FF};
   // 120 - HyHiTh2
-  AMACv2Field HyHiThCh6;
-  AMACv2Field HyHiThCh7;
-  AMACv2Field HyHiThCh8;
+  AMACv2Field HyHiThCh6 ={"HyHiThCh6", &RegisterHyHiTh2, 0, 10, 0x3FF};
+  AMACv2Field HyHiThCh7 ={"HyHiThCh7", &RegisterHyHiTh2, 10, 10, 0x3FF};
+  AMACv2Field HyHiThCh8 ={"HyHiThCh8", &RegisterHyHiTh2, 20, 10, 0x3FF};
   // 121 - HyHiTh3
-  AMACv2Field HyHiThCh9;
-  AMACv2Field HyHiThCh10;
-  AMACv2Field HyHiThCh11;
+  AMACv2Field HyHiThCh9 ={"HyHiThCh9", &RegisterHyHiTh3, 0, 10, 0x3FF};
+  AMACv2Field HyHiThCh10 ={"HyHiThCh10", &RegisterHyHiTh3, 10, 10, 0x3FF};
+  AMACv2Field HyHiThCh11 ={"HyHiThCh11", &RegisterHyHiTh3, 20, 10, 0x3FF};
   // 122 - HyHiTh4
-  AMACv2Field HyHiThCh12;
-  AMACv2Field HyHiThCh13;
-  AMACv2Field HyHiThCh14;
+  AMACv2Field HyHiThCh12 ={"HyHiThCh12", &RegisterHyHiTh4, 0, 10, 0x3FF};
+  AMACv2Field HyHiThCh13 ={"HyHiThCh13", &RegisterHyHiTh4, 10, 10, 0x3FF};
+  AMACv2Field HyHiThCh14 ={"HyHiThCh14", &RegisterHyHiTh4, 20, 10, 0x3FF};
   // 123 - HyHiTh5
-  AMACv2Field HyHiThCh15;
+  AMACv2Field HyHiThCh15 ={"HyHiThCh15", &RegisterHyHiTh5, 0, 10, 0x3FF};
   // 124 - HV0LoTh0
-  AMACv2Field HV0LoThCh0;
-  AMACv2Field HV0LoThCh1;
-  AMACv2Field HV0LoThCh2;
+  AMACv2Field HV0LoThCh0 ={"HV0LoThCh0", &RegisterHV0LoTh0, 0, 10, 0x0};
+  AMACv2Field HV0LoThCh1 ={"HV0LoThCh1", &RegisterHV0LoTh0, 10, 10, 0x0};
+  AMACv2Field HV0LoThCh2 ={"HV0LoThCh2", &RegisterHV0LoTh0, 20, 10, 0x0};
   // 125 - HV0LoTh1
-  AMACv2Field HV0LoThCh3;
-  AMACv2Field HV0LoThCh4;
-  AMACv2Field HV0LoThCh5;
+  AMACv2Field HV0LoThCh3 ={"HV0LoThCh3", &RegisterHV0LoTh1, 0, 10, 0x0};
+  AMACv2Field HV0LoThCh4 ={"HV0LoThCh4", &RegisterHV0LoTh1, 10, 10, 0x0};
+  AMACv2Field HV0LoThCh5 ={"HV0LoThCh5", &RegisterHV0LoTh1, 20, 10, 0x0};
   // 126 - HV0LoTh2
-  AMACv2Field HV0LoThCh6;
-  AMACv2Field HV0LoThCh7;
-  AMACv2Field HV0LoThCh8;
+  AMACv2Field HV0LoThCh6 ={"HV0LoThCh6", &RegisterHV0LoTh2, 0, 10, 0x0};
+  AMACv2Field HV0LoThCh7 ={"HV0LoThCh7", &RegisterHV0LoTh2, 10, 10, 0x0};
+  AMACv2Field HV0LoThCh8 ={"HV0LoThCh8", &RegisterHV0LoTh2, 20, 10, 0x0};
   // 127 - HV0LoTh3
-  AMACv2Field HV0LoThCh9;
-  AMACv2Field HV0LoThCh10;
-  AMACv2Field HV0LoThCh11;
+  AMACv2Field HV0LoThCh9 ={"HV0LoThCh9", &RegisterHV0LoTh3, 0, 10, 0x0};
+  AMACv2Field HV0LoThCh10 ={"HV0LoThCh10", &RegisterHV0LoTh3, 10, 10, 0x0};
+  AMACv2Field HV0LoThCh11 ={"HV0LoThCh11", &RegisterHV0LoTh3, 20, 10, 0x0};
   // 128 - HV0LoTh4
-  AMACv2Field HV0LoThCh12;
-  AMACv2Field HV0LoThCh13;
-  AMACv2Field HV0LoThCh14;
+  AMACv2Field HV0LoThCh12 ={"HV0LoThCh12", &RegisterHV0LoTh4, 0, 10, 0x0};
+  AMACv2Field HV0LoThCh13 ={"HV0LoThCh13", &RegisterHV0LoTh4, 10, 10, 0x0};
+  AMACv2Field HV0LoThCh14 ={"HV0LoThCh14", &RegisterHV0LoTh4, 20, 10, 0x0};
   // 129 - HV0LoTh5
-  AMACv2Field HV0LoThCh15;
+  AMACv2Field HV0LoThCh15 ={"HV0LoThCh15", &RegisterHV0LoTh5, 0, 10, 0x0};
   // 130 - HV0HiTh0
-  AMACv2Field HV0HiThCh0;
-  AMACv2Field HV0HiThCh1;
-  AMACv2Field HV0HiThCh2;
+  AMACv2Field HV0HiThCh0 ={"HV0HiThCh0", &RegisterHV0HiTh0, 0, 10, 0x3FF};
+  AMACv2Field HV0HiThCh1 ={"HV0HiThCh1", &RegisterHV0HiTh0, 10, 10, 0x3FF};
+  AMACv2Field HV0HiThCh2 ={"HV0HiThCh2", &RegisterHV0HiTh0, 20, 10, 0x3FF};
   // 131 - HV0HiTh1
-  AMACv2Field HV0HiThCh3;
-  AMACv2Field HV0HiThCh4;
-  AMACv2Field HV0HiThCh5;
+  AMACv2Field HV0HiThCh3 ={"HV0HiThCh3", &RegisterHV0HiTh1, 0, 10, 0x3FF};
+  AMACv2Field HV0HiThCh4 ={"HV0HiThCh4", &RegisterHV0HiTh1, 10, 10, 0x3FF};
+  AMACv2Field HV0HiThCh5 ={"HV0HiThCh5", &RegisterHV0HiTh1, 20, 10, 0x3FF};
   // 132 - HV0HiTh2
-  AMACv2Field HV0HiThCh6;
-  AMACv2Field HV0HiThCh7;
-  AMACv2Field HV0HiThCh8;
+  AMACv2Field HV0HiThCh6 ={"HV0HiThCh6", &RegisterHV0HiTh2, 0, 10, 0x3FF};
+  AMACv2Field HV0HiThCh7 ={"HV0HiThCh7", &RegisterHV0HiTh2, 10, 10, 0x3FF};
+  AMACv2Field HV0HiThCh8 ={"HV0HiThCh8", &RegisterHV0HiTh2, 20, 10, 0x3FF};
   // 133 - HV0HiTh3
-  AMACv2Field HV0HiThCh9;
-  AMACv2Field HV0HiThCh10;
-  AMACv2Field HV0HiThCh11;
+  AMACv2Field HV0HiThCh9 ={"HV0HiThCh9", &RegisterHV0HiTh3, 0, 10, 0x3FF};
+  AMACv2Field HV0HiThCh10 ={"HV0HiThCh10", &RegisterHV0HiTh3, 10, 10, 0x3FF};
+  AMACv2Field HV0HiThCh11 ={"HV0HiThCh11", &RegisterHV0HiTh3, 20, 10, 0x3FF};
   // 134 - HV0HiTh4
-  AMACv2Field HV0HiThCh12;
-  AMACv2Field HV0HiThCh13;
-  AMACv2Field HV0HiThCh14;
+  AMACv2Field HV0HiThCh12 ={"HV0HiThCh12", &RegisterHV0HiTh4, 0, 10, 0x3FF};
+  AMACv2Field HV0HiThCh13 ={"HV0HiThCh13", &RegisterHV0HiTh4, 10, 10, 0x3FF};
+  AMACv2Field HV0HiThCh14 ={"HV0HiThCh14", &RegisterHV0HiTh4, 20, 10, 0x3FF};
   // 135 - HV0HiTh5
-  AMACv2Field HV0HiThCh15;
-  // 136 - HV2LoTh0
-  AMACv2Field HV2LoThCh0;
-  AMACv2Field HV2LoThCh1;
-  AMACv2Field HV2LoThCh2;
+  AMACv2Field HV0HiThCh15 ={"HV0HiThCh15", &RegisterHV0HiTh5, 0, 10, 0x3FF};
+  // 136 - HV2HiTh0
+  AMACv2Field HV2LoThCh0 ={"HV2LoThCh0", &RegisterHV2LoTh0, 0, 10, 0x0};
+  AMACv2Field HV2LoThCh1 ={"HV2LoThCh1", &RegisterHV2LoTh0, 10, 10, 0x0};
+  AMACv2Field HV2LoThCh2 ={"HV2LoThCh2", &RegisterHV2LoTh0, 20, 10, 0x0};
   // 137 - HV2LoTh1
-  AMACv2Field HV2LoThCh3;
-  AMACv2Field HV2LoThCh4;
-  AMACv2Field HV2LoThCh5;
+  AMACv2Field HV2LoThCh3 ={"HV2LoThCh3", &RegisterHV2LoTh1, 0, 10, 0x0};
+  AMACv2Field HV2LoThCh4 ={"HV2LoThCh4", &RegisterHV2LoTh1, 10, 10, 0x0};
+  AMACv2Field HV2LoThCh5 ={"HV2LoThCh5", &RegisterHV2LoTh1, 20, 10, 0x0};
   // 138 - HV2LoTh2
-  AMACv2Field HV2LoThCh6;
-  AMACv2Field HV2LoThCh7;
-  AMACv2Field HV2LoThCh8;
+  AMACv2Field HV2LoThCh6 ={"HV2LoThCh6", &RegisterHV2LoTh2, 0, 10, 0x0};
+  AMACv2Field HV2LoThCh7 ={"HV2LoThCh7", &RegisterHV2LoTh2, 10, 10, 0x0};
+  AMACv2Field HV2LoThCh8 ={"HV2LoThCh8", &RegisterHV2LoTh2, 20, 10, 0x0};
   // 139 - HV2LoTh3
-  AMACv2Field HV2LoThCh9;
-  AMACv2Field HV2LoThCh10;
-  AMACv2Field HV2LoThCh11;
+  AMACv2Field HV2LoThCh9 ={"HV2LoThCh9", &RegisterHV2LoTh3, 0, 10, 0x0};
+  AMACv2Field HV2LoThCh10 ={"HV2LoThCh10", &RegisterHV2LoTh3, 10, 10, 0x0};
+  AMACv2Field HV2LoThCh11 ={"HV2LoThCh11", &RegisterHV2LoTh3, 20, 10, 0x0};
   // 140 - HV2LoTh4
-  AMACv2Field HV2LoThCh12;
-  AMACv2Field HV2LoThCh13;
-  AMACv2Field HV2LoThCh14;
+  AMACv2Field HV2LoThCh12 ={"HV2LoThCh12", &RegisterHV2LoTh4, 0, 10, 0x0};
+  AMACv2Field HV2LoThCh13 ={"HV2LoThCh13", &RegisterHV2LoTh4, 10, 10, 0x0};
+  AMACv2Field HV2LoThCh14 ={"HV2LoThCh14", &RegisterHV2LoTh4, 20, 10, 0x0};
   // 141 - HV2LoTh5
-  AMACv2Field HV2LoThCh15;
+  AMACv2Field HV2LoThCh15 ={"HV2LoThCh15", &RegisterHV2LoTh5, 0, 10, 0x0};
   // 142 - HV2HiTh0
-  AMACv2Field HV2HiThCh0;
-  AMACv2Field HV2HiThCh1;
-  AMACv2Field HV2HiThCh2;
+  AMACv2Field HV2HiThCh0 ={"HV2HiThCh0", &RegisterHV2HiTh0, 0, 10, 0x3FF};
+  AMACv2Field HV2HiThCh1 ={"HV2HiThCh1", &RegisterHV2HiTh0, 10, 10, 0x3FF};
+  AMACv2Field HV2HiThCh2 ={"HV2HiThCh2", &RegisterHV2HiTh0, 20, 10, 0x3FF};
   // 143 - HV2HiTh1
-  AMACv2Field HV2HiThCh3;
-  AMACv2Field HV2HiThCh4;
-  AMACv2Field HV2HiThCh5;
+  AMACv2Field HV2HiThCh3 ={"HV2HiThCh3", &RegisterHV2HiTh1, 0, 10, 0x3FF};
+  AMACv2Field HV2HiThCh4 ={"HV2HiThCh4", &RegisterHV2HiTh1, 10, 10, 0x3FF};
+  AMACv2Field HV2HiThCh5 ={"HV2HiThCh5", &RegisterHV2HiTh1, 20, 10, 0x3FF};
   // 144 - HV2HiTh2
-  AMACv2Field HV2HiThCh6;
-  AMACv2Field HV2HiThCh7;
-  AMACv2Field HV2HiThCh8;
+  AMACv2Field HV2HiThCh6 ={"HV2HiThCh6", &RegisterHV2HiTh2, 0, 10, 0x3FF};
+  AMACv2Field HV2HiThCh7 ={"HV2HiThCh7", &RegisterHV2HiTh2, 10, 10, 0x3FF};
+  AMACv2Field HV2HiThCh8 ={"HV2HiThCh8", &RegisterHV2HiTh2, 20, 10, 0x3FF};
   // 145 - HV2HiTh3
-  AMACv2Field HV2HiThCh9;
-  AMACv2Field HV2HiThCh10;
-  AMACv2Field HV2HiThCh11;
+  AMACv2Field HV2HiThCh9 ={"HV2HiThCh9", &RegisterHV2HiTh3, 0, 10, 0x3FF};
+  AMACv2Field HV2HiThCh10 ={"HV2HiThCh10", &RegisterHV2HiTh3, 10, 10, 0x3FF};
+  AMACv2Field HV2HiThCh11 ={"HV2HiThCh11", &RegisterHV2HiTh3, 20, 10, 0x3FF};
   // 146 - HV2HiTh4
-  AMACv2Field HV2HiThCh12;
-  AMACv2Field HV2HiThCh13;
-  AMACv2Field HV2HiThCh14;
+  AMACv2Field HV2HiThCh12 ={"HV2HiThCh12", &RegisterHV2HiTh4, 0, 10, 0x3FF};
+  AMACv2Field HV2HiThCh13 ={"HV2HiThCh13", &RegisterHV2HiTh4, 10, 10, 0x3FF};
+  AMACv2Field HV2HiThCh14 ={"HV2HiThCh14", &RegisterHV2HiTh4, 20, 10, 0x3FF};
   // 147 - HV2HiTh5
-  AMACv2Field HV2HiThCh15;
+  AMACv2Field HV2HiThCh15 ={"HV2HiThCh15", &RegisterHV2HiTh5, 0, 10, 0x3FF};
   // 148 - DCDCLoTh0
-  AMACv2Field DCDCLoThCh0;
-  AMACv2Field DCDCLoThCh1;
-  AMACv2Field DCDCLoThCh2;
+  AMACv2Field DCDCLoThCh0 ={"DCDCLoThCh0", &RegisterDCDCLoTh0, 0, 10, 0x0};
+  AMACv2Field DCDCLoThCh1 ={"DCDCLoThCh1", &RegisterDCDCLoTh0, 10, 10, 0x0};
+  AMACv2Field DCDCLoThCh2 ={"DCDCLoThCh2", &RegisterDCDCLoTh0, 20, 10, 0x0};
   // 149 - DCDCLoTh1
-  AMACv2Field DCDCLoThCh3;
-  AMACv2Field DCDCLoThCh4;
-  AMACv2Field DCDCLoThCh5;
+  AMACv2Field DCDCLoThCh3 ={"DCDCLoThCh3", &RegisterDCDCLoTh1, 0, 10, 0x0};
+  AMACv2Field DCDCLoThCh4 ={"DCDCLoThCh4", &RegisterDCDCLoTh1, 10, 10, 0x0};
+  AMACv2Field DCDCLoThCh5 ={"DCDCLoThCh5", &RegisterDCDCLoTh1, 20, 10, 0x0};
   // 150 - DCDCLoTh2
-  AMACv2Field DCDCLoThCh6;
-  AMACv2Field DCDCLoThCh7;
-  AMACv2Field DCDCLoThCh8;
+  AMACv2Field DCDCLoThCh6 ={"DCDCLoThCh6", &RegisterDCDCLoTh2, 0, 10, 0x0};
+  AMACv2Field DCDCLoThCh7 ={"DCDCLoThCh7", &RegisterDCDCLoTh2, 10, 10, 0x0};
+  AMACv2Field DCDCLoThCh8 ={"DCDCLoThCh8", &RegisterDCDCLoTh2, 20, 10, 0x0};
   // 151 - DCDCLoTh3
-  AMACv2Field DCDCLoThCh9;
-  AMACv2Field DCDCLoThCh10;
-  AMACv2Field DCDCLoThCh11;
+  AMACv2Field DCDCLoThCh9 ={"DCDCLoThCh9", &RegisterDCDCLoTh3, 0, 10, 0x0};
+  AMACv2Field DCDCLoThCh10 ={"DCDCLoThCh10", &RegisterDCDCLoTh3, 10, 10, 0x0};
+  AMACv2Field DCDCLoThCh11 ={"DCDCLoThCh11", &RegisterDCDCLoTh3, 20, 10, 0x0};
   // 152 - DCDCLoTh4
-  AMACv2Field DCDCLoThCh12;
-  AMACv2Field DCDCLoThCh13;
-  AMACv2Field DCDCLoThCh14;
+  AMACv2Field DCDCLoThCh12 ={"DCDCLoThCh12", &RegisterDCDCLoTh4, 0, 10, 0x0};
+  AMACv2Field DCDCLoThCh13 ={"DCDCLoThCh13", &RegisterDCDCLoTh4, 10, 10, 0x0};
+  AMACv2Field DCDCLoThCh14 ={"DCDCLoThCh14", &RegisterDCDCLoTh4, 20, 10, 0x0};
   // 153 - DCDCLoTh5
-  AMACv2Field DCDCLoThCh15;
+  AMACv2Field DCDCLoThCh15 ={"DCDCLoThCh15", &RegisterDCDCLoTh5, 0, 10, 0x0};
   // 154 - DCDCHiTh0
-  AMACv2Field DCDCHiThCh0;
-  AMACv2Field DCDCHiThCh1;
-  AMACv2Field DCDCHiThCh2;
+  AMACv2Field DCDCHiThCh0  ={"DCDCHiThCh0" , &RegisterDCDCHiTh0,  0, 10, 0x3FF};
+  AMACv2Field DCDCHiThCh1  ={"DCDCHiThCh1" , &RegisterDCDCHiTh0, 10, 10, 0x3FF};
+  AMACv2Field DCDCHiThCh2  ={"DCDCHiThCh2" , &RegisterDCDCHiTh0, 20, 10, 0x3FF};
   // 155 - DCDCHiTh1
-  AMACv2Field DCDCHiThCh3;
-  AMACv2Field DCDCHiThCh4;
-  AMACv2Field DCDCHiThCh5;
+  AMACv2Field DCDCHiThCh3  ={"DCDCHiThCh3" , &RegisterDCDCHiTh1,  0, 10, 0x3FF};
+  AMACv2Field DCDCHiThCh4  ={"DCDCHiThCh4" , &RegisterDCDCHiTh1, 10, 10, 0x3FF};
+  AMACv2Field DCDCHiThCh5  ={"DCDCHiThCh5" , &RegisterDCDCHiTh1, 20, 10, 0x3FF};
   // 156 - DCDCHiTh2
-  AMACv2Field DCDCHiThCh6;
-  AMACv2Field DCDCHiThCh7;
-  AMACv2Field DCDCHiThCh8;
+  AMACv2Field DCDCHiThCh6  ={"DCDCHiThCh6" , &RegisterDCDCHiTh2,  0, 10, 0x3FF};
+  AMACv2Field DCDCHiThCh7  ={"DCDCHiThCh7" , &RegisterDCDCHiTh2, 10, 10, 0x3FF};
+  AMACv2Field DCDCHiThCh8  ={"DCDCHiThCh8" , &RegisterDCDCHiTh2, 20, 10, 0x3FF};
   // 157 - DCDCHiTh3
-  AMACv2Field DCDCHiThCh9;
-  AMACv2Field DCDCHiThCh10;
-  AMACv2Field DCDCHiThCh11;
+  AMACv2Field DCDCHiThCh9  ={"DCDCHiThCh9" , &RegisterDCDCHiTh3,  0, 10, 0x3FF};
+  AMACv2Field DCDCHiThCh10 ={"DCDCHiThCh10", &RegisterDCDCHiTh3, 10, 10, 0x3FF};
+  AMACv2Field DCDCHiThCh11 ={"DCDCHiThCh11", &RegisterDCDCHiTh3, 20, 10, 0x3FF};
   // 158 - DCDCHiTh4
-  AMACv2Field DCDCHiThCh12;
-  AMACv2Field DCDCHiThCh13;
-  AMACv2Field DCDCHiThCh14;
+  AMACv2Field DCDCHiThCh12 ={"DCDCHiThCh12", &RegisterDCDCHiTh4,  0, 10, 0x3FF};
+  AMACv2Field DCDCHiThCh13 ={"DCDCHiThCh13", &RegisterDCDCHiTh4, 10, 10, 0x3FF};
+  AMACv2Field DCDCHiThCh14 ={"DCDCHiThCh14", &RegisterDCDCHiTh4, 20, 10, 0x3FF};
   // 159 - DCDCHiTh5
-  AMACv2Field DCDCHiThCh15;
+  AMACv2Field DCDCHiThCh15 ={"DCDCHiThCh15", &RegisterDCDCHiTh5,  0, 10, 0x3FF};
   // 160 - WRNLoTh0
-  AMACv2Field WRNLoThCh0;
-  AMACv2Field WRNLoThCh1;
-  AMACv2Field WRNLoThCh2;
+  AMACv2Field WRNLoThCh0  ={"WRNLoThCh0" , &RegisterWRNLoTh0,  0, 10, 0x0};
+  AMACv2Field WRNLoThCh1  ={"WRNLoThCh1" , &RegisterWRNLoTh0, 10, 10, 0x0};
+  AMACv2Field WRNLoThCh2  ={"WRNLoThCh2" , &RegisterWRNLoTh0, 20, 10, 0x0};
   // 161 - WRNLoTh1
-  AMACv2Field WRNLoThCh3;
-  AMACv2Field WRNLoThCh4;
-  AMACv2Field WRNLoThCh5;
+  AMACv2Field WRNLoThCh3  ={"WRNLoThCh3" , &RegisterWRNLoTh1,  0, 10, 0x0};
+  AMACv2Field WRNLoThCh4  ={"WRNLoThCh4" , &RegisterWRNLoTh1, 10, 10, 0x0};
+  AMACv2Field WRNLoThCh5  ={"WRNLoThCh5" , &RegisterWRNLoTh1, 20, 10, 0x0};
   // 162 - WRNLoTh2
-  AMACv2Field WRNLoThCh6;
-  AMACv2Field WRNLoThCh7;
-  AMACv2Field WRNLoThCh8;
+  AMACv2Field WRNLoThCh6  ={"WRNLoThCh6" , &RegisterWRNLoTh2,  0, 10, 0x0};
+  AMACv2Field WRNLoThCh7  ={"WRNLoThCh7" , &RegisterWRNLoTh2, 10, 10, 0x0};
+  AMACv2Field WRNLoThCh8  ={"WRNLoThCh8" , &RegisterWRNLoTh2, 20, 10, 0x0};
   // 163 - WRNLoTh3
-  AMACv2Field WRNLoThCh9;
-  AMACv2Field WRNLoThCh10;
-  AMACv2Field WRNLoThCh11;
+  AMACv2Field WRNLoThCh9  ={"WRNLoThCh9" , &RegisterWRNLoTh3,  0, 10, 0x0};
+  AMACv2Field WRNLoThCh10 ={"WRNLoThCh10", &RegisterWRNLoTh3, 10, 10, 0x0};
+  AMACv2Field WRNLoThCh11 ={"WRNLoThCh11", &RegisterWRNLoTh3, 20, 10, 0x0};
   // 164 - WRNLoTh4
-  AMACv2Field WRNLoThCh12;
-  AMACv2Field WRNLoThCh13;
-  AMACv2Field WRNLoThCh14;
+  AMACv2Field WRNLoThCh12 ={"WRNLoThCh12", &RegisterWRNLoTh4,  0, 10, 0x0};
+  AMACv2Field WRNLoThCh13 ={"WRNLoThCh13", &RegisterWRNLoTh4, 10, 10, 0x0};
+  AMACv2Field WRNLoThCh14 ={"WRNLoThCh14", &RegisterWRNLoTh4, 20, 10, 0x0};
   // 165 - WRNLoTh5
-  AMACv2Field WRNLoThCh15;
-  // 166 - WRNHiTh0;
-  AMACv2Field WRNHiThCh0;
-  AMACv2Field WRNHiThCh1;
-  AMACv2Field WRNHiThCh2;
+  AMACv2Field WRNLoThCh15 ={"WRNLoThCh15", &RegisterWRNLoTh5,  0, 10, 0x0};
+  // 166 - WRNHiTh0
+  AMACv2Field WRNHiThCh0  ={"WRNHiThCh0" , &RegisterWRNHiTh0,  0, 10, 0x3FF};
+  AMACv2Field WRNHiThCh1  ={"WRNHiThCh1" , &RegisterWRNHiTh0, 10, 10, 0x3FF};
+  AMACv2Field WRNHiThCh2  ={"WRNHiThCh2" , &RegisterWRNHiTh0, 20, 10, 0x3FF};
   // 167 - WRNHiTh1
-  AMACv2Field WRNHiThCh3;
-  AMACv2Field WRNHiThCh4;
-  AMACv2Field WRNHiThCh5;
+  AMACv2Field WRNHiThCh3  ={"WRNHiThCh3" , &RegisterWRNHiTh1,  0, 10, 0x3FF};
+  AMACv2Field WRNHiThCh4  ={"WRNHiThCh4" , &RegisterWRNHiTh1, 10, 10, 0x3FF};
+  AMACv2Field WRNHiThCh5  ={"WRNHiThCh5" , &RegisterWRNHiTh1, 20, 10, 0x3FF};
   // 168 - WRNHiTh2
-  AMACv2Field WRNHiThCh6;
-  AMACv2Field WRNHiThCh7;
-  AMACv2Field WRNHiThCh8;
+  AMACv2Field WRNHiThCh6  ={"WRNHiThCh6" , &RegisterWRNHiTh2,  0, 10, 0x3FF};
+  AMACv2Field WRNHiThCh7  ={"WRNHiThCh7" , &RegisterWRNHiTh2, 10, 10, 0x3FF};
+  AMACv2Field WRNHiThCh8  ={"WRNHiThCh8" , &RegisterWRNHiTh2, 20, 10, 0x3FF};
   // 169 - WRNHiTh3
-  AMACv2Field WRNHiThCh9;
-  AMACv2Field WRNHiThCh10;
-  AMACv2Field WRNHiThCh11;
+  AMACv2Field WRNHiThCh9  ={"WRNHiThCh9" , &RegisterWRNHiTh3,  0, 10, 0x3FF};
+  AMACv2Field WRNHiThCh10 ={"WRNHiThCh10", &RegisterWRNHiTh3, 10, 10, 0x3FF};
+  AMACv2Field WRNHiThCh11 ={"WRNHiThCh11", &RegisterWRNHiTh3, 20, 10, 0x3FF};
   // 170 - WRNHiTh4
-  AMACv2Field WRNHiThCh12;
-  AMACv2Field WRNHiThCh13;
-  AMACv2Field WRNHiThCh14;
+  AMACv2Field WRNHiThCh12 ={"WRNHiThCh12", &RegisterWRNHiTh4,  0, 10, 0x3FF};
+  AMACv2Field WRNHiThCh13 ={"WRNHiThCh13", &RegisterWRNHiTh4, 10, 10, 0x3FF};
+  AMACv2Field WRNHiThCh14 ={"WRNHiThCh14", &RegisterWRNHiTh4, 20, 10, 0x3FF};
   // 171 - WRNHiTh5
-  AMACv2Field WRNHiThCh15;
+  AMACv2Field WRNHiThCh15 ={"WRNHiThCh15", &RegisterWRNHiTh5,  0, 10, 0x3FF};
+
 
+  /** @} */  
 protected:
+  //! List of all registers
+  std::vector<AMACv2Register AMACv2RegMap::*> m_registers;
+  //! List of all fields
+  std::vector<AMACv2Field AMACv2RegMap::*> m_fields;
+  
+  //
+  // Name to attribute maps
+  std::unordered_map<uint8_t    , AMACv2Register AMACv2RegMap::*> m_regAddrMap;
+  std::unordered_map<std::string, AMACv2Register AMACv2RegMap::*> m_regMap;
   std::unordered_map<std::string, AMACv2Field AMACv2RegMap::*> m_fieldMap;
 };
 #endif //AMACREGMAP_H
diff --git a/pbv3/AMACv2Register.cpp b/pbv3/AMACv2Register.cpp
index e69de29b..155ead01 100644
--- a/pbv3/AMACv2Register.cpp
+++ b/pbv3/AMACv2Register.cpp
@@ -0,0 +1,20 @@
+#include "AMACv2Register.h"
+
+AMACv2Register::AMACv2Register(const std::string& name, uint32_t address, rw_t rw)
+  : m_name(name), m_address(address), m_rw(rw)
+{ }
+
+std::string AMACv2Register::getName() const
+{ return m_name; }
+
+uint8_t AMACv2Register::getAddress() const
+{ return m_address; }
+
+void AMACv2Register::setValue(uint32_t value)
+{ m_value=value; }
+
+uint32_t AMACv2Register::getValue() const
+{ return m_value; }
+
+rw_t AMACv2Register::isRW() const
+{ return m_rw; }
diff --git a/pbv3/AMACv2Register.h b/pbv3/AMACv2Register.h
index e6834920..24d87ea1 100644
--- a/pbv3/AMACv2Register.h
+++ b/pbv3/AMACv2Register.h
@@ -1,22 +1,51 @@
 #ifndef AMACV2REGISTER_H
 #define AMACV2REGISTER_H
 
+#include <iostream>
+
 enum rw_t {RO=1, WO=2, RW=3};
 
 //! \brief Description of an AMACv2 register
 class AMACv2Register
 {
- public:
+public:
+  //! \brief Create a named register
+  /**
+   * Default register values should be set through field
+   * operations.
+   *
+   * \param name Register name
+   * \param address Register address
+   * \param rw Read/write definition
+   */
+  AMACv2Register(const std::string& name, uint32_t address, rw_t rw);
+
+  //! Get the name
+  std::string getName() const;
+  
+  //! Get address
+  uint8_t getAddress() const;
+
+  //! set value
+  void setValue(uint32_t value);
+
+  //! Get value
+  uint32_t getValue() const;
+  
+  //! Get RW definition
+  rw_t isRW() const;
+  
+private:
   //! Helpful name for register
-  std::string name;
+  std::string m_name;
 
   //! Register address
-  uint8_t address;
+  uint8_t m_address;
   //! Register value
-  uint32_t value;
+  uint32_t m_value;
 
   //! Read/write mode
-  rw_t rw;
+  rw_t m_rw;
 };
 
 #endif // AMACV2REGISTER_H
diff --git a/pbv3/PBv3ConfigTools.cpp b/pbv3/PBv3ConfigTools.cpp
index 197cd251..694a809e 100644
--- a/pbv3/PBv3ConfigTools.cpp
+++ b/pbv3/PBv3ConfigTools.cpp
@@ -82,7 +82,7 @@ namespace PBv3ConfigTools
     for(const AMACv2Field* field : amac->getFields())
       {
 	if(field->isReadWrite())
-	  config["properties"][field->getFieldName()]=field->read();
+	  config["properties"][field->getName()]=field->read();
       }
   }
 
@@ -120,7 +120,7 @@ namespace PBv3ConfigTools
     logger(logINFO) << "## Tuning VDDREG ##";
     json config;
 
-    amac->wrField(&AMACv2Reg::VDDbgen, 1);
+    amac->wrField(&AMACv2RegMap::VDDbgen, 1);
 
     // Run the test
     double bestVDDREG=0;
@@ -128,7 +128,7 @@ namespace PBv3ConfigTools
 
     for(uint VDDbg=0;VDDbg<pow(2,4);VDDbg++)
       {
-	amac->wrField(&AMACv2Reg::VDDbg, VDDbg);
+	amac->wrField(&AMACv2RegMap::VDDbg, VDDbg);
 	usleep(5e3);
 
 	double VDDREG=amac->getVDDREG();
@@ -164,11 +164,11 @@ namespace PBv3ConfigTools
     uint32_t bestAMbg=0;
     json bestSlope, bestOffset;
 
-    amac->wrField(&AMACv2Reg::AMbgen, 1);
+    amac->wrField(&AMACv2RegMap::AMbgen, 1);
 
     for(uint AMbg=0;AMbg<pow(2,4);AMbg++)
       {
-	amac->wrField(&AMACv2Reg::AMbg, AMbg);
+	amac->wrField(&AMACv2RegMap::AMbg, AMbg);
 	usleep(5e3);
 	json slope =calibrateSlope (amac, CALdac);
 	json offset=calibrateOffset(amac);
@@ -210,12 +210,12 @@ namespace PBv3ConfigTools
     uint32_t bestAMintCalib=0;
     json bestSlope;
 
-    amac->wrField(&AMACv2Reg::Ch4Mux , 1); // Set Ch4 mux to CAL input
+    amac->wrField(&AMACv2RegMap::Ch4Mux , 1); // Set Ch4 mux to CAL input
     for(uint32_t AMintCalib=0;
 	AMintCalib<16;
 	AMintCalib++)
       {
-	amac->wrField(&AMACv2Reg::AMintCalib, AMintCalib);
+	amac->wrField(&AMACv2RegMap::AMintCalib, AMintCalib);
 	logger(logDEBUG) << "Set AMintCalib = " << AMintCalib;
 
 	json slope=calibrateSlope(amac, CALdac);
@@ -227,7 +227,7 @@ namespace PBv3ConfigTools
 	  }
       }
 
-    amac->wrField(&AMACv2Reg::AMintCalib, bestAMintCalib);
+    amac->wrField(&AMACv2RegMap::AMintCalib, bestAMintCalib);
     json bestOffset=calibrateOffset(amac);
 
     logger(logINFO) << "\tAMintCalib = " << bestAMintCalib;
@@ -248,25 +248,25 @@ namespace PBv3ConfigTools
 
     json config;
 
-    if(amac->rdField(&AMACv2Reg::DCDCen)==1)
+    if(amac->rdField(&AMACv2RegMap::DCDCen)==1)
       {
 	logger(logWARNING) << "tuneCur10V run with DCDCen=1";
       }
 
-    uint32_t DCDCiZeroReading_curr=amac->rdField(&AMACv2Reg::DCDCiZeroReading);
-    uint32_t Ch12Mux_curr         =amac->rdField(&AMACv2Reg::Ch12Mux         );
-    uint32_t DCDCiP_curr          =amac->rdField(&AMACv2Reg::DCDCiP          );
-    uint32_t DCDCiOffset_curr     =amac->rdField(&AMACv2Reg::DCDCiOffset     );
+    uint32_t DCDCiZeroReading_curr=amac->rdField(&AMACv2RegMap::DCDCiZeroReading);
+    uint32_t Ch12Mux_curr         =amac->rdField(&AMACv2RegMap::Ch12Mux         );
+    uint32_t DCDCiP_curr          =amac->rdField(&AMACv2RegMap::DCDCiP          );
+    uint32_t DCDCiOffset_curr     =amac->rdField(&AMACv2RegMap::DCDCiOffset     );
 
     //
     // Buffer offsets
-    amac->wrField(&AMACv2Reg::DCDCiZeroReading , 1); // Short the DCDCi inputs
+    amac->wrField(&AMACv2RegMap::DCDCiZeroReading , 1); // Short the DCDCi inputs
 
     logger(logDEBUG) << "Measuring relative buffer offset";
 
     static const uint32_t BOtests=4; // Defines number of samples per test point
 
-    amac->wrField(&AMACv2Reg::Ch12Mux , 1); // Read the low point
+    amac->wrField(&AMACv2RegMap::Ch12Mux , 1); // Read the low point
     double VtestLZero=0;
     for(uint32_t i=0;i<BOtests;i++)
       {
@@ -274,7 +274,7 @@ namespace PBv3ConfigTools
 	VtestLZero+=amac->getADC(12)/BOtests;
       }
 
-    amac->wrField(&AMACv2Reg::Ch12Mux , 2); // Read the high point
+    amac->wrField(&AMACv2RegMap::Ch12Mux , 2); // Read the high point
     double VtestHZero=0;
     for(uint32_t i=0;i<BOtests;i++)
       {
@@ -289,7 +289,7 @@ namespace PBv3ConfigTools
     //
     // Tune the current mirrors (does not do anything other than write values)
 
-    amac->wrField(&AMACv2Reg::DCDCiZeroReading , 0); // Separate the DCDCi inputs
+    amac->wrField(&AMACv2RegMap::DCDCiZeroReading , 0); // Separate the DCDCi inputs
 
     logger(logDEBUG) << "Tuning input CM mirror";
     double bestCMDV=-666; // Best attanable match
@@ -298,12 +298,12 @@ namespace PBv3ConfigTools
     static const uint32_t trails=100; // Number of trails per point
     for(uint32_t idcdcP=0;idcdcP<pow(2,3);idcdcP++)
       {
-	amac->wrField(&AMACv2Reg::DCDCiP, idcdcP);
+	amac->wrField(&AMACv2RegMap::DCDCiP, idcdcP);
 	for(uint32_t idcdcN=0;idcdcN<pow(2,3);idcdcN++)
 	  {
-	    amac->wrField(&AMACv2Reg::DCDCiN, idcdcN);
+	    amac->wrField(&AMACv2RegMap::DCDCiN, idcdcN);
 
-	    amac->wrField(&AMACv2Reg::Ch12Mux , 0); // Read the mid point
+	    amac->wrField(&AMACv2RegMap::Ch12Mux , 0); // Read the mid point
 
 	    double Vout=0;
 	    for(uint i=0;i<trails;i++)
@@ -313,7 +313,7 @@ namespace PBv3ConfigTools
 	      }
 	    Vout/=trails;
 
-	    amac->wrField(&AMACv2Reg::Ch12Mux , 1); // Read the low point
+	    amac->wrField(&AMACv2RegMap::Ch12Mux , 1); // Read the low point
 	    double VtestL=0;
 	    for(uint i=0;i<trails;i++)
 	      {
@@ -322,7 +322,7 @@ namespace PBv3ConfigTools
 	      }
 	    VtestL/=trails;
 
-	    amac->wrField(&AMACv2Reg::Ch12Mux , 2); // Read the high point
+	    amac->wrField(&AMACv2RegMap::Ch12Mux , 2); // Read the high point
 	    double VtestH=0;
 	    for(uint i=0;i<trails;i++)
 	      {
@@ -349,20 +349,20 @@ namespace PBv3ConfigTools
     //
     // Amplifier offset tunning
     //
-    amac->wrField(&AMACv2Reg::DCDCiP, bestidcdcP);
-    amac->wrField(&AMACv2Reg::DCDCiN, bestidcdcN);
-    amac->wrField(&AMACv2Reg::Ch12Mux , 0);
+    amac->wrField(&AMACv2RegMap::DCDCiP, bestidcdcP);
+    amac->wrField(&AMACv2RegMap::DCDCiN, bestidcdcN);
+    amac->wrField(&AMACv2RegMap::Ch12Mux , 0);
 
     //
     // Zero Mode
     logger(logDEBUG) << "Tuning amplifier offset, \"Zero Mode\"";
-    amac->wrField(&AMACv2Reg::DCDCiZeroReading , 1); // Short the DCDCi inputs
+    amac->wrField(&AMACv2RegMap::DCDCiZeroReading , 1); // Short the DCDCi inputs
 
     double bestDVZeroMode=-1;
     uint32_t bestOffset=0;
     for(uint i=0;i<pow(2,4);i++)
       {
-    	amac->wrField(&AMACv2Reg::DCDCiOffset, i);
+    	amac->wrField(&AMACv2RegMap::DCDCiOffset, i);
 	std::this_thread::sleep_for(std::chrono::milliseconds(2));
     	double DV=amac->getADC(12);
     	logger(logDEBUG) << " DCDCiOffset = " << i << ", DV = " << DV << " mV";
@@ -373,7 +373,7 @@ namespace PBv3ConfigTools
     	  }
       }
 
-    amac->wrField(&AMACv2Reg::DCDCiOffset, bestOffset);
+    amac->wrField(&AMACv2RegMap::DCDCiOffset, bestOffset);
     bestDVZeroMode=0;
     for(uint i=0; i<100; i++)
       {
@@ -389,14 +389,14 @@ namespace PBv3ConfigTools
     // Full Chain
     logger(logDEBUG) << "Tuning amplifier offset, \"Full Chain\"";
 
-    amac->wrField(&AMACv2Reg::DCDCiZeroReading , 0); // Separate the DCDCi inputs
+    amac->wrField(&AMACv2RegMap::DCDCiZeroReading , 0); // Separate the DCDCi inputs
 
     double bestDVFullChain=-1;
     /** Code to tune to offset to full chain
     uint32_t bestOffsetFullChain=0;
     for(uint i=0;i<pow(2,4);i++)
       {
-    	amac->wrField(&AMACv2Reg::DCDCiOffset, i);
+    	amac->wrField(&AMACv2RegMap::DCDCiOffset, i);
 	std::this_thread::sleep_for(std::chrono::milliseconds(2));
     	double DV=amac->getADC(12);
     	logger(logDEBUG) << " DCDCiOffset = " << i << ", DV = " << DV << " mV";
@@ -408,7 +408,7 @@ namespace PBv3ConfigTools
       }
     **/
 
-    amac->wrField(&AMACv2Reg::DCDCiOffset, bestOffset);
+    amac->wrField(&AMACv2RegMap::DCDCiOffset, bestOffset);
     bestDVFullChain=0;
     for(uint i=0; i<100; i++)
       {
@@ -429,10 +429,10 @@ namespace PBv3ConfigTools
     configAMAC(amac, config, true);
 
     // Revert to old state
-    amac->wrField(&AMACv2Reg::DCDCiZeroReading, DCDCiZeroReading_curr);
-    amac->wrField(&AMACv2Reg::Ch12Mux         , Ch12Mux_curr         );
-    amac->wrField(&AMACv2Reg::DCDCiP          , DCDCiP_curr          );
-    amac->wrField(&AMACv2Reg::DCDCiOffset     , DCDCiOffset_curr     );
+    amac->wrField(&AMACv2RegMap::DCDCiZeroReading, DCDCiZeroReading_curr);
+    amac->wrField(&AMACv2RegMap::Ch12Mux         , Ch12Mux_curr         );
+    amac->wrField(&AMACv2RegMap::DCDCiP          , DCDCiP_curr          );
+    amac->wrField(&AMACv2RegMap::DCDCiOffset     , DCDCiOffset_curr     );
 
     return config;
   }
@@ -444,20 +444,20 @@ namespace PBv3ConfigTools
     json config;
 
     // Power on the current mirrors
-    amac->wrField(&AMACv2Reg::DCDCen, 1);
-    amac->wrField(&AMACv2Reg::DCDCenC, 1);
+    amac->wrField(&AMACv2RegMap::DCDCen, 1);
+    amac->wrField(&AMACv2RegMap::DCDCenC, 1);
 
-    amac->wrField(&AMACv2Reg::DCDCoZeroReading , 1); // Short the DCDCo inputs
+    amac->wrField(&AMACv2RegMap::DCDCoZeroReading , 1); // Short the DCDCo inputs
 
     //
     // Tune the offset
-    amac->wrField(&AMACv2Reg::Ch13Mux , 0);
+    amac->wrField(&AMACv2RegMap::Ch13Mux , 0);
 
     double bestDV=-1;
     uint32_t bestOffset=0; 
     for(uint i=0;i<pow(2,4);i++)
       {
-    	amac->wrField(&AMACv2Reg::DCDCoOffset, i);
+    	amac->wrField(&AMACv2RegMap::DCDCoOffset, i);
     	usleep(5e3);
     	double DV=amac->getADC(13);
     	logger(logDEBUG) << " DCDCoOffset = " << i << ", DV = " << DV << " mV";
@@ -468,7 +468,7 @@ namespace PBv3ConfigTools
     	  }
       }
 
-    amac->wrField(&AMACv2Reg::DCDCoOffset, bestOffset);
+    amac->wrField(&AMACv2RegMap::DCDCoOffset, bestOffset);
     bestDV=0;
     for(uint i=0; i<100; i++)
       {
@@ -480,7 +480,7 @@ namespace PBv3ConfigTools
     logger(logINFO) << "\tDCDCoOffset = " << bestOffset;
     logger(logINFO) << "\toffset = " << bestDV << " mV";
 
-    amac->wrField(&AMACv2Reg::DCDCoZeroReading , 0); // separate the DCDCo inputs
+    amac->wrField(&AMACv2RegMap::DCDCoZeroReading , 0); // separate the DCDCo inputs
 
     //
     // Tune the current mirrors (does not do anything other than write values)
@@ -492,14 +492,14 @@ namespace PBv3ConfigTools
     uint32_t trails=2;
     for(uint32_t odcdcP=0;odcdcP<2;odcdcP++)
       {
-	amac->wrField(&AMACv2Reg::DCDCoP, odcdcP);
+	amac->wrField(&AMACv2RegMap::DCDCoP, odcdcP);
 	for(uint32_t odcdcN=0;odcdcN<2;odcdcN++)
 	  {
-	    amac->wrField(&AMACv2Reg::DCDCoN, odcdcN);
+	    amac->wrField(&AMACv2RegMap::DCDCoN, odcdcN);
 
 	    sleep(1);
 
-	    amac->wrField(&AMACv2Reg::Ch13Mux , 0); // Read the mid point
+	    amac->wrField(&AMACv2RegMap::Ch13Mux , 0); // Read the mid point
 	    double Vout=0;
 	    for(uint i=0;i<trails;i++)
 	      {
@@ -508,7 +508,7 @@ namespace PBv3ConfigTools
 	      }
 	    Vout/=trails;
 
-	    amac->wrField(&AMACv2Reg::Ch13Mux , 1); // Read the low point
+	    amac->wrField(&AMACv2RegMap::Ch13Mux , 1); // Read the low point
 	    double VtestL=0;
 	    for(uint i=0;i<trails;i++)
 	      {
@@ -517,7 +517,7 @@ namespace PBv3ConfigTools
 	      }
 	    VtestL/=trails;
 
-	    amac->wrField(&AMACv2Reg::Ch13Mux , 2); // Read the high point
+	    amac->wrField(&AMACv2RegMap::Ch13Mux , 2); // Read the high point
 	    double VtestH=0;
 	    for(uint i=0;i<trails;i++)
 	      {
@@ -541,8 +541,8 @@ namespace PBv3ConfigTools
     logger(logINFO) << "\tDCDCoP/N = " << bestodcdcP<<","<<bestodcdcN;
     logger(logINFO) << "\toffset = " << bestCMDV << " mV";
 
-    amac->wrField(&AMACv2Reg::DCDCen, 0);
-    amac->wrField(&AMACv2Reg::DCDCenC, 0);
+    amac->wrField(&AMACv2RegMap::DCDCen, 0);
+    amac->wrField(&AMACv2RegMap::DCDCenC, 0);
 
     config["properties"]["DCDCoOffset"] = bestOffset;
     config["properties"]["DCDCoP"] = bestodcdcP;
@@ -625,7 +625,7 @@ namespace PBv3ConfigTools
     double CALact=0;
     uint32_t CALamac=0;
 
-    amac->wrField(&AMACv2Reg::Ch4Mux , 1); // Set Ch4 mux to CAL input
+    amac->wrField(&AMACv2RegMap::Ch4Mux , 1); // Set Ch4 mux to CAL input
 
     // Run ramp
     std::vector<double> x,y;
@@ -641,7 +641,7 @@ namespace PBv3ConfigTools
 
 	// digital about
 	usleep(5e3);
-	CALamac = amac->rdField(&AMACv2Reg::Ch4Value);
+	CALamac = amac->rdField(&AMACv2RegMap::Ch4Value);
 	if(CALamac==1023) break; //saturated, don't include
 	if(750<CALamac && CALamac<760) continue; //Switch point
 
@@ -681,67 +681,67 @@ namespace PBv3ConfigTools
     json config;
 
     // Enable offset calibration
-    amac->wrField(&AMACv2Reg::AMzeroCalib , 1);
-    amac->wrField(&AMACv2Reg::AMzeroCalibC, 1);
+    amac->wrField(&AMACv2RegMap::AMzeroCalib , 1);
+    amac->wrField(&AMACv2RegMap::AMzeroCalibC, 1);
     usleep(5e3);
 
     // Calculate the calibration
     uint32_t counts;
 
-    counts=amac->rdField(&AMACv2Reg::Ch0Value );
+    counts=amac->rdField(&AMACv2RegMap::Ch0Value );
     config["results"]["AMOFFSET"][ 0] = counts;
 
-    counts=amac->rdField(&AMACv2Reg::Ch1Value );
+    counts=amac->rdField(&AMACv2RegMap::Ch1Value );
     config["results"]["AMOFFSET"][ 1] = counts;
 
-    counts=amac->rdField(&AMACv2Reg::Ch2Value );
+    counts=amac->rdField(&AMACv2RegMap::Ch2Value );
     config["results"]["AMOFFSET"][ 2] = counts;
 
-    counts=amac->rdField(&AMACv2Reg::Ch3Value );
+    counts=amac->rdField(&AMACv2RegMap::Ch3Value );
     config["results"]["AMOFFSET"][ 3] = counts;
 
-    counts=amac->rdField(&AMACv2Reg::Ch4Value );
+    counts=amac->rdField(&AMACv2RegMap::Ch4Value );
     config["results"]["AMOFFSET"][ 4] = counts;
 
-    counts=amac->rdField(&AMACv2Reg::Ch5Value );
+    counts=amac->rdField(&AMACv2RegMap::Ch5Value );
     config["results"]["AMOFFSET"][ 5] = counts;
 
-    counts=amac->rdField(&AMACv2Reg::Ch6Value );
+    counts=amac->rdField(&AMACv2RegMap::Ch6Value );
     config["results"]["AMOFFSET"][ 6] = counts;
 
-    counts=amac->rdField(&AMACv2Reg::Ch7Value );
+    counts=amac->rdField(&AMACv2RegMap::Ch7Value );
     config["results"]["AMOFFSET"][ 7] = counts;
 
-    counts=amac->rdField(&AMACv2Reg::Ch8Value );
+    counts=amac->rdField(&AMACv2RegMap::Ch8Value );
     config["results"]["AMOFFSET"][ 8] = counts;
 
-    counts=amac->rdField(&AMACv2Reg::Ch9Value );
+    counts=amac->rdField(&AMACv2RegMap::Ch9Value );
     config["results"]["AMOFFSET"][ 9] = counts;
 
-    counts=amac->rdField(&AMACv2Reg::Ch10Value);
+    counts=amac->rdField(&AMACv2RegMap::Ch10Value);
     config["results"]["AMOFFSET"][10] = counts;
 
-    counts=amac->rdField(&AMACv2Reg::Ch11Value);
+    counts=amac->rdField(&AMACv2RegMap::Ch11Value);
     config["results"]["AMOFFSET"][11] = counts;
 
-    counts=amac->rdField(&AMACv2Reg::Ch12Value);
+    counts=amac->rdField(&AMACv2RegMap::Ch12Value);
     config["results"]["AMOFFSET"][12] = counts;
 
-    counts=amac->rdField(&AMACv2Reg::Ch13Value);
+    counts=amac->rdField(&AMACv2RegMap::Ch13Value);
     config["results"]["AMOFFSET"][13] = counts;
 
-    counts=amac->rdField(&AMACv2Reg::Ch14Value);
+    counts=amac->rdField(&AMACv2RegMap::Ch14Value);
     config["results"]["AMOFFSET"][14] = counts;
 
-    counts=amac->rdField(&AMACv2Reg::Ch15Value);
+    counts=amac->rdField(&AMACv2RegMap::Ch15Value);
     config["results"]["AMOFFSET"][15] = counts;
 
     logger(logDEBUG) << config["results"]["AMOFFSET"];
 
 
     // Disable offset calibration
-    amac->wrField(&AMACv2Reg::AMzeroCalib , 0);
-    amac->wrField(&AMACv2Reg::AMzeroCalibC, 0);
+    amac->wrField(&AMACv2RegMap::AMzeroCalib , 0);
+    amac->wrField(&AMACv2RegMap::AMzeroCalibC, 0);
 
     configAMAC(amac, config, true);
 
@@ -755,9 +755,9 @@ namespace PBv3ConfigTools
     json config;
 
     // Enable NTC calibration
-    amac->wrField(&AMACv2Reg::NTCpbCal, 0);
-    amac->wrField(&AMACv2Reg::NTCx0Cal, 0);
-    amac->wrField(&AMACv2Reg::NTCy0Cal, 0);
+    amac->wrField(&AMACv2RegMap::NTCpbCal, 0);
+    amac->wrField(&AMACv2RegMap::NTCx0Cal, 0);
+    amac->wrField(&AMACv2RegMap::NTCy0Cal, 0);
     usleep(5e3);
 
     double NTCx =amac->getNTCx ();
@@ -773,9 +773,9 @@ namespace PBv3ConfigTools
     config["results"]["NTCPB"]= NTCpb;
 
     // Disable NTC calibration
-    amac->wrField(&AMACv2Reg::NTCpbCal, 1);
-    amac->wrField(&AMACv2Reg::NTCx0Cal, 1);
-    amac->wrField(&AMACv2Reg::NTCy0Cal, 1);
+    amac->wrField(&AMACv2RegMap::NTCpbCal, 1);
+    amac->wrField(&AMACv2RegMap::NTCx0Cal, 1);
+    amac->wrField(&AMACv2RegMap::NTCy0Cal, 1);
 
     configAMAC(amac, config, true);
 
@@ -788,9 +788,9 @@ namespace PBv3ConfigTools
 
     json config;
 
-    amac->wrField(&AMACv2Reg::DCDCiZeroReading , 1); // Short the DCDCi inputs
+    amac->wrField(&AMACv2RegMap::DCDCiZeroReading , 1); // Short the DCDCi inputs
 
-    amac->wrField(&AMACv2Reg::Ch12Mux , 0);
+    amac->wrField(&AMACv2RegMap::Ch12Mux , 0);
 
     double DV=0;
     for(uint i=0; i<100; i++)
@@ -803,7 +803,7 @@ namespace PBv3ConfigTools
     config["results"]["CUR10VOFFSET"] = DV;
     configAMAC(amac, config, true);
 
-    amac->wrField(&AMACv2Reg::DCDCiZeroReading , 0); // Separate the DCDCi inputs
+    amac->wrField(&AMACv2RegMap::DCDCiZeroReading , 0); // Separate the DCDCi inputs
 
     return config;
   }
@@ -814,9 +814,9 @@ namespace PBv3ConfigTools
 
     json config;
 
-    amac->wrField(&AMACv2Reg::DCDCoZeroReading , 1); // Short the DCDCo inputs
+    amac->wrField(&AMACv2RegMap::DCDCoZeroReading , 1); // Short the DCDCo inputs
 
-    amac->wrField(&AMACv2Reg::Ch13Mux , 0);
+    amac->wrField(&AMACv2RegMap::Ch13Mux , 0);
 
     double DV=0;
     for(uint i=0; i<100; i++)
@@ -829,7 +829,7 @@ namespace PBv3ConfigTools
     config["results"]["CUR1VOFFSET"] = DV;
     configAMAC(amac, config, true);
 
-    amac->wrField(&AMACv2Reg::DCDCoZeroReading , 0); // Separate the DCDCo inputs
+    amac->wrField(&AMACv2RegMap::DCDCoZeroReading , 0); // Separate the DCDCo inputs
 
     return config;
   }
@@ -841,7 +841,7 @@ namespace PBv3ConfigTools
     json config;
 
     uint32_t DCDCen_curr    =amac->rdField(&AMACv2::DCDCen);
-    uint32_t CTAToffset_curr=amac->rdField(&AMACv2Reg::CTAToffset);
+    uint32_t CTAToffset_curr=amac->rdField(&AMACv2RegMap::CTAToffset);
 
     //
     // Check if bPOL is enabled, heating everything up
@@ -885,7 +885,7 @@ namespace PBv3ConfigTools
     // Calibrate CTAT's
     for(uint32_t CTAToffset_set=0; CTAToffset_set<16; CTAToffset_set++)
       {
-	amac->wrField(&AMACv2Reg::CTAToffset, CTAToffset_set);
+	amac->wrField(&AMACv2RegMap::CTAToffset, CTAToffset_set);
 	std::this_thread::sleep_for(std::chrono::milliseconds(5));
 
 	double CTAT  = amac->getCTAT();
@@ -902,7 +902,7 @@ namespace PBv3ConfigTools
 	amac->wrField(&AMACv2::DCDCen , 1);
 	amac->wrField(&AMACv2::DCDCenC, 1);
       }
-    amac->wrField(&AMACv2Reg::CTAToffset, CTAToffset_curr );
+    amac->wrField(&AMACv2RegMap::CTAToffset, CTAToffset_curr );
 
     configAMAC(amac, config, true);
 
diff --git a/pbv3/PBv3ConfigTools.h b/pbv3/PBv3ConfigTools.h
index 00321afa..6f715db3 100644
--- a/pbv3/PBv3ConfigTools.h
+++ b/pbv3/PBv3ConfigTools.h
@@ -288,7 +288,7 @@ namespace PBv3ConfigTools
    *
    * \return updated json calibration
    */
-  json calibrateTemperature (std::shared_ptr<AMACv2> amac);
+  json calibrateTemperature(std::shared_ptr<AMACv2> amac);
 
   /**
    * \brief Determine the AMAC PADID
diff --git a/pbv3/PBv3TestTools.cpp b/pbv3/PBv3TestTools.cpp
index 374420d5..9556fa87 100644
--- a/pbv3/PBv3TestTools.cpp
+++ b/pbv3/PBv3TestTools.cpp
@@ -42,8 +42,8 @@ namespace PBv3TestTools
     // Disable DC/DC output
     try
       {
-	amac->wrField(&AMACv2::DCDCen, 0);
-	amac->wrField(&AMACv2::DCDCenC, 0);
+	amac->wrField(&AMACv2RegMap::DCDCen, 0);
+	amac->wrField(&AMACv2RegMap::DCDCenC, 0);
       }
     catch(const EndeavourComException &e)
       {
@@ -60,13 +60,13 @@ namespace PBv3TestTools
     double Iin  = tb->getVinCurrent();
     double Vin  = tb->getVin();
     double iout = tb->getLoad(pbNum);
-    int Vdcdc   = amac->rdField(&AMACv2::Ch0Value);
-    int VddLr   = amac->rdField(&AMACv2::Ch1Value);
-    int DCDCin  = amac->rdField(&AMACv2::Ch2Value);
-    int NTC     = amac->rdField(&AMACv2::Ch9Value);
-    int Cur10V  = amac->rdField(&AMACv2::Ch12Value);
-    int Cur1V   = amac->rdField(&AMACv2::Ch13Value);
-    int PTAT    = amac->rdField(&AMACv2::Ch15Value);
+    int Vdcdc   = amac->rdField(&AMACv2RegMap::Ch0Value);
+    int VddLr   = amac->rdField(&AMACv2RegMap::Ch1Value);
+    int DCDCin  = amac->rdField(&AMACv2RegMap::Ch2Value);
+    int NTC     = amac->rdField(&AMACv2RegMap::Ch9Value);
+    int Cur10V  = amac->rdField(&AMACv2RegMap::Ch12Value);
+    int Cur1V   = amac->rdField(&AMACv2RegMap::Ch13Value);
+    int PTAT    = amac->rdField(&AMACv2RegMap::Ch15Value);
 
     logger(logINFO) << " --> Reading " << lv_off << "V in off state.";
 
@@ -90,8 +90,8 @@ namespace PBv3TestTools
     logger(logINFO) << " --> Trying to turn on DCDC ...";
     try
       {
-	amac->wrField(&AMACv2::DCDCen, 1);
-	amac->wrField(&AMACv2::DCDCenC, 1);
+	amac->wrField(&AMACv2RegMap::DCDCen, 1);
+	amac->wrField(&AMACv2RegMap::DCDCenC, 1);
       }
     catch(EndeavourComException &e)
       {
@@ -106,13 +106,13 @@ namespace PBv3TestTools
     Iin  = tb->getVinCurrent();
     Vin  = tb->getVin();
     iout = tb->getLoad(pbNum);
-    Vdcdc  = amac->rdField(&AMACv2::Ch0Value);
-    VddLr  = amac->rdField(&AMACv2::Ch1Value);
-    DCDCin = amac->rdField(&AMACv2::Ch2Value);
-    NTC    = amac->rdField(&AMACv2::Ch9Value);
-    Cur10V = amac->rdField(&AMACv2::Ch12Value);
-    Cur1V  = amac->rdField(&AMACv2::Ch13Value);
-    PTAT   = amac->rdField(&AMACv2::Ch15Value);
+    Vdcdc  = amac->rdField(&AMACv2RegMap::Ch0Value);
+    VddLr  = amac->rdField(&AMACv2RegMap::Ch1Value);
+    DCDCin = amac->rdField(&AMACv2RegMap::Ch2Value);
+    NTC    = amac->rdField(&AMACv2RegMap::Ch9Value);
+    Cur10V = amac->rdField(&AMACv2RegMap::Ch12Value);
+    Cur1V  = amac->rdField(&AMACv2RegMap::Ch13Value);
+    PTAT   = amac->rdField(&AMACv2RegMap::Ch15Value);
     logger(logINFO) << " --> Reading " << lv_on << "V in on state.";
 
     testSum["results"]["LVENABLE"  ][1] = true;
@@ -172,10 +172,10 @@ namespace PBv3TestTools
     std::shared_ptr<AMACv2> amac=tb->getPB(pbNum);
 
     // Store current state
-    uint32_t DCDCen_curr =amac->rdField(&AMACv2Reg::DCDCen );
-    uint32_t DCDCenC_curr=amac->rdField(&AMACv2Reg::DCDCenC);
-    uint32_t Ch12Mux_curr=amac->rdField(&AMACv2Reg::Ch12Mux);
-    uint32_t Ch13Mux_curr=amac->rdField(&AMACv2Reg::Ch13Mux);
+    uint32_t DCDCen_curr =amac->rdField(&AMACv2RegMap::DCDCen );
+    uint32_t DCDCenC_curr=amac->rdField(&AMACv2RegMap::DCDCenC);
+    uint32_t Ch12Mux_curr=amac->rdField(&AMACv2RegMap::Ch12Mux);
+    uint32_t Ch13Mux_curr=amac->rdField(&AMACv2RegMap::Ch13Mux);
 
     //
     // Initialize
@@ -188,8 +188,8 @@ namespace PBv3TestTools
     tb->setVin(VinSet);
 
     logger(logINFO) << " --> Turn off DCDC ..";
-    amac->wrField(&AMACv2::DCDCen, 0);
-    amac->wrField(&AMACv2::DCDCenC, 0);
+    amac->wrField(&AMACv2RegMap::DCDCen, 0);
+    amac->wrField(&AMACv2RegMap::DCDCenC, 0);
     std::this_thread::sleep_for(std::chrono::milliseconds(500));
     
     double Iin_offset = tb->getVinCurrent();
@@ -197,8 +197,8 @@ namespace PBv3TestTools
     testSum["results"]["IINOFFSET"] = Iin_offset;
 
     logger(logINFO) << " --> Turn on DCDC ...";
-    amac->wrField(&AMACv2::DCDCen, 1);
-    amac->wrField(&AMACv2::DCDCenC, 1);
+    amac->wrField(&AMACv2RegMap::DCDCen, 1);
+    amac->wrField(&AMACv2RegMap::DCDCenC, 1);
 
     //unsigned dwell_time = .1; //s
     unsigned dwell_time_s = .005; //s
@@ -211,8 +211,8 @@ namespace PBv3TestTools
 	      << "\t" << "VddLr" << "\t" << "DCDCin" << "\t" << "NTC" << "\t"
 	      << "Cur10V" << "\t" << "Cur1V" << "\t" << "PTAT" << "\t" << "Efficiency" << "\t" << "EfficiencySense" << std::endl;
     // Set sub-channel
-    amac->wrField(&AMACv2::Ch12Mux, 0); //a
-    amac->wrField(&AMACv2::Ch13Mux, 0); //a
+    amac->wrField(&AMACv2RegMap::Ch12Mux, 0); //a
+    amac->wrField(&AMACv2RegMap::Ch13Mux, 0); //a
 
     // Loop over currents
     int index = 0;
@@ -231,13 +231,13 @@ namespace PBv3TestTools
 
 	for(uint32_t trail=0; trail<trails; trail++)
 	  {
-	    Vdcdc  = amac->rdField(&AMACv2::Ch0Value);
-	    VddLr  = amac->rdField(&AMACv2::Ch1Value);
-	    DCDCin = amac->rdField(&AMACv2::Ch2Value);
-	    NTC    = amac->rdField(&AMACv2::Ch9Value);
-	    Cur10V = amac->rdField(&AMACv2::Ch12Value);
-	    Cur1V  = amac->rdField(&AMACv2::Ch13Value);
-	    PTAT   = amac->rdField(&AMACv2::Ch15Value);
+	    Vdcdc  = amac->rdField(&AMACv2RegMap::Ch0Value);
+	    VddLr  = amac->rdField(&AMACv2RegMap::Ch1Value);
+	    DCDCin = amac->rdField(&AMACv2RegMap::Ch2Value);
+	    NTC    = amac->rdField(&AMACv2RegMap::Ch9Value);
+	    Cur10V = amac->rdField(&AMACv2RegMap::Ch12Value);
+	    Cur1V  = amac->rdField(&AMACv2RegMap::Ch13Value);
+	    PTAT   = amac->rdField(&AMACv2RegMap::Ch15Value);
 
 	    double Vin = tb->getVin();
             double Iin = tb->getVinCurrent();
@@ -273,10 +273,10 @@ namespace PBv3TestTools
     tb->loadOff(pbNum);
 
     // Revert to old state
-    amac->wrField(&AMACv2Reg::DCDCen , DCDCen_curr );
-    amac->wrField(&AMACv2Reg::DCDCenC, DCDCenC_curr);
-    amac->wrField(&AMACv2Reg::Ch12Mux, Ch12Mux_curr);
-    amac->wrField(&AMACv2Reg::Ch13Mux, Ch13Mux_curr);
+    amac->wrField(&AMACv2RegMap::DCDCen , DCDCen_curr );
+    amac->wrField(&AMACv2RegMap::DCDCenC, DCDCenC_curr);
+    amac->wrField(&AMACv2RegMap::Ch12Mux, Ch12Mux_curr);
+    amac->wrField(&AMACv2RegMap::Ch13Mux, Ch13Mux_curr);
 
     testSum["results"]["TIMEEND"] = PBv3Utils::getTimeAsString(std::chrono::system_clock::now());
 
@@ -297,21 +297,21 @@ namespace PBv3TestTools
     std::shared_ptr<AMACv2> amac=tb->getPB(pbNum);
     std::shared_ptr<PowerSupplyChannel> hv=tb->getHVPS();
 
-    uint32_t CntSetHV0frq_curr =amac->rdField(&AMACv2Reg::CntSetHV0frq );
-    uint32_t CntSetCHV0frq_curr=amac->rdField(&AMACv2Reg::CntSetCHV0frq);
-    uint32_t CntSetHV0en_curr  =amac->rdField(&AMACv2Reg::CntSetHV0en  );
-    uint32_t CntSetCHV0en_curr =amac->rdField(&AMACv2Reg::CntSetCHV0en );
-    uint32_t HVcurGain_curr    =amac->rdField(&AMACv2Reg::HVcurGain   );
+    uint32_t CntSetHV0frq_curr =amac->rdField(&AMACv2RegMap::CntSetHV0frq );
+    uint32_t CntSetCHV0frq_curr=amac->rdField(&AMACv2RegMap::CntSetCHV0frq);
+    uint32_t CntSetHV0en_curr  =amac->rdField(&AMACv2RegMap::CntSetHV0en  );
+    uint32_t CntSetCHV0en_curr =amac->rdField(&AMACv2RegMap::CntSetCHV0en );
+    uint32_t HVcurGain_curr    =amac->rdField(&AMACv2RegMap::HVcurGain   );
     
-    amac->wrField(&AMACv2Reg::HVcurGain, 4);
+    amac->wrField(&AMACv2RegMap::HVcurGain, 4);
 
     try
       {	
 	// Turn off HV enable from AMAC
-	amac->wrField(&AMACv2::CntSetHV0frq, frequency);
-	amac->wrField(&AMACv2::CntSetCHV0frq, frequency);
-	amac->wrField(&AMACv2::CntSetHV0en, 0);
-	amac->wrField(&AMACv2::CntSetCHV0en, 0);
+	amac->wrField(&AMACv2RegMap::CntSetHV0frq, frequency);
+	amac->wrField(&AMACv2RegMap::CntSetCHV0frq, frequency);
+	amac->wrField(&AMACv2RegMap::CntSetHV0en, 0);
+	amac->wrField(&AMACv2RegMap::CntSetCHV0en, 0);
       }
     catch(const EndeavourComException &e)
       {
@@ -332,7 +332,7 @@ namespace PBv3TestTools
     double hv_v_off = hv->measureVoltage();
     double hv_i_off = hv->measureCurrent();
     double hvout_i_off = tb->getHVoutCurrent(pbNum);
-    uint32_t HVret_off = amac->rdField(&AMACv2::Ch14Value);
+    uint32_t HVret_off = amac->rdField(&AMACv2RegMap::Ch14Value);
 
     testSum["results"]["CntSetHV0frq"][0] = frequency;
     testSum["results"]["CntSetHV0en" ][0] = false;
@@ -348,8 +348,8 @@ namespace PBv3TestTools
     logger(logINFO) << " --> Turn on HV enable.";
     try
       {
-	amac->wrField(&AMACv2::CntSetHV0en, 1);
-	amac->wrField(&AMACv2::CntSetCHV0en, 1);
+	amac->wrField(&AMACv2RegMap::CntSetHV0en, 1);
+	amac->wrField(&AMACv2RegMap::CntSetCHV0en, 1);
       }
     catch(const EndeavourComException &e)
       {
@@ -361,7 +361,7 @@ namespace PBv3TestTools
     double hv_v_on = hv->measureVoltage();
     double hv_i_on = hv->measureCurrent();
     double hvout_i_on = tb->getHVoutCurrent(pbNum);
-    uint32_t HVret_on = amac->rdField(&AMACv2::Ch14Value);
+    uint32_t HVret_on = amac->rdField(&AMACv2RegMap::Ch14Value);
 
     testSum["results"]["CntSetHV0frq"][1] = frequency;
     testSum["results"]["CntSetHV0en" ][1] = true;
@@ -401,11 +401,11 @@ namespace PBv3TestTools
     testSum["results"]["TIMEEND"] = PBv3Utils::getTimeAsString(std::chrono::system_clock::now());
 
     // Revert to old state
-    amac->wrField(&AMACv2Reg::CntSetHV0frq , CntSetHV0frq_curr );
-    amac->wrField(&AMACv2Reg::CntSetCHV0frq, CntSetCHV0frq_curr);
-    amac->wrField(&AMACv2Reg::CntSetHV0en  , CntSetHV0en_curr  );
-    amac->wrField(&AMACv2Reg::CntSetCHV0en , CntSetCHV0en_curr );
-    amac->wrField(&AMACv2Reg::HVcurGain    , HVcurGain_curr    );
+    amac->wrField(&AMACv2RegMap::CntSetHV0frq , CntSetHV0frq_curr );
+    amac->wrField(&AMACv2RegMap::CntSetCHV0frq, CntSetCHV0frq_curr);
+    amac->wrField(&AMACv2RegMap::CntSetHV0en  , CntSetHV0en_curr  );
+    amac->wrField(&AMACv2RegMap::CntSetCHV0en , CntSetCHV0en_curr );
+    amac->wrField(&AMACv2RegMap::HVcurGain    , HVcurGain_curr    );
   
     return testSum;
   }
@@ -421,25 +421,25 @@ namespace PBv3TestTools
     for(uint32_t index=0; index<tests; index++)
       {
 	// ADCs
-	uint32_t Vdcdc   = amac->rdField(&AMACv2::Ch0Value);
-	uint32_t VddLr   = amac->rdField(&AMACv2::Ch1Value);
-	uint32_t DCDCin  = amac->rdField(&AMACv2::Ch2Value);
-	amac->wrField(&AMACv2::Ch3Mux, 0); //a
-	uint32_t VDDREG  = amac->rdField(&AMACv2::Ch3Value);
-	amac->wrField(&AMACv2::Ch3Mux, 2); //c
-	uint32_t AM900BG = amac->rdField(&AMACv2::Ch3Value);
-	amac->wrField(&AMACv2::Ch4Mux, 0); //a
-	uint32_t AM600BG = amac->rdField(&AMACv2::Ch4Value);
-	amac->wrField(&AMACv2::Ch4Mux, 1); //b
-	uint32_t CALin   = amac->rdField(&AMACv2::Ch4Value);
-	uint32_t CTAT    = amac->rdField(&AMACv2::Ch6Value);
-	uint32_t NTCx    = amac->rdField(&AMACv2::Ch7Value);
-	uint32_t NTCy    = amac->rdField(&AMACv2::Ch8Value);
-	uint32_t NTCpb   = amac->rdField(&AMACv2::Ch9Value);
-	uint32_t Cur10V  = amac->rdField(&AMACv2::Ch12Value);
-	uint32_t Cur1V   = amac->rdField(&AMACv2::Ch13Value);
-	uint32_t HVret   = amac->rdField(&AMACv2::Ch14Value);
-	uint32_t PTAT    = amac->rdField(&AMACv2::Ch15Value);
+	uint32_t Vdcdc   = amac->rdField(&AMACv2RegMap::Ch0Value);
+	uint32_t VddLr   = amac->rdField(&AMACv2RegMap::Ch1Value);
+	uint32_t DCDCin  = amac->rdField(&AMACv2RegMap::Ch2Value);
+	amac->wrField(&AMACv2RegMap::Ch3Mux, 0); //a
+	uint32_t VDDREG  = amac->rdField(&AMACv2RegMap::Ch3Value);
+	amac->wrField(&AMACv2RegMap::Ch3Mux, 2); //c
+	uint32_t AM900BG = amac->rdField(&AMACv2RegMap::Ch3Value);
+	amac->wrField(&AMACv2RegMap::Ch4Mux, 0); //a
+	uint32_t AM600BG = amac->rdField(&AMACv2RegMap::Ch4Value);
+	amac->wrField(&AMACv2RegMap::Ch4Mux, 1); //b
+	uint32_t CALin   = amac->rdField(&AMACv2RegMap::Ch4Value);
+	uint32_t CTAT    = amac->rdField(&AMACv2RegMap::Ch6Value);
+	uint32_t NTCx    = amac->rdField(&AMACv2RegMap::Ch7Value);
+	uint32_t NTCy    = amac->rdField(&AMACv2RegMap::Ch8Value);
+	uint32_t NTCpb   = amac->rdField(&AMACv2RegMap::Ch9Value);
+	uint32_t Cur10V  = amac->rdField(&AMACv2RegMap::Ch12Value);
+	uint32_t Cur1V   = amac->rdField(&AMACv2RegMap::Ch13Value);
+	uint32_t HVret   = amac->rdField(&AMACv2RegMap::Ch14Value);
+	uint32_t PTAT    = amac->rdField(&AMACv2RegMap::Ch15Value);
 
 	double Vin = (lv!=nullptr)? lv->measureVoltage() : 0.;
 	double Iin = (lv!=nullptr)? lv->measureCurrent() : 0.;
@@ -561,50 +561,50 @@ namespace PBv3TestTools
 
     int counts;
 
-    amac->wrField(&AMACv2Reg::AMzeroCalib, 1);
-    amac->wrField(&AMACv2Reg::AMzeroCalibC, 1);
+    amac->wrField(&AMACv2RegMap::AMzeroCalib, 1);
+    amac->wrField(&AMACv2RegMap::AMzeroCalibC, 1);
 
-    uint32_t gain_curr=amac->rdField(&AMACv2Reg::AMintCalib);
+    uint32_t gain_curr=amac->rdField(&AMACv2RegMap::AMintCalib);
 
     int index = 0;
     for(uint32_t gain_set=((scanSettings)?0:gain_curr);
 	gain_set<((scanSettings)?16:(gain_curr+1));
 	gain_set++)
       {
-	amac->wrField(&AMACv2Reg::AMintCalib, gain_set);
+	amac->wrField(&AMACv2RegMap::AMintCalib, gain_set);
 	std::this_thread::sleep_for(std::chrono::milliseconds(5));
 
-	counts = amac->rdField(&AMACv2Reg::Ch0Value );
+	counts = amac->rdField(&AMACv2RegMap::Ch0Value );
 	testSum["results"][ "CH0"][index] = counts;
-	counts = amac->rdField(&AMACv2Reg::Ch1Value );
+	counts = amac->rdField(&AMACv2RegMap::Ch1Value );
 	testSum["results"][ "CH1"][index] = counts;
-	counts = amac->rdField(&AMACv2Reg::Ch2Value );
+	counts = amac->rdField(&AMACv2RegMap::Ch2Value );
 	testSum["results"][ "CH2"][index] = counts;
-	counts = amac->rdField(&AMACv2Reg::Ch3Value );
+	counts = amac->rdField(&AMACv2RegMap::Ch3Value );
 	testSum["results"][ "CH3"][index] = counts;
-	counts = amac->rdField(&AMACv2Reg::Ch4Value );
+	counts = amac->rdField(&AMACv2RegMap::Ch4Value );
 	testSum["results"][ "CH4"][index] = counts;
-	counts = amac->rdField(&AMACv2Reg::Ch5Value );
+	counts = amac->rdField(&AMACv2RegMap::Ch5Value );
 	testSum["results"][ "CH5"][index] = counts;
-	counts = amac->rdField(&AMACv2Reg::Ch6Value );
+	counts = amac->rdField(&AMACv2RegMap::Ch6Value );
 	testSum["results"][ "CH6"][index] = counts;
-	counts = amac->rdField(&AMACv2Reg::Ch7Value );
+	counts = amac->rdField(&AMACv2RegMap::Ch7Value );
 	testSum["results"][ "CH7"][index] = counts;
-	counts = amac->rdField(&AMACv2Reg::Ch8Value );
+	counts = amac->rdField(&AMACv2RegMap::Ch8Value );
 	testSum["results"][ "CH8"][index] = counts;
-	counts = amac->rdField(&AMACv2Reg::Ch9Value );
+	counts = amac->rdField(&AMACv2RegMap::Ch9Value );
 	testSum["results"][ "CH9"][index] = counts;
-	counts = amac->rdField(&AMACv2Reg::Ch10Value);
+	counts = amac->rdField(&AMACv2RegMap::Ch10Value);
 	testSum["results"]["CH10"][index] = counts;
-	counts = amac->rdField(&AMACv2Reg::Ch11Value);
+	counts = amac->rdField(&AMACv2RegMap::Ch11Value);
 	testSum["results"]["CH11"][index] = counts;
-	counts = amac->rdField(&AMACv2Reg::Ch12Value);
+	counts = amac->rdField(&AMACv2RegMap::Ch12Value);
 	testSum["results"]["CH12"][index] = counts;
-	counts = amac->rdField(&AMACv2Reg::Ch13Value);
+	counts = amac->rdField(&AMACv2RegMap::Ch13Value);
 	testSum["results"]["CH13"][index] = counts;
-	counts = amac->rdField(&AMACv2Reg::Ch14Value);
+	counts = amac->rdField(&AMACv2RegMap::Ch14Value);
 	testSum["results"]["CH14"][index] = counts;
-	counts = amac->rdField(&AMACv2Reg::Ch15Value);
+	counts = amac->rdField(&AMACv2RegMap::Ch15Value);
 	testSum["results"]["CH15"][index] = counts;
 
 	testSum["results"]["AMintCalib"][index] = gain_set;
@@ -634,26 +634,26 @@ namespace PBv3TestTools
 
     std::cout << "CAL" << "\t" << "BG" << "\t" << "RampGain" << "\t" << "ADCvalue" << std::endl;
 
-    uint32_t gain_curr  =amac->rdField(&AMACv2Reg::AMintCalib);
-    uint32_t bg_curr    =amac->rdField(&AMACv2Reg::AMbg      );
-    uint32_t Ch4Mux_curr=amac->rdField(&AMACv2Reg::Ch4Mux    );
+    uint32_t gain_curr  =amac->rdField(&AMACv2RegMap::AMintCalib);
+    uint32_t bg_curr    =amac->rdField(&AMACv2RegMap::AMbg      );
+    uint32_t Ch4Mux_curr=amac->rdField(&AMACv2RegMap::Ch4Mux    );
 
     // Run the test
     uint32_t index=0;
     double CALact=0;
     uint32_t CALamac=0;
-    amac->wrField(&AMACv2Reg::Ch4Mux , 1); // Set Ch4 mux to CAL input
+    amac->wrField(&AMACv2RegMap::Ch4Mux , 1); // Set Ch4 mux to CAL input
     for(uint32_t bg_set = ((scanSettings)?0:bg_curr);
 	bg_set<((scanSettings)?16:(bg_curr+1));
 	bg_set++)
       {
-	amac->wrField(&AMACv2Reg::AMbg , bg_set);
+	amac->wrField(&AMACv2RegMap::AMbg , bg_set);
 
 	for(uint32_t gain_set = (scanSettings)?0:gain_curr;
 	    gain_set<((scanSettings)?16:(gain_curr+1));
 	    gain_set++)
 	  {
-	    amac->wrField(&AMACv2Reg::AMintCalib, gain_set);
+	    amac->wrField(&AMACv2RegMap::AMintCalib, gain_set);
 
 	    // Longer wait for the first value due to RC constant
 	    CALdac->set(0);
@@ -665,7 +665,7 @@ namespace PBv3TestTools
 		// wait
 		std::this_thread::sleep_for(std::chrono::milliseconds(5));
 		// measure
-		CALamac = amac->rdField(&AMACv2Reg::Ch4Value);
+		CALamac = amac->rdField(&AMACv2RegMap::Ch4Value);
 
 		testSum["results"]["CALIN"     ][index] = CALact;
 		testSum["results"]["AMACCAL"   ][index] = CALamac;
@@ -681,9 +681,9 @@ namespace PBv3TestTools
     testSum["results"]["TIMEEND"] = PBv3Utils::getTimeAsString(std::chrono::system_clock::now());
 
     // Revert to old state
-    amac->wrField(&AMACv2Reg::AMintCalib, gain_curr  );
-    amac->wrField(&AMACv2Reg::AMbg      , bg_curr    );
-    amac->wrField(&AMACv2Reg::Ch4Mux    , Ch4Mux_curr);
+    amac->wrField(&AMACv2RegMap::AMintCalib, gain_curr  );
+    amac->wrField(&AMACv2RegMap::AMbg      , bg_curr    );
+    amac->wrField(&AMACv2RegMap::Ch4Mux    , Ch4Mux_curr);
 
     return testSum;
   }
@@ -762,9 +762,9 @@ namespace PBv3TestTools
     std::shared_ptr<AMACv2> amac=tb->getPB(pbNum);
     std::shared_ptr<PowerSupplyChannel> hv=tb->getHVPS();
 
-    uint32_t CntSetHV0en_curr  =amac->rdField(&AMACv2Reg::CntSetHV0en );
-    uint32_t CntSetCHV0en_curr =amac->rdField(&AMACv2Reg::CntSetCHV0en);
-    uint32_t HVcurGain_curr    =amac->rdField(&AMACv2Reg::HVcurGain   );
+    uint32_t CntSetHV0en_curr  =amac->rdField(&AMACv2RegMap::CntSetHV0en );
+    uint32_t CntSetCHV0en_curr =amac->rdField(&AMACv2RegMap::CntSetCHV0en);
+    uint32_t HVcurGain_curr    =amac->rdField(&AMACv2RegMap::HVcurGain   );
 
     double ileak_min = 0;
     double ileak_max = 1.0e-3;
@@ -779,8 +779,8 @@ namespace PBv3TestTools
     hv->turnOn();
 
     logger(logINFO) << " --> Turn on HVmux";
-    amac->wrField(&AMACv2::CntSetHV0en , 1);
-    amac->wrField(&AMACv2::CntSetCHV0en, 1);
+    amac->wrField(&AMACv2RegMap::CntSetHV0en , 1);
+    amac->wrField(&AMACv2RegMap::CntSetCHV0en, 1);
 
     logger(logINFO) << " --> Starting measurement";
     std::cout << "HV_i_set\tHV_v_set\tHV_v\t\tHV_i\t\tHVout_i\t\tGain 0\tGain 1\tGain 2\tGain 4\tGain 8" << std::endl;
@@ -805,12 +805,12 @@ namespace PBv3TestTools
 	    for (unsigned g=0; g<5; g++)
 	      {
 		if (g == 0)
-		  amac->wrField(&AMACv2::HVcurGain, 0);
+		  amac->wrField(&AMACv2RegMap::HVcurGain, 0);
 		else
-		  amac->wrField(&AMACv2::HVcurGain, pow(2,g-1));
+		  amac->wrField(&AMACv2RegMap::HVcurGain, pow(2,g-1));
 
 		std::this_thread::sleep_for(std::chrono::milliseconds(500));
-		val[g] = amac->rdField(&AMACv2::Ch14Value);
+		val[g] = amac->rdField(&AMACv2RegMap::Ch14Value);
 	      }
 	    std::cout << std::scientific << std::setprecision(3) << ileak << "\t" << ileak*resist<< "\t" << hv_v << "\t" << hv_i << "\t" << hvout_i << "\t" << std::dec << val[0] << "\t" << val[1] << "\t" << val[2] << "\t" << val[3] << "\t" << val[4] << std::endl;
 	    testSum["results"]["ILEAK"    ][index]=ileak;
@@ -832,9 +832,9 @@ namespace PBv3TestTools
     testSum["results"]["TIMEEND"] = PBv3Utils::getTimeAsString(std::chrono::system_clock::now());
 
     // Revert to old state
-    amac->wrField(&AMACv2Reg::CntSetHV0en , CntSetHV0en_curr );
-    amac->wrField(&AMACv2Reg::CntSetCHV0en, CntSetCHV0en_curr);
-    amac->wrField(&AMACv2Reg::HVcurGain   , HVcurGain_curr   );
+    amac->wrField(&AMACv2RegMap::CntSetHV0en , CntSetHV0en_curr );
+    amac->wrField(&AMACv2RegMap::CntSetCHV0en, CntSetCHV0en_curr);
+    amac->wrField(&AMACv2RegMap::HVcurGain   , HVcurGain_curr   );
 
     return testSum;
   }
@@ -862,12 +862,12 @@ namespace PBv3TestTools
 	for (unsigned g=0; g<5; g++)
 	  {
 	    if (g == 0)
-	      amac->wrField(&AMACv2::HVcurGain, 0);
+	      amac->wrField(&AMACv2RegMap::HVcurGain, 0);
 	    else
-	      amac->wrField(&AMACv2::HVcurGain, pow(2,g-1));
+	      amac->wrField(&AMACv2RegMap::HVcurGain, pow(2,g-1));
 
 	    std::this_thread::sleep_for(std::chrono::milliseconds(10));
-	    val[g] = amac->rdField(&AMACv2::Ch14Value);
+	    val[g] = amac->rdField(&AMACv2RegMap::Ch14Value);
 	  }
 	std::cout << std::scientific << std::setprecision(3) << hv_v << "\t" << hv_i << "\t" << std::dec << val[0] << "\t" << val[1] << "\t" << val[2] << "\t" << val[3] << "\t" << val[4] << std::endl;
 	testSum["results"]["HVV"      ][index]=hv_v;
@@ -947,7 +947,7 @@ namespace PBv3TestTools
 	int DCDCin;
 	try
 	  {
-	    DCDCin = amac->rdField(&AMACv2::Ch2Value);
+	    DCDCin = amac->rdField(&AMACv2RegMap::Ch2Value);
 	  }
 	catch(EndeavourComException &e)
 	  {
@@ -986,17 +986,17 @@ namespace PBv3TestTools
     std::shared_ptr<AMACv2> amac = tb->getPB(pbNum);
 
     // Store current state
-    uint32_t DCDCen_curr          =amac->rdField(&AMACv2Reg::DCDCen          );
-    uint32_t DCDCenC_curr         =amac->rdField(&AMACv2Reg::DCDCenC         );
+    uint32_t DCDCen_curr          =amac->rdField(&AMACv2RegMap::DCDCen          );
+    uint32_t DCDCenC_curr         =amac->rdField(&AMACv2RegMap::DCDCenC         );
 
-    uint32_t DCDCiZeroReading_curr=amac->rdField(&AMACv2Reg::DCDCiZeroReading);
-    uint32_t DCDCiOffset_curr     =amac->rdField(&AMACv2Reg::DCDCiOffset     );
-    uint32_t DCDCiP_curr          =amac->rdField(&AMACv2Reg::DCDCiP          );
-    uint32_t DCDCiN_curr          =amac->rdField(&AMACv2Reg::DCDCiN          );
+    uint32_t DCDCiZeroReading_curr=amac->rdField(&AMACv2RegMap::DCDCiZeroReading);
+    uint32_t DCDCiOffset_curr     =amac->rdField(&AMACv2RegMap::DCDCiOffset     );
+    uint32_t DCDCiP_curr          =amac->rdField(&AMACv2RegMap::DCDCiP          );
+    uint32_t DCDCiN_curr          =amac->rdField(&AMACv2RegMap::DCDCiN          );
 
     logger(logINFO) << " --> Turn off DCDC ...";
-    amac->wrField(&AMACv2::DCDCen , 0);
-    amac->wrField(&AMACv2::DCDCenC, 0);
+    amac->wrField(&AMACv2RegMap::DCDCen , 0);
+    amac->wrField(&AMACv2RegMap::DCDCenC, 0);
 
     logger(logINFO) << " --> Starting measurement ...";
 
@@ -1006,34 +1006,34 @@ namespace PBv3TestTools
     // Short the P/N
     for(uint DCDCiZeroReading=0;DCDCiZeroReading<2;DCDCiZeroReading++)
       {
-	amac->wrField(&AMACv2Reg::DCDCiZeroReading , DCDCiZeroReading);
+	amac->wrField(&AMACv2RegMap::DCDCiZeroReading , DCDCiZeroReading);
 	logger(logDEBUG) << "Set DCDCiZeroReading = " << DCDCiZeroReading;
 	for(uint DCDCiOffset=0;DCDCiOffset<pow(2,4);DCDCiOffset++)
 	  {
-	    amac->wrField(&AMACv2Reg::DCDCiOffset, DCDCiOffset);
+	    amac->wrField(&AMACv2RegMap::DCDCiOffset, DCDCiOffset);
 	    logger(logDEBUG) << "Set DCDCiOffset = " << DCDCiOffset;
 	    for(uint32_t DCDCiP=0;DCDCiP<pow(2,3);DCDCiP++)
 	      {
-		amac->wrField(&AMACv2Reg::DCDCiP, DCDCiP);
+		amac->wrField(&AMACv2RegMap::DCDCiP, DCDCiP);
 		logger(logDEBUG) << "Set DCDCiP = " << DCDCiP;
 		for(uint32_t DCDCiN=0;DCDCiN<pow(2,3);DCDCiN++)
 		  {
-		    amac->wrField(&AMACv2Reg::DCDCiN, DCDCiN);
+		    amac->wrField(&AMACv2RegMap::DCDCiN, DCDCiN);
 		    logger(logDEBUG) << "Set DCDCiN = " << DCDCiN;
 
 		    for (uint32_t i=0; i<tests; i++)
 		      {
-			amac->wrField(&AMACv2::Ch12Mux, 0); //a
+			amac->wrField(&AMACv2RegMap::Ch12Mux, 0); //a
 			std::this_thread::sleep_for(std::chrono::milliseconds(2));
-			Cur10V = amac->rdField(&AMACv2::Ch12Value);
+			Cur10V = amac->rdField(&AMACv2RegMap::Ch12Value);
 
-			amac->wrField(&AMACv2::Ch12Mux, 1); //b
+			amac->wrField(&AMACv2RegMap::Ch12Mux, 1); //b
 			std::this_thread::sleep_for(std::chrono::milliseconds(2));
-			Cur10VTPL = amac->rdField(&AMACv2::Ch12Value);
+			Cur10VTPL = amac->rdField(&AMACv2RegMap::Ch12Value);
 
-			amac->wrField(&AMACv2::Ch12Mux, 2); //c
+			amac->wrField(&AMACv2RegMap::Ch12Mux, 2); //c
 			std::this_thread::sleep_for(std::chrono::milliseconds(2));
-			Cur10VTPH = amac->rdField(&AMACv2::Ch12Value);
+			Cur10VTPH = amac->rdField(&AMACv2RegMap::Ch12Value);
 
 			testSum["results"]["DCDCiZeroReading"][index] = DCDCiZeroReading;
 			testSum["results"]["DCDCiOffset"     ][index] = DCDCiOffset;
@@ -1052,12 +1052,12 @@ namespace PBv3TestTools
     testSum["results"]["TIMEEND"] = PBv3Utils::getTimeAsString(std::chrono::system_clock::now());
   
     // Revert to old state
-    amac->wrField(&AMACv2Reg::DCDCen          ,DCDCen_curr          );
-    amac->wrField(&AMACv2Reg::DCDCenC         ,DCDCenC_curr         );
-    amac->wrField(&AMACv2Reg::DCDCiZeroReading,DCDCiZeroReading_curr);
-    amac->wrField(&AMACv2Reg::DCDCiOffset     ,DCDCiOffset_curr     );
-    amac->wrField(&AMACv2Reg::DCDCiP          ,DCDCiP_curr          );
-    amac->wrField(&AMACv2Reg::DCDCiN          ,DCDCiN_curr          );
+    amac->wrField(&AMACv2RegMap::DCDCen          ,DCDCen_curr          );
+    amac->wrField(&AMACv2RegMap::DCDCenC         ,DCDCenC_curr         );
+    amac->wrField(&AMACv2RegMap::DCDCiZeroReading,DCDCiZeroReading_curr);
+    amac->wrField(&AMACv2RegMap::DCDCiOffset     ,DCDCiOffset_curr     );
+    amac->wrField(&AMACv2RegMap::DCDCiP          ,DCDCiP_curr          );
+    amac->wrField(&AMACv2RegMap::DCDCiN          ,DCDCiN_curr          );
 
     return testSum;
   }
@@ -1074,17 +1074,17 @@ namespace PBv3TestTools
     std::shared_ptr<AMACv2> amac = tb->getPB(pbNum);
 
     // Store current state
-    uint32_t DCDCen_curr          =amac->rdField(&AMACv2Reg::DCDCen          );
-    uint32_t DCDCenC_curr         =amac->rdField(&AMACv2Reg::DCDCenC         );
+    uint32_t DCDCen_curr          =amac->rdField(&AMACv2RegMap::DCDCen          );
+    uint32_t DCDCenC_curr         =amac->rdField(&AMACv2RegMap::DCDCenC         );
 
-    uint32_t DCDCoZeroReading_curr=amac->rdField(&AMACv2Reg::DCDCoZeroReading);
-    uint32_t DCDCoOffset_curr     =amac->rdField(&AMACv2Reg::DCDCoOffset     );
-    uint32_t DCDCoP_curr          =amac->rdField(&AMACv2Reg::DCDCoP          );
-    uint32_t DCDCoN_curr          =amac->rdField(&AMACv2Reg::DCDCoN          );
+    uint32_t DCDCoZeroReading_curr=amac->rdField(&AMACv2RegMap::DCDCoZeroReading);
+    uint32_t DCDCoOffset_curr     =amac->rdField(&AMACv2RegMap::DCDCoOffset     );
+    uint32_t DCDCoP_curr          =amac->rdField(&AMACv2RegMap::DCDCoP          );
+    uint32_t DCDCoN_curr          =amac->rdField(&AMACv2RegMap::DCDCoN          );
 
     logger(logINFO) << " --> Turn on DCDC ...";
-    amac->wrField(&AMACv2::DCDCen , 0);
-    amac->wrField(&AMACv2::DCDCenC, 0);
+    amac->wrField(&AMACv2RegMap::DCDCen , 0);
+    amac->wrField(&AMACv2RegMap::DCDCenC, 0);
 
     logger(logINFO) << " --> Starting measurement ...";
     // Set sub-channel
@@ -1093,34 +1093,34 @@ namespace PBv3TestTools
 
     for(uint32_t DCDCoZeroReading=0;DCDCoZeroReading<2;DCDCoZeroReading++)
       {
-	amac->wrField(&AMACv2Reg::DCDCoZeroReading , DCDCoZeroReading);
+	amac->wrField(&AMACv2RegMap::DCDCoZeroReading , DCDCoZeroReading);
 	logger(logDEBUG) << "Set DCDCoZeroReading = " << DCDCoZeroReading;
 	for(uint32_t DCDCoOffset=0;DCDCoOffset<pow(2,4);DCDCoOffset++)
 	  {
-	    amac->wrField(&AMACv2Reg::DCDCoOffset, DCDCoOffset);
+	    amac->wrField(&AMACv2RegMap::DCDCoOffset, DCDCoOffset);
 	    logger(logDEBUG) << "Set DCDCoOffset = " << DCDCoOffset;
 	    for(uint32_t DCDCoP=0;DCDCoP<2;DCDCoP++)
 	      {
-		amac->wrField(&AMACv2Reg::DCDCoP, DCDCoP);
+		amac->wrField(&AMACv2RegMap::DCDCoP, DCDCoP);
 		logger(logDEBUG) << "Set DCDCoP = " << DCDCoP;
 		for(uint32_t DCDCoN=0;DCDCoN<2;DCDCoN++)
 		  {
-		    amac->wrField(&AMACv2Reg::DCDCoN, DCDCoN);
+		    amac->wrField(&AMACv2RegMap::DCDCoN, DCDCoN);
 		    logger(logDEBUG) << "Set DCDCoN = " << DCDCoN;
 
 		    for (uint32_t i=0; i<tests; i++)
 		      {
-			amac->wrField(&AMACv2::Ch13Mux, 0); //a
+			amac->wrField(&AMACv2RegMap::Ch13Mux, 0); //a
 			std::this_thread::sleep_for(std::chrono::milliseconds(2));
-			Cur1V = amac->rdField(&AMACv2::Ch13Value);
+			Cur1V = amac->rdField(&AMACv2RegMap::Ch13Value);
 
-			amac->wrField(&AMACv2::Ch13Mux, 1); //b
+			amac->wrField(&AMACv2RegMap::Ch13Mux, 1); //b
 			std::this_thread::sleep_for(std::chrono::milliseconds(2));
-			Cur1VTPL = amac->rdField(&AMACv2::Ch13Value);
+			Cur1VTPL = amac->rdField(&AMACv2RegMap::Ch13Value);
 
-			amac->wrField(&AMACv2::Ch13Mux, 2); //c
+			amac->wrField(&AMACv2RegMap::Ch13Mux, 2); //c
 			std::this_thread::sleep_for(std::chrono::milliseconds(2));
-			Cur1VTPH = amac->rdField(&AMACv2::Ch13Value);
+			Cur1VTPH = amac->rdField(&AMACv2RegMap::Ch13Value);
 
 			testSum["results"]["DCDCoZeroReading"][index] = DCDCoZeroReading;
 			testSum["results"]["DCDCoOffset"     ][index] = DCDCoOffset;
@@ -1140,12 +1140,12 @@ namespace PBv3TestTools
     testSum["results"]["TIMEEND"] = PBv3Utils::getTimeAsString(std::chrono::system_clock::now());
   
     // Revert to old state
-    amac->wrField(&AMACv2Reg::DCDCen          ,DCDCen_curr          );
-    amac->wrField(&AMACv2Reg::DCDCenC         ,DCDCenC_curr         );
-    amac->wrField(&AMACv2Reg::DCDCoZeroReading,DCDCoZeroReading_curr);
-    amac->wrField(&AMACv2Reg::DCDCoOffset     ,DCDCoOffset_curr     );
-    amac->wrField(&AMACv2Reg::DCDCoP          ,DCDCoP_curr          );
-    amac->wrField(&AMACv2Reg::DCDCoN          ,DCDCoN_curr          );
+    amac->wrField(&AMACv2RegMap::DCDCen          ,DCDCen_curr          );
+    amac->wrField(&AMACv2RegMap::DCDCenC         ,DCDCenC_curr         );
+    amac->wrField(&AMACv2RegMap::DCDCoZeroReading,DCDCoZeroReading_curr);
+    amac->wrField(&AMACv2RegMap::DCDCoOffset     ,DCDCoOffset_curr     );
+    amac->wrField(&AMACv2RegMap::DCDCoP          ,DCDCoP_curr          );
+    amac->wrField(&AMACv2RegMap::DCDCoN          ,DCDCoN_curr          );
 
     return testSum;
   }
@@ -1164,18 +1164,18 @@ namespace PBv3TestTools
     try
       {
       std::shared_ptr<AMACv2> amac = tb->getPB(pbNum);
-      testSum.merge_patch(PBv3TestTools::toggleOutputHelper(tb, pbNum, PBv3TB::VOUT  ,    1,    0, -0.10, 0.10, 1.4, 1.6, "Vout", &AMACv2::DCDCen, &AMACv2::DCDCenC));
-      testSum.merge_patch(PBv3TestTools::toggleOutputHelper(tb, pbNum, PBv3TB::OFout ,    1,    0, -0.10, 0.10, 1.0, 1.5, "OFout", &AMACv2::RstCntOF, &AMACv2::RstCntCOF));
-      testSum.merge_patch(PBv3TestTools::toggleOutputHelper(tb, pbNum, PBv3TB::SHUNTx, 0xFF, 0x00, -0.10, 0.30, 0.9, 1.3, "Shuntx", &AMACv2::DACShuntx));
-      testSum.merge_patch(PBv3TestTools::toggleOutputHelper(tb, pbNum, PBv3TB::SHUNTy, 0xFF, 0x00, -0.10, 0.30, 0.9, 1.3, "Shunty", &AMACv2::DACShunty));
-      testSum.merge_patch(PBv3TestTools::toggleOutputHelper(tb, pbNum, PBv3TB::CALx  , 0xFF, 0x00, -0.10, 0.10, 0.9, 1.3, "CALx", &AMACv2::DACCalx));
-      testSum.merge_patch(PBv3TestTools::toggleOutputHelper(tb, pbNum, PBv3TB::CALy  , 0xFF, 0x00, -0.10, 0.10, 0.9, 1.3, "CALy", &AMACv2::DACCALy));
-      testSum.merge_patch(PBv3TestTools::toggleOutputHelper(tb, pbNum, PBv3TB::LDx0EN,    0,    1, -0.01, 0.01, 1.0, 1.5, "LDx0EN", &AMACv2::CntSetHxLDO0en, &AMACv2::CntSetCHxLDO0en));
-      testSum.merge_patch(PBv3TestTools::toggleOutputHelper(tb, pbNum, PBv3TB::LDx1EN,    0,    1, -0.01, 0.01, 1.0, 1.5, "LDx1EN", &AMACv2::CntSetHxLDO1en, &AMACv2::CntSetCHxLDO1en));
-      testSum.merge_patch(PBv3TestTools::toggleOutputHelper(tb, pbNum, PBv3TB::LDx2EN,    0,    1, -0.01, 0.01, 1.0, 1.5, "LDx2EN", &AMACv2::CntSetHxLDO2en, &AMACv2::CntSetCHxLDO2en));
-      testSum.merge_patch(PBv3TestTools::toggleOutputHelper(tb, pbNum, PBv3TB::LDy0EN,    0,    1, -0.01, 0.01, 1.0, 1.5, "LDy0EN", &AMACv2::CntSetHyLDO0en, &AMACv2::CntSetCHyLDO0en));
-      testSum.merge_patch(PBv3TestTools::toggleOutputHelper(tb, pbNum, PBv3TB::LDy1EN,    0,    1, -0.01, 0.01, 1.0, 1.5, "LDy1EN", &AMACv2::CntSetHyLDO1en, &AMACv2::CntSetCHyLDO1en));
-      testSum.merge_patch(PBv3TestTools::toggleOutputHelper(tb, pbNum, PBv3TB::LDy2EN,    0,    1, -0.01, 0.01, 1.0, 1.5, "LDy2EN", &AMACv2::CntSetHyLDO2en, &AMACv2::CntSetCHyLDO2en));
+      testSum.merge_patch(PBv3TestTools::toggleOutputHelper(tb, pbNum, PBv3TB::VOUT  ,    1,    0, -0.10, 0.10, 1.4, 1.6, "Vout", &AMACv2RegMap::DCDCen, &AMACv2RegMap::DCDCenC));
+      testSum.merge_patch(PBv3TestTools::toggleOutputHelper(tb, pbNum, PBv3TB::OFout ,    1,    0, -0.10, 0.10, 1.0, 1.5, "OFout", &AMACv2RegMap::RstCntOF, &AMACv2RegMap::RstCntCOF));
+      testSum.merge_patch(PBv3TestTools::toggleOutputHelper(tb, pbNum, PBv3TB::SHUNTx, 0xFF, 0x00, -0.10, 0.30, 0.9, 1.3, "Shuntx", &AMACv2RegMap::DACShuntx));
+      testSum.merge_patch(PBv3TestTools::toggleOutputHelper(tb, pbNum, PBv3TB::SHUNTy, 0xFF, 0x00, -0.10, 0.30, 0.9, 1.3, "Shunty", &AMACv2RegMap::DACShunty));
+      testSum.merge_patch(PBv3TestTools::toggleOutputHelper(tb, pbNum, PBv3TB::CALx  , 0xFF, 0x00, -0.10, 0.10, 0.9, 1.3, "CALx", &AMACv2RegMap::DACCalx));
+      testSum.merge_patch(PBv3TestTools::toggleOutputHelper(tb, pbNum, PBv3TB::CALy  , 0xFF, 0x00, -0.10, 0.10, 0.9, 1.3, "CALy", &AMACv2RegMap::DACCALy));
+      testSum.merge_patch(PBv3TestTools::toggleOutputHelper(tb, pbNum, PBv3TB::LDx0EN,    0,    1, -0.01, 0.01, 1.0, 1.5, "LDx0EN", &AMACv2RegMap::CntSetHxLDO0en, &AMACv2RegMap::CntSetCHxLDO0en));
+      testSum.merge_patch(PBv3TestTools::toggleOutputHelper(tb, pbNum, PBv3TB::LDx1EN,    0,    1, -0.01, 0.01, 1.0, 1.5, "LDx1EN", &AMACv2RegMap::CntSetHxLDO1en, &AMACv2RegMap::CntSetCHxLDO1en));
+      testSum.merge_patch(PBv3TestTools::toggleOutputHelper(tb, pbNum, PBv3TB::LDx2EN,    0,    1, -0.01, 0.01, 1.0, 1.5, "LDx2EN", &AMACv2RegMap::CntSetHxLDO2en, &AMACv2RegMap::CntSetCHxLDO2en));
+      testSum.merge_patch(PBv3TestTools::toggleOutputHelper(tb, pbNum, PBv3TB::LDy0EN,    0,    1, -0.01, 0.01, 1.0, 1.5, "LDy0EN", &AMACv2RegMap::CntSetHyLDO0en, &AMACv2RegMap::CntSetCHyLDO0en));
+      testSum.merge_patch(PBv3TestTools::toggleOutputHelper(tb, pbNum, PBv3TB::LDy1EN,    0,    1, -0.01, 0.01, 1.0, 1.5, "LDy1EN", &AMACv2RegMap::CntSetHyLDO1en, &AMACv2RegMap::CntSetCHyLDO1en));
+      testSum.merge_patch(PBv3TestTools::toggleOutputHelper(tb, pbNum, PBv3TB::LDy2EN,    0,    1, -0.01, 0.01, 1.0, 1.5, "LDy2EN", &AMACv2RegMap::CntSetHyLDO2en, &AMACv2RegMap::CntSetCHyLDO2en));
 
 
     testSum["results"]["TIMEEND"] = PBv3Utils::getTimeAsString(std::chrono::system_clock::now());
@@ -1190,7 +1190,7 @@ namespace PBv3TestTools
     return testSum;
   }
 
-  json toggleOutputHelper(std::shared_ptr<PBv3TB> tb, uint32_t pbNum, PBv3TB::CARRIER_OUTPUT muxCh, uint32_t on, uint32_t off, double offLowThresh, double offHighThresh, double onLowThresh, double onHighThresh, const std::string outString, AMACv2Field AMACv2Reg::* amacCh, AMACv2Field AMACv2Reg::* amacChCopy)
+  json toggleOutputHelper(std::shared_ptr<PBv3TB> tb, uint32_t pbNum, PBv3TB::CARRIER_OUTPUT muxCh, uint32_t on, uint32_t off, double offLowThresh, double offHighThresh, double onLowThresh, double onHighThresh, const std::string outString, AMACv2Field AMACv2RegMap::* amacCh, AMACv2Field AMACv2RegMap::* amacChCopy)
   { 
     double offValue = 0;
     double onValue = 0;
@@ -1301,7 +1301,7 @@ namespace PBv3TestTools
     testSum["results"]["TIMESTART"] = PBv3Utils::getTimeAsString(std::chrono::system_clock::now());
     testSum["passed"] = true;
 
-    uint32_t CTAToffset_curr=amac->rdField(&AMACv2Reg::CTAToffset);
+    uint32_t CTAToffset_curr=amac->rdField(&AMACv2RegMap::CTAToffset);
 
     std::cout << "AMACCTAT" << "\t" << "AMACNTCX" << "\t" << "AMACNTCY" << "\t" << "AMACNTCPB" << "\t" << "AMACPTAT" << "\t" << "CTAToffset" << std::endl;
 
@@ -1310,14 +1310,14 @@ namespace PBv3TestTools
 	CTAToffset_set<((scanSettings)?16:(CTAToffset_curr+1));
 	CTAToffset_set++)
       {
-	amac->wrField(&AMACv2Reg::CTAToffset, CTAToffset_set);
+	amac->wrField(&AMACv2RegMap::CTAToffset, CTAToffset_set);
 	std::this_thread::sleep_for(std::chrono::milliseconds(100));
 
-	uint32_t CTAT  = amac->rdField(&AMACv2::Ch6Value);
-	uint32_t NTCx  = amac->rdField(&AMACv2::Ch7Value);
-	uint32_t NTCy  = amac->rdField(&AMACv2::Ch8Value);
-	uint32_t NTCpb = amac->rdField(&AMACv2::Ch9Value);
-	uint32_t PTAT  = amac->rdField(&AMACv2::Ch15Value);
+	uint32_t CTAT  = amac->rdField(&AMACv2RegMap::Ch6Value);
+	uint32_t NTCx  = amac->rdField(&AMACv2RegMap::Ch7Value);
+	uint32_t NTCy  = amac->rdField(&AMACv2RegMap::Ch8Value);
+	uint32_t NTCpb = amac->rdField(&AMACv2RegMap::Ch9Value);
+	uint32_t PTAT  = amac->rdField(&AMACv2RegMap::Ch15Value);
 
 	testSum["results"]["AMACCTAT"   ][index]=CTAT;
 	testSum["results"]["AMACNTCX"   ][index]=NTCx;
@@ -1335,7 +1335,7 @@ namespace PBv3TestTools
     testSum["results"]["TIMEEND"] = PBv3Utils::getTimeAsString(std::chrono::system_clock::now());
 
     // Revert to old state
-    amac->wrField(&AMACv2Reg::CTAToffset, CTAToffset_curr );
+    amac->wrField(&AMACv2RegMap::CTAToffset, CTAToffset_curr );
 
     return testSum;
   }
@@ -1349,34 +1349,34 @@ namespace PBv3TestTools
     testSum["passed"] = true;
 
     uint32_t nSEU=0;
-    for(const std::pair<uint32_t, rw_t>& reg : AMACv2Reg::Registers)
+    for(const AMACv2Register* reg : amac->getRegisters())
       {
-	if(reg.second!=RW)
+	if(reg->isRW()!=RW)
 	  continue;
 
-	uint32_t expval=amac->getReg(reg.first);
-	uint32_t curval=amac->read_reg(reg.first);
+	uint32_t expval=reg->getValue();
+	uint32_t curval=amac->read_reg(reg->getAddress());
 
-	testSum["results"]["reg"+std::to_string(reg.first)+"value"]=curval;
-	testSum["results"]["reg"+std::to_string(reg.first)+"expec"]=expval;
+	testSum["results"]["reg"+std::to_string(reg->getAddress())+"value"]=curval;
+	testSum["results"]["reg"+std::to_string(reg->getAddress())+"expec"]=expval;
 
 	if(expval!=curval)
 	  { // There was an SEU
 	    ++nSEU;
 
 	    std::stringstream ss;
-	    ss << "SEU in register " << reg.first << ": ";
+	    ss << "SEU in register " << reg->getAddress() << ": ";
 	    ss << "0x" << std::hex << std::setw(8) << std::setfill('0') << curval << std::dec;
 	    ss << " (expected 0x" << std::hex << std::setw(8) << std::setfill('0') << expval << std::dec << ")";
 	    logger(logINFO) << ss.str();
 
 	    // Correct
-	    amac->write_reg(reg.first, expval);
-	    uint32_t curval2=amac->read_reg(reg.first);
+	    amac->write_reg(reg->getAddress(), expval);
+	    uint32_t curval2=amac->read_reg(reg->getAddress());
 	    if(curval2==expval)
 	      {
 		std::stringstream ss;
-		ss << "Found an unrecoverable SEU in register " << reg.first << ": ";
+		ss << "Found an unrecoverable SEU in register " << reg->getAddress() << ": ";
 		ss << "0x" << std::hex << std::setw(8) << std::setfill('0') << curval << std::dec;
 		ss << " (expected 0x" << std::hex << std::setw(8) << std::setfill('0') << expval << std::dec << ")";
 		throw std::runtime_error(ss.str());
diff --git a/pbv3/PBv3TestTools.h b/pbv3/PBv3TestTools.h
index 57dd715b..128c73eb 100644
--- a/pbv3/PBv3TestTools.h
+++ b/pbv3/PBv3TestTools.h
@@ -201,7 +201,7 @@ namespace PBv3TestTools
    *
    * \return json object with test results
    */
-  json toggleOutputHelper(std::shared_ptr<PBv3TB> tb, uint32_t pbNum, PBv3TB::CARRIER_OUTPUT muxCh, uint32_t on, uint32_t off, double offLowThresh, double offHighThresh, double onLowThresh, double onHighThresh, std::string outString, AMACv2Field AMACv2Reg::* amacCh, AMACv2Field AMACv2Reg::* amacChCopy=nullptr);
+  json toggleOutputHelper(std::shared_ptr<PBv3TB> tb, uint32_t pbNum, PBv3TB::CARRIER_OUTPUT muxCh, uint32_t on, uint32_t off, double offLowThresh, double offHighThresh, double onLowThresh, double onHighThresh, std::string outString, AMACv2Field AMACv2RegMap::* amacCh, AMACv2Field AMACv2RegMap::* amacChCopy=nullptr);
 
   /** \name HV tests
    * @{ */
diff --git a/pbv3/tools/pbv3_active_fancy_load.cpp b/pbv3/tools/pbv3_active_fancy_load.cpp
index 06e11c0e..5537fece 100644
--- a/pbv3/tools/pbv3_active_fancy_load.cpp
+++ b/pbv3/tools/pbv3_active_fancy_load.cpp
@@ -38,10 +38,10 @@ json measureEfficiency(std::shared_ptr<AMACv2> amac, std::shared_ptr<PowerSupply
     testSum["passed"] = true;
 
     // Store current state
-    uint32_t DCDCen_curr =amac->rdField(&AMACv2Reg::DCDCen );
-    uint32_t DCDCenC_curr=amac->rdField(&AMACv2Reg::DCDCenC);
-    uint32_t Ch12Mux_curr=amac->rdField(&AMACv2Reg::Ch12Mux);
-    uint32_t Ch13Mux_curr=amac->rdField(&AMACv2Reg::Ch13Mux);
+    uint32_t DCDCen_curr =amac->rdField(&AMACv2RegMap::DCDCen );
+    uint32_t DCDCenC_curr=amac->rdField(&AMACv2RegMap::DCDCenC);
+    uint32_t Ch12Mux_curr=amac->rdField(&AMACv2RegMap::Ch12Mux);
+    uint32_t Ch13Mux_curr=amac->rdField(&AMACv2RegMap::Ch13Mux);
 
     //
     // Initialize
@@ -149,10 +149,10 @@ json measureEfficiency(std::shared_ptr<AMACv2> amac, std::shared_ptr<PowerSupply
     load->turnOff();
 
     // Revert to old state
-    amac->wrField(&AMACv2Reg::DCDCen , DCDCen_curr );
-    amac->wrField(&AMACv2Reg::DCDCenC, DCDCenC_curr);
-    amac->wrField(&AMACv2Reg::Ch12Mux, Ch12Mux_curr);
-    amac->wrField(&AMACv2Reg::Ch13Mux, Ch13Mux_curr);
+    amac->wrField(&AMACv2RegMap::DCDCen , DCDCen_curr );
+    amac->wrField(&AMACv2RegMap::DCDCenC, DCDCenC_curr);
+    amac->wrField(&AMACv2RegMap::Ch12Mux, Ch12Mux_curr);
+    amac->wrField(&AMACv2RegMap::Ch13Mux, Ch13Mux_curr);
 
     testSum["results"]["TIMEEND"] = PBv3Utils::getTimeAsString(std::chrono::system_clock::now());
 
diff --git a/pbv3/tools/pbv3_field.cpp b/pbv3/tools/pbv3_field.cpp
index 9d04bfd5..11a23ea7 100644
--- a/pbv3/tools/pbv3_field.cpp
+++ b/pbv3/tools/pbv3_field.cpp
@@ -108,7 +108,7 @@ int main(int argc, char* argv[])
   if (command == "list")
     {
       for(const AMACv2Field* field : amac->getFields())
-	std::cout << field->getFieldName() << std::endl;
+	std::cout << field->getName() << std::endl;
     }
   else if (command == "read")
     {
diff --git a/pbv3/tools/pbv3_print_status.cpp b/pbv3/tools/pbv3_print_status.cpp
index 018ac578..56343f88 100644
--- a/pbv3/tools/pbv3_print_status.cpp
+++ b/pbv3/tools/pbv3_print_status.cpp
@@ -25,7 +25,7 @@ std::string equipConfigFile = "config/equip_testbench.json";
 //---------------
 
 //------ Channel Map
-std::map<std::string,AMACv2Field AMACv2Reg::*> channelmap={
+std::map<std::string,AMACv2Field AMACv2RegMap::*> channelmap={
   {"VDCDC"       ,&AMACv2::Ch0Value},
   {"VDDLR"       ,&AMACv2::Ch1Value},
   {"DCDCin"      ,&AMACv2::Ch2Value},
@@ -56,7 +56,7 @@ std::map<std::string,AMACv2Field AMACv2Reg::*> channelmap={
   {"PTAT"        ,&AMACv2::Ch15Value},
 };
 
-std::map<std::string,std::pair<AMACv2Field AMACv2Reg::*, uint32_t> > muxmap={
+std::map<std::string,std::pair<AMACv2Field AMACv2RegMap::*, uint32_t> > muxmap={
   {"VDDREG"      ,{&AMACv2::Ch3Mux ,0}},
   {"sysBG"       ,{&AMACv2::Ch3Mux ,1}},
   {"AM900BG"     ,{&AMACv2::Ch3Mux ,2}},
diff --git a/pbv3/tools/pbv3_readADC.cpp b/pbv3/tools/pbv3_readADC.cpp
index 398228fe..ac0cb08c 100644
--- a/pbv3/tools/pbv3_readADC.cpp
+++ b/pbv3/tools/pbv3_readADC.cpp
@@ -23,7 +23,7 @@ std::string equipConfigFile = "config/equip_testbench.json";
 //---------------
 
 //------ Channel Map
-std::map<std::string,AMACv2Field AMACv2Reg::*> channelmap={
+std::map<std::string, AMACv2Field AMACv2RegMap::*> channelmap={
   {"VDCDC"       ,&AMACv2::Ch0Value},
   {"VDDLR"       ,&AMACv2::Ch1Value},
   {"DCDCin"      ,&AMACv2::Ch2Value},
@@ -54,7 +54,7 @@ std::map<std::string,AMACv2Field AMACv2Reg::*> channelmap={
   {"PTAT"        ,&AMACv2::Ch15Value},
 };
 
-std::map<std::string,std::pair<AMACv2Field AMACv2Reg::*, uint32_t> > muxmap={
+std::map<std::string,std::pair<AMACv2Field AMACv2RegMap::*, uint32_t> > muxmap={
   {"VDDREG"      ,{&AMACv2::Ch3Mux ,0}},
   {"sysBG"       ,{&AMACv2::Ch3Mux ,1}},
   {"AM900BG"     ,{&AMACv2::Ch3Mux ,2}},
@@ -79,7 +79,7 @@ void usage(char* argv[])
 {
   std::cerr << "Usage: " << argv[0] << " [options] channel" << std::endl;
   std::cerr << "Channel can be either number or one of the following. a name.:" << std::endl;
-  for(const std::pair<std::string,AMACv2Field AMACv2Reg::*>& kv : channelmap)
+  for(const std::pair<std::string,AMACv2Field AMACv2RegMap::*>& kv : channelmap)
     std::cerr << "  " << kv.first << std::endl;
   std::cerr << std::endl;
   std::cerr << "List of options:" << std::endl;
@@ -159,7 +159,7 @@ int main(int argc, char* argv[])
 
   //
   // Perform the read of the ADC
-  AMACv2Field AMACv2Reg::* ch;
+  AMACv2Field AMACv2RegMap::* ch;
 
   // try channel number
   try
-- 
GitLab


From 6848cd015351b83b9546c6ca15e5ed3be1f899cd Mon Sep 17 00:00:00 2001
From: Berkeley Strippers <strips@lbl>
Date: Tue, 25 Aug 2020 18:48:00 -0700
Subject: [PATCH 19/29] monitor.C: Use ABC channel ID instead of pad ID to
 identify chip.

---
 itsdaq/monitor.C | 9 +++++----
 1 file changed, 5 insertions(+), 4 deletions(-)

diff --git a/itsdaq/monitor.C b/itsdaq/monitor.C
index 6a003fb8..8fc16f16 100644
--- a/itsdaq/monitor.C
+++ b/itsdaq/monitor.C
@@ -1,5 +1,3 @@
-//#include "macros/pedestal.cpp"
-
 #include <chrono>
 #include <unordered_map>
 #include <vector>
@@ -154,7 +152,10 @@ public:
 	    StarChipPacket p(false);
 	    p.add_word(0x13c);
 	    for(uint8_t byte : packet)
-	      p.add_word(byte);
+	      {
+		p.add_word(byte);
+		//std::cout << "0x" << std::hex << std::setw(2) << std::setfill('0') << (uint32_t)byte << std::dec << std::endl;
+	      }
 	    p.add_word(0x1dc);
 	    p.parse();
 
@@ -170,7 +171,7 @@ public:
 		continue;
 	      }
 
-	    uint32_t abc_index=(p.abc_status>>12)&0xF;
+	    uint32_t abc_index=p.channel_abc; //(p.abc_status>>12)&0xF;
 	    if(!br_abcregs[n][abc_index])
 	      {
 		std::cerr << "ERROR! Invalid ABC index: " << (uint32_t) p.channel_abc << std::endl;
-- 
GitLab


From 8d6fdab0d339cee4c7e331ddbf11d7a99d3afb0f Mon Sep 17 00:00:00 2001
From: Berkeley Strippers <strips@lbl>
Date: Tue, 25 Aug 2020 20:54:17 -0700
Subject: [PATCH 20/29] Add stream capture dump to monitor.

---
 itsdaq/monitor.C | 99 ++++++++++++++++++++++++++++++++++++++++++++++--
 1 file changed, 96 insertions(+), 3 deletions(-)

diff --git a/itsdaq/monitor.C b/itsdaq/monitor.C
index 8fc16f16..6fddcd16 100644
--- a/itsdaq/monitor.C
+++ b/itsdaq/monitor.C
@@ -22,13 +22,15 @@ public:
 	m_registerValuesErr[kv.first]=true;
       }
   }
-  
+
   void createBranches(TTree *t, const std::string& prefix)
   {
     for(const std::pair<int, std::string>& kv : m_registerMap)
       {
-	t->Branch((prefix+"_"+kv.second       ).c_str(), &m_registerValues   [kv.first]);
-	t->Branch((prefix+"_"+kv.second+"_err").c_str(), &m_registerValuesErr[kv.first]);
+	std::string branch_prefix=prefix+"_"+kv.second;
+
+	t->Branch((branch_prefix       ).c_str(), &m_registerValues   [kv.first]);
+	t->Branch((branch_prefix+"_err").c_str(), &m_registerValuesErr[kv.first]);
       }
   }
 
@@ -50,6 +52,68 @@ private:
   std::unordered_map<int, uint8_t > m_registerValuesErr;
 };
 
+/**
+ * Capture stream dump
+ */
+class RegisterReadStreamCaptureDump
+{
+private:
+  static const uint32_t MAX_STREAMCAPTURE=1024;
+
+public:
+  RegisterReadStreamCaptureDump(const std::unordered_map<int, std::string>& registerMap)
+    : m_registerMap(registerMap)
+  {
+    // Value holders
+    for(const std::pair<int, std::string>& kv : m_registerMap)
+      {
+	m_streamCaptureSize[kv.first]=0;
+	m_streamCapture    [kv.first]=new uint8_t[MAX_STREAMCAPTURE];
+      }
+  }
+
+  ~RegisterReadStreamCaptureDump()
+  {
+    for(const std::pair<int, uint8_t*> kv : m_streamCapture)
+      delete[] kv.second;
+  }
+
+  void createBranches(TTree *t, const std::string& prefix)
+  {
+    for(const std::pair<int, std::string>& kv : m_registerMap)
+      {
+	std::string branch_prefix=prefix+"_"+kv.second;
+
+	t->Branch((branch_prefix+"_capsize").c_str(), &m_streamCaptureSize[kv.first]);
+	t->Branch((branch_prefix+"_cap").c_str(), m_streamCapture[kv.first], (branch_prefix+"_cap["+branch_prefix+"_capsize]/b").c_str());
+      }
+  }
+
+  void resetValue(int reg)
+  {
+    m_streamCaptureSize[reg]=0;
+  }
+
+  void setValueByte(int reg, uint32_t idx, uint8_t value)
+  {
+    if(idx>MAX_STREAMCAPTURE)
+      {
+	std::cerr << "ERROR: RegisterReadStreamCaptureDump::setValueByte with idx " << idx << " > MAX_STREAMCAPTURE " << MAX_STREAMCAPTURE << std::endl;
+	return;
+      }
+
+    if(m_streamCaptureSize[reg]<=idx)
+      m_streamCaptureSize[reg]=idx+1; // resize
+
+    m_streamCapture[reg][idx]=value;
+  }
+
+private:
+  std::unordered_map<int, std::string> m_registerMap;
+  std::unordered_map<int, uint32_t > m_streamCaptureSize;
+  std::unordered_map<int, uint8_t* > m_streamCapture;
+};
+
 /**
  * Reads all registers from HCC + ABC and dumps them to a
  * TTree.
@@ -101,6 +165,7 @@ public:
 	// Find packets in streams
 	std::vector<std::vector<uint8_t>> packets;
 	find_hcc_packets(n, packets);
+	save_capture_stream(n, kv.first, br_hcccap[n]);
 
 	// Decode packets
 	for(const std::vector<uint8_t>& packet : packets)
@@ -145,6 +210,7 @@ public:
 	// Find packets in streams
 	std::vector<std::vector<uint8_t>> packets;
 	find_hcc_packets(n, packets);
+	save_capture_stream(n, kv.first, br_abccap[n]);
 
 	// Decode packets
 	for(const std::vector<uint8_t>& packet : packets)
@@ -183,6 +249,24 @@ public:
       }
   }
 
+  void save_capture_stream(int module_id, int reg, std::shared_ptr<RegisterReadStreamCaptureDump> br)
+  {
+    br->resetValue(reg);
+
+    int l = 0; // "link" 1 should be empty
+    int burst = m_e->burst_count;
+    int scan_width = e->m[module_id]->scan_size(burst, l);
+
+    uint8_t byte;
+    for(int b=0; b<scan_width; b++)
+      {
+	int bit = m_e->m[module_id]->scan_lookup(burst, l, b);
+	byte=(byte<<1)|(bit&0x1);
+	if((b%8)==7)
+	  br->setValueByte(reg, (b-7)/8, byte);
+      }
+  }
+
   bool find_hcc_packets(int module_id, std::vector<std::vector<uint8_t>>& result)
   {
     result.clear();
@@ -294,6 +378,8 @@ private:
   TTree *m_tree=nullptr;
   std::unordered_map<int, std::shared_ptr<RegisterDump>> br_hccregs;
   std::unordered_map<int, std::vector<std::shared_ptr<RegisterDump>>> br_abcregs;
+  std::unordered_map<int, std::shared_ptr<RegisterReadStreamCaptureDump>> br_hcccap;
+  std::unordered_map<int, std::shared_ptr<RegisterReadStreamCaptureDump>> br_abccap;
   uint32_t br_timestamp;
 
   // Register map
@@ -320,6 +406,9 @@ private:
 	    br_hccregs[n]->createBranches(m_tree, "Mod"+std::to_string(n)+"_HCC");
 	  }
 
+	br_hcccap[n]=std::make_shared<RegisterReadStreamCaptureDump>(hcc_regs);
+	br_hcccap[n]->createBranches(m_tree, "Mod"+std::to_string(n)+"_HCC");
+
 	// ABC Registers
 	bool v1=get_chipset()==9;
 	const std::unordered_map<int, std::string>& abc_regs=(v1)?(abcv1_regs):(abcv0_regs);
@@ -330,6 +419,9 @@ private:
 	    abcdumps[a]->createBranches(m_tree, "Mod"+std::to_string(n)+"_ABC"+std::to_string(a));
 	  }
 	br_abcregs[n]=abcdumps;
+
+	br_abccap[n]=std::make_shared<RegisterReadStreamCaptureDump>(abc_regs);
+	br_abccap[n]->createBranches(m_tree, "Mod"+std::to_string(n)+"_ABC");
       }
   }
 
@@ -442,6 +534,7 @@ void monitor()
 	  d.run();
       
 	  sleep(1);
+	  //return 1;
 	}
     }
 }
-- 
GitLab


From 1a808bdf4f0547ccc7936fec8e89e25286bb3768 Mon Sep 17 00:00:00 2001
From: Berkeley Strippers <strips@lbl>
Date: Thu, 27 Aug 2020 14:42:55 -0700
Subject: [PATCH 21/29] Update monitor.C

---
 itsdaq/monitor.C | 423 +++++++++++------------------------------------
 1 file changed, 100 insertions(+), 323 deletions(-)

diff --git a/itsdaq/monitor.C b/itsdaq/monitor.C
index 6fddcd16..ed76e547 100644
--- a/itsdaq/monitor.C
+++ b/itsdaq/monitor.C
@@ -6,52 +6,6 @@
 #include <TFile.h>
 #include <TTree.h>
 
-/**
- * Register map and values for a given chip
- */
-class RegisterDump
-{
-public:
-  RegisterDump(const std::unordered_map<int, std::string>& registerMap)
-    : m_registerMap(registerMap)
-  {
-    // Value holders
-    for(const std::pair<int, std::string>& kv : m_registerMap)
-      {
-	m_registerValues   [kv.first]=0;
-	m_registerValuesErr[kv.first]=true;
-      }
-  }
-
-  void createBranches(TTree *t, const std::string& prefix)
-  {
-    for(const std::pair<int, std::string>& kv : m_registerMap)
-      {
-	std::string branch_prefix=prefix+"_"+kv.second;
-
-	t->Branch((branch_prefix       ).c_str(), &m_registerValues   [kv.first]);
-	t->Branch((branch_prefix+"_err").c_str(), &m_registerValuesErr[kv.first]);
-      }
-  }
-
-  void resetValue(int reg)
-  {
-    m_registerValues   [reg]=0x0;
-    m_registerValuesErr[reg]=true;
-  }
-
-  void setValue(int reg, uint32_t value)
-  {
-    m_registerValues   [reg]=value;
-    m_registerValuesErr[reg]=false;
-  }
-
-private:
-  std::unordered_map<int, std::string> m_registerMap;
-  std::unordered_map<int, uint32_t> m_registerValues;
-  std::unordered_map<int, uint8_t > m_registerValuesErr;
-};
-
 /**
  * Capture stream dump
  */
@@ -61,57 +15,77 @@ private:
   static const uint32_t MAX_STREAMCAPTURE=1024;
 
 public:
-  RegisterReadStreamCaptureDump(const std::unordered_map<int, std::string>& registerMap)
-    : m_registerMap(registerMap)
+  RegisterReadStreamCaptureDump()
   {
     // Value holders
-    for(const std::pair<int, std::string>& kv : m_registerMap)
-      {
-	m_streamCaptureSize[kv.first]=0;
-	m_streamCapture    [kv.first]=new uint8_t[MAX_STREAMCAPTURE];
-      }
+    m_timestamp        =0;
+    m_module           =0;
+    m_reg              =0;
+    m_streamCaptureSize=0;
+    m_streamCapture    =new uint8_t[MAX_STREAMCAPTURE];
+
+    // TTree
+    m_tree=new TTree("registerread", "");
+
+    m_tree->Branch("timestamp", &m_timestamp        );
+    m_tree->Branch("module"   , &m_module           );
+    m_tree->Branch("reg"      , &m_reg              );
+    m_tree->Branch("capsize"  , &m_streamCaptureSize);
+    m_tree->Branch("cap"      , m_streamCapture     , "cap[capsize]/b");
   }
 
   ~RegisterReadStreamCaptureDump()
   {
-    for(const std::pair<int, uint8_t*> kv : m_streamCapture)
-      delete[] kv.second;
+    delete[] m_streamCapture;
   }
 
-  void createBranches(TTree *t, const std::string& prefix)
+  TTree* tree()
+  { return m_tree; }
+
+  void fillValue(uint32_t timestamp, uint32_t module_id, int reg, TModule* mod, uint32_t burst, uint32_t link)
   {
-    for(const std::pair<int, std::string>& kv : m_registerMap)
+    // Common branches
+    m_timestamp=timestamp;
+    m_module=module_id;
+    m_reg=reg;
+
+    // Check size
+    int scan_width = mod->scan_size(burst, link);
+    m_streamCaptureSize=scan_width/8;
+    if((m_streamCaptureSize/8)>MAX_STREAMCAPTURE)
       {
-	std::string branch_prefix=prefix+"_"+kv.second;
-
-	t->Branch((branch_prefix+"_capsize").c_str(), &m_streamCaptureSize[kv.first]);
-	t->Branch((branch_prefix+"_cap").c_str(), m_streamCapture[kv.first], (branch_prefix+"_cap["+branch_prefix+"_capsize]/b").c_str());
+	std::cerr << "WARNING: RegisterReadStreamCaptureDump::fullValue with scan_width/8 " << scan_width/8 << " > MAX_STREAMCAPTURE " << MAX_STREAMCAPTURE << std::endl;
+	m_streamCaptureSize=MAX_STREAMCAPTURE;
       }
-  }
-
-  void resetValue(int reg)
-  {
-    m_streamCaptureSize[reg]=0;
-  }
 
-  void setValueByte(int reg, uint32_t idx, uint8_t value)
-  {
-    if(idx>MAX_STREAMCAPTURE)
+    // The capture stream
+    uint8_t byte;
+    for(int b=0; b<std::min<int>(scan_width, 8*MAX_STREAMCAPTURE); b++)
       {
-	std::cerr << "ERROR: RegisterReadStreamCaptureDump::setValueByte with idx " << idx << " > MAX_STREAMCAPTURE " << MAX_STREAMCAPTURE << std::endl;
-	return;
+	int bit = mod->scan_lookup(burst, link, b);
+	byte=(byte<<1)|(bit&0x1);
+	if((b%8)==7)
+	  m_streamCapture[(b-7)/8]=byte;
       }
 
-    if(m_streamCaptureSize[reg]<=idx)
-      m_streamCaptureSize[reg]=idx+1; // resize
+    /*
+    for(uint32_t i=0; i< m_streamCaptureSize; i++)
+      std::cout << std::hex << std::setw(2) << std::setfill('0') << (uint32_t)m_streamCapture[i] << std::dec << std::endl;
+    */
 
-    m_streamCapture[reg][idx]=value;
+    m_tree->Fill();
   }
 
 private:
-  std::unordered_map<int, std::string> m_registerMap;
-  std::unordered_map<int, uint32_t > m_streamCaptureSize;
-  std::unordered_map<int, uint8_t* > m_streamCapture;
+  // kTreeStructures
+  TTree *m_tree=nullptr;
+
+  // Branches
+  uint32_t m_timestamp;
+  uint32_t m_module;
+  int m_reg;
+  uint32_t m_streamCaptureSize;
+  uint8_t* m_streamCapture;
 };
 
 /**
@@ -125,18 +99,22 @@ public:
     : m_e(e)
   {
     m_fh=TFile::Open(outputpath.c_str(), "RECREATE");
-    createTree();
+    m_regdump=std::make_shared<RegisterReadStreamCaptureDump>();    
   }
 
   ~RegisterDumper()
   {
-    m_tree->Write();
+    m_regdump->tree()->Write();
     m_fh->Close();
+
+    std::string output=m_fh->GetPath();
+    output.pop_back(); output.pop_back(); // Remove ":/"
+    std::cout << "Registers dumped to: " << output << std::endl;
   }
 
   void run()
   {
-    br_timestamp = std::chrono::duration_cast<std::chrono::seconds>((std::chrono::system_clock::now().time_since_epoch())).count();
+    m_timestamp = std::chrono::duration_cast<std::chrono::seconds>((std::chrono::system_clock::now().time_since_epoch())).count();
 
     bool hccFormat=m_e->HccPresent();
     for (int n=0; n<m_e->GetMaxModules(); ++n)
@@ -148,9 +126,6 @@ public:
 
 	// Peform ABC register read
 	run_abc_registers(n);
-
-	// Fill tree
-	m_tree->Fill();
       }
   }
 
@@ -158,39 +133,9 @@ public:
   {
     for(const std::pair<int, std::string>& kv : hcc_regs)
       {
-	br_hccregs[n]->resetValue(kv.first);
-
 	m_e->ReadChipRegister(kv.first+256);
 
-	// Find packets in streams
-	std::vector<std::vector<uint8_t>> packets;
-	find_hcc_packets(n, packets);
-	save_capture_stream(n, kv.first, br_hcccap[n]);
-
-	// Decode packets
-	for(const std::vector<uint8_t>& packet : packets)
-	  {
-	    StarChipPacket p(false);
-	    p.add_word(0x13c);
-	    for(uint8_t byte : packet)
-	      p.add_word(byte);
-	    p.add_word(0x1dc);
-	    p.parse();
-
-	    if(p.type!=TYP_HCC_RR)
-	      {
-		std::cerr << "WARNING! Unexpected packet type: " << packet_type_names[p.type] << std::endl;
-		continue;
-	      }
-
-	    if(p.address!=kv.first)
-	      {
-		std::cerr << "ERROR! Wrong address: " << (uint32_t)p.address << "(expected " << (uint32_t)kv.first << ")" << std::endl;
-		continue;
-	      }
-
-	    br_hccregs[n]->setValue(kv.first, p.value);
-	  }
+	m_regdump->fillValue(m_timestamp, n, kv.first+256, e->m[n], m_e->burst_count, 0);
       }
   }
 
@@ -202,229 +147,26 @@ public:
     const std::unordered_map<int, std::string>& abc_regs=(v1)?(abcv1_regs):(abcv0_regs);
     for(const std::pair<int, std::string>& kv : abc_regs)
       {
-	for(int a=0; a<m_e->GetNChips(); ++a)
-	  br_abcregs[n][a]->resetValue(kv.first);
-
 	m_e->ReadChipRegister(kv.first);
 
-	// Find packets in streams
-	std::vector<std::vector<uint8_t>> packets;
-	find_hcc_packets(n, packets);
-	save_capture_stream(n, kv.first, br_abccap[n]);
-
-	// Decode packets
-	for(const std::vector<uint8_t>& packet : packets)
-	  {
-	    StarChipPacket p(false);
-	    p.add_word(0x13c);
-	    for(uint8_t byte : packet)
-	      {
-		p.add_word(byte);
-		//std::cout << "0x" << std::hex << std::setw(2) << std::setfill('0') << (uint32_t)byte << std::dec << std::endl;
-	      }
-	    p.add_word(0x1dc);
-	    p.parse();
-
-	    if(p.type!=TYP_ABC_RR)
-	      {
-		std::cerr << "WARNING! Unexpected packet type: " << packet_type_names[p.type] << std::endl;
-		continue;
-	      }
-
-	    if(p.address!=kv.first)
-	      {
-		std::cerr << "ERROR! Wrong address: " << (uint32_t)p.address << "(expected " << (uint32_t)kv.first << ")" << std::endl;
-		continue;
-	      }
-
-	    uint32_t abc_index=p.channel_abc; //(p.abc_status>>12)&0xF;
-	    if(!br_abcregs[n][abc_index])
-	      {
-		std::cerr << "ERROR! Invalid ABC index: " << (uint32_t) p.channel_abc << std::endl;
-		continue;
-	      }
-
-	    br_abcregs[n][abc_index]->setValue(kv.first, p.value);
-	  }
+	m_regdump->fillValue(m_timestamp, n, kv.first, e->m[n], m_e->burst_count, 0);
       }
   }
 
-  void save_capture_stream(int module_id, int reg, std::shared_ptr<RegisterReadStreamCaptureDump> br)
-  {
-    br->resetValue(reg);
-
-    int l = 0; // "link" 1 should be empty
-    int burst = m_e->burst_count;
-    int scan_width = e->m[module_id]->scan_size(burst, l);
-
-    uint8_t byte;
-    for(int b=0; b<scan_width; b++)
-      {
-	int bit = m_e->m[module_id]->scan_lookup(burst, l, b);
-	byte=(byte<<1)|(bit&0x1);
-	if((b%8)==7)
-	  br->setValueByte(reg, (b-7)/8, byte);
-      }
-  }
-
-  bool find_hcc_packets(int module_id, std::vector<std::vector<uint8_t>>& result)
-  {
-    result.clear();
-
-    int l = 0; // "link" 1 should be empty
-    int burst = m_e->burst_count;
-    int scan_width = e->m[module_id]->scan_size(burst, l);
-
-    int offset = 1; // Why is bit 0 0?
-    // Skip 1s at the beginning
-    while(e->m[module_id]->scan_lookup(burst, l, offset))
-      {
-	offset ++;
-	if(offset >= scan_width)
-	  return true; // No data detected
-      }
-
-    // This is for unencoded mode (not 8b10b)
-    // SOP|10-bit words|EOP
-    // Each 10-bit word has 00 then 8-bit byte
-    uint16_t word = 0;
-
-    std::vector<uint8_t> bytes;
-
-    bool inPacket = false;
-    bool found_end = false;
-
-    for(int b=0; b+offset<scan_width; b++)
-      {
-	int bit = m_e->m[module_id]->scan_lookup(burst, l, offset + b);
-	//std::cout << b+offset << "/" << scan_width << " - " << (b%10) << ": " << bit << std::endl;
-
-	if(found_end)
-	  {
-	    if(bit == 0)
-	      continue;
-	    else
-	      {
-		std::cerr << "Found non-zero bit after end of capture2 buffer" << std::endl;
-		// Capture2 doesn't fill the whole of the burst width
-		break;
-	      }
-	  }
-
-	word <<= 1;
-	if(bit) word |= 1;
-
-	if((b % 10) != 9) // Continue parsing until end of "byte" reached
-	  continue;
-
-	if(word == 0x3ff)
-	  {
-	    // Ignore idle
-	    if(inPacket)
-	      {
-		std::cerr << "Bad idle inside packet" << std::endl;
-		bytes.clear();
-		inPacket = false;
-	      }
-	  }
-	else if(word == 0x13c) // SOP
-	  {
-	    inPacket = true;
-	  }
-	else if(word == 0x1dc) // EOP
-	  {
-	    result.push_back(bytes);
-	    bytes.clear();
-	    inPacket = false;
-	  }
-	else
-	  {
-	    if(word & 0x300)
-	      {
-		// We're in capture2 mode, so might come to the end of the data
-		// before the end of the burst histo.
-		uint16_t test_word = word;
-		while(test_word & 0x200)
-		  test_word = (test_word << 1) & 0x3ff;
-
-		if(test_word)
-		  {
-		    std::cerr << "Non data word is NOT IDLE, EOP or SOP!, but is 0x" << std::hex << std::setw(4) << std::setfill('0') << word << std::dec << std::endl;
-
-		    inPacket = false;
-		    bytes.clear();
-		  }
-		else
-		  {
-		    // End of buffer we copied from the packet
-		    found_end = true;
-		  }
-	      }
-	    bytes.push_back(word&0xFF);
-	  }
-
-	word = 0;
-      }
-
-    return false;
-  }
-
 private:
   // module
   TST *m_e=nullptr;
 
   // output data
   TFile *m_fh=nullptr;
-  TTree *m_tree=nullptr;
-  std::unordered_map<int, std::shared_ptr<RegisterDump>> br_hccregs;
-  std::unordered_map<int, std::vector<std::shared_ptr<RegisterDump>>> br_abcregs;
-  std::unordered_map<int, std::shared_ptr<RegisterReadStreamCaptureDump>> br_hcccap;
-  std::unordered_map<int, std::shared_ptr<RegisterReadStreamCaptureDump>> br_abccap;
-  uint32_t br_timestamp;
+  std::shared_ptr<RegisterReadStreamCaptureDump> m_regdump;
+  uint32_t m_timestamp;
 
   // Register map
   static const std::unordered_map<int, std::string> hcc_regs;
   static const std::unordered_map<int, std::string> abcv0_regs;
   static const std::unordered_map<int, std::string> abcv1_regs;
 
-  void createTree()
-  {      
-    // Create the tree
-    m_fh->cd();
-    m_tree=new TTree("registers", "registers");
-    m_tree->Branch("time", &br_timestamp);
-
-    // Query module to get structure
-    for (int n=0; n<m_e->GetMaxModules(); ++n)
-      {
-	if(!m_e->m[n]->present) continue;
-
-	// HCC Registers
-	if(m_e->HccPresent())
-	  {
-	    br_hccregs[n]=std::make_shared<RegisterDump>(hcc_regs);
-	    br_hccregs[n]->createBranches(m_tree, "Mod"+std::to_string(n)+"_HCC");
-	  }
-
-	br_hcccap[n]=std::make_shared<RegisterReadStreamCaptureDump>(hcc_regs);
-	br_hcccap[n]->createBranches(m_tree, "Mod"+std::to_string(n)+"_HCC");
-
-	// ABC Registers
-	bool v1=get_chipset()==9;
-	const std::unordered_map<int, std::string>& abc_regs=(v1)?(abcv1_regs):(abcv0_regs);
-	std::vector<std::shared_ptr<RegisterDump>> abcdumps(e->GetNChips(), nullptr);
-	for(int a=0; a<m_e->GetNChips(); ++a)
-	  {
-	    abcdumps[a]=std::make_shared<RegisterDump>(abc_regs);
-	    abcdumps[a]->createBranches(m_tree, "Mod"+std::to_string(n)+"_ABC"+std::to_string(a));
-	  }
-	br_abcregs[n]=abcdumps;
-
-	br_abccap[n]=std::make_shared<RegisterReadStreamCaptureDump>(abc_regs);
-	br_abccap[n]->createBranches(m_tree, "Mod"+std::to_string(n)+"_ABC");
-      }
-  }
-
   int get_chipset()
   {
     for(int n=0; n<m_e->GetLastPresentId()+1; ++n)
@@ -486,6 +228,25 @@ const std::unordered_map<int, std::string> RegisterDumper::abcv1_regs =
     {184, "Counter56"}, {185, "Counter57"}, {186, "Counter58"}, {187, "Counter59"}, {188, "Counter60"}, {189, "Counter61"}, {190, "Counter62"}, {191, "Counter63"}
   };
 
+void set_default_registers(TST* e)
+{
+  /*
+  // Mask registers
+  for(uint32_t reg=ABC_STAR_REG_MASK_BASE; reg<ABC_STAR_REG_MASK_END; reg++)
+    e->ConfigureVariable(reg, 0xF0F0F0F0);
+
+  // TrimDAC registers
+  for(uint32_t i=0; i<32; i++)
+    e->ConfigureVariable(ABC_STAR_REG_TRIM_LO_BASE+i, 0xF0F0F0F0);
+
+  for(uint32_t i=0; i<8; i++)
+    e->ConfigureVariable(ABC_STAR_REG_TRIM_HI_BASE+i, 0xF0F0F0F0);
+
+  // Cal registers
+  for(uint32_t i=0; i<8; i++)
+    e->ConfigureVariable(ABC_STAR_REG_CAL_BASE+i, 0x00000000);
+  */
+}
 
 void monitor()
 {
@@ -514,11 +275,19 @@ void monitor()
   hcc_star_hpr_stop();
   e->ExecuteConfigs();
 
+  e->ConfigureVariable(ST_TRIM, 0x15);
+  e->ConfigureVariable(ST_MASK, 0x1);
+  e->ExecuteConfigs();
+
+  hcc_star_packet_transparent_mode();
+  st_dump_chip_registers();
+
   //
   // RUN ME!
   auto t_bigloopstart = std::chrono::system_clock::now();
   while(std::chrono::duration_cast<std::chrono::seconds>(std::chrono::system_clock::now()-t_bigloopstart).count()<time_running)
     {
+
       //
       // Test structures
       char f_name[128];
@@ -532,9 +301,17 @@ void monitor()
       while(std::chrono::duration_cast<std::chrono::seconds>(std::chrono::system_clock::now()-t_smallloopstart).count()<stime_running)
 	{
 	  d.run();
-      
+
 	  sleep(1);
-	  //return 1;
+	  //return;
 	}
+
+      //
+      // Reset SEU counters
+      hcc_star_seu_reset();
+      abc_star_seu_reset();
+
+      // Restore all configurations
+      e->ExecuteConfigs();
     }
 }
-- 
GitLab


From 266b5a0180bf6255380fd4d8e20b73c821453ef7 Mon Sep 17 00:00:00 2001
From: Berkeley Strippers <strips@lbl>
Date: Fri, 25 Sep 2020 15:08:02 -0700
Subject: [PATCH 22/29] Add status output to module-powerOn.

---
 scripts/module-powerOn.sh | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/scripts/module-powerOn.sh b/scripts/module-powerOn.sh
index a6e1757d..ed3c0092 100755
--- a/scripts/module-powerOn.sh
+++ b/scripts/module-powerOn.sh
@@ -35,13 +35,14 @@ OPTS="-e ${TBCONFIG}"
 
 #
 # Enable the DCDC
+echo "Enable the DCDC"
 ./bin/pbv3_field ${OPTS} write DCDCen 1 || exit 1
 ./bin/pbv3_field ${OPTS} write DCDCenC 1 || exit 1
-
 #
 # Enable the Hybrid
 
 # Hybrid LDOs
+echo "Hybrid LDO's"
 ./bin/pbv3_field ${OPTS} write CntSetHyLDO0en 1 || exit 1
 ./bin/pbv3_field ${OPTS} write CntSetCHyLDO0en 1 || exit 1
 ./bin/pbv3_field ${OPTS} write CntSetHyLDO1en 1 || exit 1
@@ -57,6 +58,7 @@ OPTS="-e ${TBCONFIG}"
 ./bin/pbv3_field ${OPTS} write CntSetCHxLDO2en 1 || exit 1
 
 # resetB
+echo "HCC ResetB"
 ./bin/pbv3_field ${OPTS} write RstCntHyHCCresetB 1 || exit 1
 ./bin/pbv3_field ${OPTS} write RstCntCHyHCCresetB 1 || exit 1
 ./bin/pbv3_field ${OPTS} write RstCntHxHCCresetB 1 || exit 1
@@ -65,5 +67,3 @@ OPTS="-e ${TBCONFIG}"
 # HV mux
 ./bin/pbv3_field ${OPTS} write CntSetCHV0en 1 || exit 1
 ./bin/pbv3_field ${OPTS} write CntSetHV0en 1 || exit 1
-
-
-- 
GitLab


From 94bd37dd465a88e96e9f81de47032a02b7ce6675 Mon Sep 17 00:00:00 2001
From: Berkeley Strippers <strips@lbl>
Date: Fri, 25 Sep 2020 15:24:06 -0700
Subject: [PATCH 23/29] Add cleanup to pbv3_betsee.

---
 pbv3/tools/pbv3_betsee.cpp | 22 +++++++++++++++++-----
 1 file changed, 17 insertions(+), 5 deletions(-)

diff --git a/pbv3/tools/pbv3_betsee.cpp b/pbv3/tools/pbv3_betsee.cpp
index 03ecb494..387520da 100644
--- a/pbv3/tools/pbv3_betsee.cpp
+++ b/pbv3/tools/pbv3_betsee.cpp
@@ -1,6 +1,7 @@
 #include <unistd.h>
 #include <string.h>
 #include <getopt.h>
+#include <signal.h>
 
 #include <chrono>
 #include <fstream>
@@ -26,6 +27,10 @@ std::string configfile1 = "config1.json";
 std::string equipConfigFile = "config/equip_testbench.json";
 //---------------
 
+bool quit=false;
+void cleanup(int signum)
+{ quit=true; }
+
 #define PERIOD_LONG 60 // number of seconds of monitoring between calibrations
 #define PERIOD_MONITOR 1 // number of seconds to wait between readings
 void usage(char* argv[])
@@ -88,6 +93,10 @@ int main(int argc, char* argv[])
   logger(logDEBUG) << " configfile0: " << configfile0;
   logger(logDEBUG) << " configfile1: " << configfile1;
 
+  // Register interrupt for cleanup
+  signal(SIGINT, cleanup);
+  signal(SIGTERM, cleanup);
+
   // Get default config
   json defconfig0;
   if(!configfile0.empty())
@@ -111,15 +120,15 @@ int main(int argc, char* argv[])
   if(tb==nullptr)
     return 1;
 
-  std::shared_ptr<AMACv2> amac0=tb->getPB(1);
-  std::shared_ptr<AMACv2> amac1=tb->getPB(2);
+  std::shared_ptr<AMACv2> amac0=tb->getPB(0);
+  std::shared_ptr<AMACv2> amac1=tb->getPB(1);
   amac0->init();
   amac1->init();
 
   // 
   // Start running tests in a loop forever!
   //
-  while(true)
+  while(!quit)
     {
       //
       // Rerun the calibration
@@ -130,6 +139,7 @@ int main(int argc, char* argv[])
       config0.merge_patch(PBv3ConfigTools::calibrateSlope      (amac0, tb->getCalDAC()));
       config0.merge_patch(PBv3ConfigTools::calibrateOffset     (amac0));
       config0.merge_patch(PBv3ConfigTools::calibrateNTC        (amac0));
+      config0.merge_patch(PBv3ConfigTools::calibrateCur10V     (amac0));
       PBv3ConfigTools::saveConfigAMAC(amac0, config0);
 
       json config1=defconfig1;
@@ -137,6 +147,7 @@ int main(int argc, char* argv[])
       config1.merge_patch(PBv3ConfigTools::calibrateSlope      (amac1, tb->getCalDAC()));
       config1.merge_patch(PBv3ConfigTools::calibrateOffset     (amac1));
       config1.merge_patch(PBv3ConfigTools::calibrateNTC        (amac1));
+      config1.merge_patch(PBv3ConfigTools::calibrateCur10V     (amac1));
       PBv3ConfigTools::saveConfigAMAC(amac1, config1);
 
       // Prepare the output structures
@@ -155,7 +166,7 @@ int main(int argc, char* argv[])
       uint32_t test=0;
 
       // Start monitoring in a loop
-      for(uint32_t monIdx=0; monIdx<PERIOD_LONG/PERIOD_MONITOR; monIdx++)
+      for(uint32_t monIdx=0; monIdx<PERIOD_LONG/PERIOD_MONITOR && !quit; monIdx++)
 	{
 	  if(std::dynamic_pointer_cast<PBv3TBSingle>(tb))
 	    {
@@ -191,7 +202,8 @@ int main(int argc, char* argv[])
       outfile1 << std::setw(4) << testSum1 << std::endl;
       outfile1.close();
 
-      logger(logINFO) << "Results stored in " << fileName0 << " and " << fileName1;
+      logger(logINFO) << "Results stored in " << fileName0;
+      logger(logINFO) << "Results stored in " << fileName1;
     }
 
   return 0;
-- 
GitLab


From c33223a88c960fa91ff5f2c8a2f0d8435a03f2fc Mon Sep 17 00:00:00 2001
From: Berkeley Strippers <strips@lbl>
Date: Fri, 25 Sep 2020 15:24:20 -0700
Subject: [PATCH 24/29] Add betsee-run.sh script.

---
 scripts/betsee-run.sh | 151 ++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 151 insertions(+)
 create mode 100755 scripts/betsee-run.sh

diff --git a/scripts/betsee-run.sh b/scripts/betsee-run.sh
new file mode 100755
index 00000000..1d0dc420
--- /dev/null
+++ b/scripts/betsee-run.sh
@@ -0,0 +1,151 @@
+#!/bin/bash
+
+#
+# Script that handles running a test on a module from scratch (no power)
+#
+# The following steps are taken:
+#  - Enable LV power
+#  - Configure the Powerboard
+#  - Power the hybrids (module-powerOn.sh)
+#  - Launch two programs in parallel:
+#    1. ROOT macro for control of the hybrid
+#    2. Start Powerboard monitoring loop
+#
+# The Powerboard monitoring loop is started a few seconds after ITSDAQ
+# to prevent clashes on the I2C bus.
+#
+# If either ITSDAQ or pbv3_monitor exists, then this script also
+# completes.
+
+# trap Ctrl+c for cleanup
+trap cleanup INT
+trap cleanup SIGCHLD
+function cleanup() {
+    echo "Terminate processes ${ITSDAQPID} ${PBPID}"
+    if [ ! -z "${ITSDAQPID}" ]; then
+	ps -p ${ITSDAQPID} && kill -- -${ITSDAQPID} 
+    fi
+    if [ ! -z "${PBPID}" ]; then
+    	ps -p ${PBPID} && kill -- -${PBPID}
+    fi
+    exit 0
+}
+
+TBCONFIG="config/equip_testbench.json"
+PB0CONFIG=""
+PB1CONFIG=""
+
+function usage
+{
+    echo "${0} [-e equip.json -0 pb0.json -1 pb1.json] datadir macro.C"
+    echo ""
+    echo "Optional arguments:"
+    echo " -e equip.json      Equipment configuration file (default: ${TBCONFIG})"
+    echo " -0 pb0.json        Main Powerboard configuration file (default: ${PB0CONFIG})"
+    echo " -1 pb1.json        Secondary Powerboard configuration file (default: ${PB1CONFIG})"
+    exit 1
+}
+
+while getopts ":he:0:1:" opt; do
+    case ${opt} in
+	h )
+	    usage
+	    ;;
+	e )
+	    TBCONFIG=${OPTARG}
+	    ;;
+	0 )
+	    PB0CONFIG=${OPTARG}
+	    ;;
+	1 )
+	    PB1CONFIG=${OPTARG}
+	    ;;
+	\? )
+	    usage
+	    ;;
+    esac
+done
+shift $((OPTIND -1))
+
+OPTS="-e ${TBCONFIG}"
+
+if [ ${#} != 2 ]; then
+    usage
+fi
+
+DATADIR=${1}
+MACRO=${2}
+
+#
+# Create output directory
+if [ ! -d ${DATADIR} ]; then
+    mkdir -p ${DATADIR}
+fi
+
+#
+# Turn on LV
+./bin/powersupply ${OPTS} -c Vin set-voltage 11 0.5 || exit 2
+./bin/powersupply ${OPTS} -e ${TBCONFIG} -c Vin power-on || exit 2
+
+#
+# Configure Powerboard
+if [ ! -z "${PB0CONFIG}" ];
+then
+    ./bin/pbv3_config -b0 ${OPTS} ${PB0CONFIG} || exit 2
+fi
+
+if [ ! -z "${PB1CONFIG}" ];
+then
+    ./bin/pbv3_config -b1 ${OPTS} ${PB1CONFIG} || exit 2
+fi
+
+#
+# Power Hybrids
+./scripts/module-powerOn.sh ${OPTS} || exit 2
+
+sleep 10
+
+#
+# Start monitoring loops
+
+# ITSDAQ
+setsid ./scripts/EXEITSDAQ.sh ${MACRO} >> ${DATADIR}/itsdaq.out 2>> ${DATADIR}/itsdaq.err &
+ITSDAQPID=${!}
+echo "ITSDAQ running as ${ITSDAQPID}"
+
+sleep 10
+
+# Powerboard
+setsid ./bin/pbv3_betsee ${OPTS} ${PB0CONFIG} ${PB1CONFIG} ${DATADIR}/ >> ${DATADIR}/pb.out 2>> ${DATADIR}/pb.err &
+PBPID=${!}
+echo "Powerboard running as ${PBPID}"
+
+#
+# Wait for monitoring loops
+while true
+do
+    if [ ! -z "${ITSDAQPID}" ]; then
+	ps -p ${ITSDAQPID} -o pid= > /dev/null
+	if [ ${?} != 0 ]; then
+	    echo "ITSDAQ proccess has completed"
+	    unset ITSDAQPID
+	fi
+    fi
+
+    if [ ! -z "${PBPID}" ]; then
+	ps -p ${PBPID} -o pid= > /dev/null
+	if [ ${?} != 0 ]; then
+    	    echo "Powerboard process has completed"
+	    unset PBPID
+	fi
+    fi
+
+
+    if [ -z "${ITSDAQPID}" ] && [ -z "${PBPID}" ]; then
+	break
+    fi
+    sleep 1
+done
+
+sleep 60 # Log a bit more data
+cleanup
-- 
GitLab


From 24e955050832cdcb04505af53051b8c247fce46e Mon Sep 17 00:00:00 2001
From: Berkeley Strippers <strips@lbl>
Date: Fri, 25 Sep 2020 15:25:00 -0700
Subject: [PATCH 25/29] Fixes to seu test.

---
 pbv3/PBv3TestTools.cpp | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/pbv3/PBv3TestTools.cpp b/pbv3/PBv3TestTools.cpp
index 9556fa87..d074e2b1 100644
--- a/pbv3/PBv3TestTools.cpp
+++ b/pbv3/PBv3TestTools.cpp
@@ -1365,7 +1365,7 @@ namespace PBv3TestTools
 	    ++nSEU;
 
 	    std::stringstream ss;
-	    ss << "SEU in register " << reg->getAddress() << ": ";
+	    ss << "SEU in register " << (uint32_t)reg->getAddress() << ": ";
 	    ss << "0x" << std::hex << std::setw(8) << std::setfill('0') << curval << std::dec;
 	    ss << " (expected 0x" << std::hex << std::setw(8) << std::setfill('0') << expval << std::dec << ")";
 	    logger(logINFO) << ss.str();
@@ -1373,10 +1373,10 @@ namespace PBv3TestTools
 	    // Correct
 	    amac->write_reg(reg->getAddress(), expval);
 	    uint32_t curval2=amac->read_reg(reg->getAddress());
-	    if(curval2==expval)
+	    if(curval2!=expval)
 	      {
 		std::stringstream ss;
-		ss << "Found an unrecoverable SEU in register " << reg->getAddress() << ": ";
+		ss << "Found an unrecoverable SEU in register " << (uint32_t)reg->getAddress() << ": ";
 		ss << "0x" << std::hex << std::setw(8) << std::setfill('0') << curval << std::dec;
 		ss << " (expected 0x" << std::hex << std::setw(8) << std::setfill('0') << expval << std::dec << ")";
 		throw std::runtime_error(ss.str());
-- 
GitLab


From 3317817e23f923bc12e0991cb6dec81cf65c8d81 Mon Sep 17 00:00:00 2001
From: Berkeley Strippers <strips@lbl>
Date: Fri, 25 Sep 2020 15:26:02 -0700
Subject: [PATCH 26/29] Add check on fields when configuring a PB.

---
 pbv3/PBv3ConfigTools.cpp | 9 ++++++++-
 1 file changed, 8 insertions(+), 1 deletion(-)

diff --git a/pbv3/PBv3ConfigTools.cpp b/pbv3/PBv3ConfigTools.cpp
index 694a809e..cc2fb27f 100644
--- a/pbv3/PBv3ConfigTools.cpp
+++ b/pbv3/PBv3ConfigTools.cpp
@@ -21,7 +21,14 @@ namespace PBv3ConfigTools
       {
 	for(auto field : cfgtop["properties"].items())
 	  {
-	    amac->findField(field.key())->setDefaultVal(field.value().get<uint32_t>());
+	    AMACv2Field *fref=amac->findField(field.key());
+	    if(fref==nullptr)
+	      {
+		logger(logWARNING) << "Skipping non-existent field " << field.key();
+		continue;
+	      }
+
+	    fref->setDefaultVal(field.value().get<uint32_t>());
 	    if(write)
 	      amac->wrField  (field.key(), field.value().get<uint32_t>());
 	  }
-- 
GitLab


From 20b861d634a5aaef0980d6786a2c356dc6e7ff7f Mon Sep 17 00:00:00 2001
From: Berkeley Strippers <strips@lbl>
Date: Fri, 25 Sep 2020 15:26:27 -0700
Subject: [PATCH 27/29] Add reset call to ADC when on module.

---
 pbv3/PBv3TB.cpp | 9 ++++++++-
 1 file changed, 8 insertions(+), 1 deletion(-)

diff --git a/pbv3/PBv3TB.cpp b/pbv3/PBv3TB.cpp
index 9acd9ee6..5233d841 100644
--- a/pbv3/PBv3TB.cpp
+++ b/pbv3/PBv3TB.cpp
@@ -1,5 +1,7 @@
 #include "PBv3TB.h"
 
+#include "AD56X9.h"
+
 #include <stdexcept>
 
 PBv3TB::PBv3TB()
@@ -15,7 +17,12 @@ void PBv3TB::setCalDAC(std::shared_ptr<DACDevice> CalDAC)
 { m_CalDAC=CalDAC; }
 
 std::shared_ptr<DACDevice> PBv3TB::getCalDAC()
-{ return m_CalDAC; }
+{ 
+  std::shared_ptr<AD56X9> me=std::dynamic_pointer_cast<AD56X9>(m_CalDAC);
+  if(me)
+    me->com()->write_block({0x4F,0x00,0x3F});
+  return m_CalDAC;
+}
 
 void PBv3TB::setLVPS(std::shared_ptr<PowerSupplyChannel> ps)
 { m_lv=ps; }
-- 
GitLab


From bba05c890f64faba69532e01d54d5a4003c88f00 Mon Sep 17 00:00:00 2001
From: Berkeley Strippers <strips@lbl>
Date: Fri, 25 Sep 2020 15:26:39 -0700
Subject: [PATCH 28/29] Map fixes.

---
 pbv3/AMACv2RegMap.cpp | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/pbv3/AMACv2RegMap.cpp b/pbv3/AMACv2RegMap.cpp
index fea3ad14..f7796870 100644
--- a/pbv3/AMACv2RegMap.cpp
+++ b/pbv3/AMACv2RegMap.cpp
@@ -224,7 +224,7 @@ void AMACv2RegMap::init()
       // 117 - HyLoTh5
       &AMACv2RegMap::HyLoThCh15,
       // 118 - HyHiTh0
-      &AMACv2RegMap::HyLoThCh0, &AMACv2RegMap::HyLoThCh1, &AMACv2RegMap::HyLoThCh2,
+      &AMACv2RegMap::HyHiThCh0, &AMACv2RegMap::HyHiThCh1, &AMACv2RegMap::HyHiThCh2,
       // 119 - HyHiTh1
       &AMACv2RegMap::HyHiThCh3, &AMACv2RegMap::HyHiThCh4, &AMACv2RegMap::HyHiThCh5,
       // 120 - HyHiTh2
@@ -248,7 +248,7 @@ void AMACv2RegMap::init()
       // 129 - HV0LoTh5
       &AMACv2RegMap::HV0LoThCh15,
       // 130 - HV0HiTh0
-      &AMACv2RegMap::HV0LoThCh0, &AMACv2RegMap::HV0LoThCh1, &AMACv2RegMap::HV0LoThCh2,
+      &AMACv2RegMap::HV0HiThCh0, &AMACv2RegMap::HV0HiThCh1, &AMACv2RegMap::HV0HiThCh2,
       // 131 - HV0HiTh1
       &AMACv2RegMap::HV0HiThCh3, &AMACv2RegMap::HV0HiThCh4, &AMACv2RegMap::HV0HiThCh5,
       // 132 - HV0HiTh2
@@ -272,7 +272,7 @@ void AMACv2RegMap::init()
       // 141 - HV2LoTh5
       &AMACv2RegMap::HV2LoThCh15,
       // 142 - HV2HiTh0
-      &AMACv2RegMap::HV2LoThCh0, &AMACv2RegMap::HV2LoThCh1, &AMACv2RegMap::HV2LoThCh2,
+      &AMACv2RegMap::HV2HiThCh0, &AMACv2RegMap::HV2HiThCh1, &AMACv2RegMap::HV2HiThCh2,
       // 143 - HV2HiTh1
       &AMACv2RegMap::HV2HiThCh3, &AMACv2RegMap::HV2HiThCh4, &AMACv2RegMap::HV2HiThCh5,
       // 144 - HV2HiTh2
@@ -296,7 +296,7 @@ void AMACv2RegMap::init()
       // 153 - DCDCLoTh5
       &AMACv2RegMap::DCDCLoThCh15,
       // 154 - DCDCHiTh0
-      &AMACv2RegMap::DCDCLoThCh0, &AMACv2RegMap::DCDCLoThCh1, &AMACv2RegMap::DCDCLoThCh2,
+      &AMACv2RegMap::DCDCHiThCh0, &AMACv2RegMap::DCDCHiThCh1, &AMACv2RegMap::DCDCHiThCh2,
       // 155 - DCDCHiTh1
       &AMACv2RegMap::DCDCHiThCh3, &AMACv2RegMap::DCDCHiThCh4, &AMACv2RegMap::DCDCHiThCh5,
       // 156 - DCDCHiTh2
-- 
GitLab


From a67aeb4f42e7f221286212e597e10e04e2c582a7 Mon Sep 17 00:00:00 2001
From: Berkeley Strippers <strips@lbl>
Date: Fri, 25 Sep 2020 15:27:17 -0700
Subject: [PATCH 29/29] Work on monitor.C

---
 itsdaq/monitor.C | 85 ++++++++++++++++++++++++++++++++++++++++--------
 1 file changed, 72 insertions(+), 13 deletions(-)

diff --git a/itsdaq/monitor.C b/itsdaq/monitor.C
index ed76e547..58d2721f 100644
--- a/itsdaq/monitor.C
+++ b/itsdaq/monitor.C
@@ -95,26 +95,25 @@ private:
 class RegisterDumper
 {
 public:
-  RegisterDumper(const std::string& outputpath, TST *e)
+  RegisterDumper(TFile *outfile, TST *e)
     : m_e(e)
   {
-    m_fh=TFile::Open(outputpath.c_str(), "RECREATE");
+    m_fh=outfile; //TFile::Open(outputpath.c_str(), "RECREATE");
     m_regdump=std::make_shared<RegisterReadStreamCaptureDump>();    
   }
 
   ~RegisterDumper()
+  { }
+
+  void write()
   {
+    m_fh->cd();
     m_regdump->tree()->Write();
-    m_fh->Close();
-
-    std::string output=m_fh->GetPath();
-    output.pop_back(); output.pop_back(); // Remove ":/"
-    std::cout << "Registers dumped to: " << output << std::endl;
   }
 
-  void run()
+  void run(uint32_t timestamp)
   {
-    m_timestamp = std::chrono::duration_cast<std::chrono::seconds>((std::chrono::system_clock::now().time_since_epoch())).count();
+    m_timestamp = timestamp;
 
     bool hccFormat=m_e->HccPresent();
     for (int n=0; n<m_e->GetMaxModules(); ++n)
@@ -255,11 +254,12 @@ void monitor()
 
   //
   // Initialize ITSDAQ and Hybrids
-  e->Restart();
+  // e->Restart();
 
   e->ConfigureVariable(10048,0xffff);
   e->ConfigureVariable(10011,0x22);
   e->ConfigureVariable(0,53,1);
+  streamConfigWrite(0xffff, 2, 0x200);
   e->ExecuteConfigs();
 
   hcc_star_reg_write(16,4);
@@ -279,7 +279,11 @@ void monitor()
   e->ConfigureVariable(ST_MASK, 0x1);
   e->ExecuteConfigs();
 
+  e->ConfigureVariable(ST_ABC_STAR_TEST_MUX, 81);
+  e->ExecuteConfigs();
+
   hcc_star_packet_transparent_mode();
+  e->ExecuteConfigs();
   st_dump_chip_registers();
 
   //
@@ -292,25 +296,80 @@ void monitor()
       // Test structures
       char f_name[128];
       BuildScanFileName(f_name,e->runnum,e->scannum++);
-      RegisterDumper d(f_name, e);
+
+      //std::string regdump_path=std::string(getDataDirectory())+"/regdump"+std::to_string(e->runnum)+"_"+std::to_string(dumpnum++)+".root";
+      TFile *fh=TFile::Open(f_name, "RECREATE");
+      uint32_t timestamp=0;
+
+      RegisterDumper d(fh, e);
+
+      fh->cd();
+
+      TTree *t=new TTree("statusblock","statusblock");
+      uint8_t br_testoutMUX=81;
+      std::string br_testout;
+      uint16_t br_sb[64];
+      t->Branch("timestamp", &timestamp);
+      t->Branch("sb", br_sb, "sb[64]/s");
+      t->Branch("testout", &br_testout);
+      t->Branch("testoutMUX", &br_testoutMUX);
 
       auto t_smallloopstart = std::chrono::system_clock::now();
 
       //
       // Continious monitoring
+      Matt_SendCommand(0, 0x2000); // start counting
       while(std::chrono::duration_cast<std::chrono::seconds>(std::chrono::system_clock::now()-t_smallloopstart).count()<stime_running)
 	{
-	  d.run();
 
+	  timestamp = std::chrono::duration_cast<std::chrono::seconds>((std::chrono::system_clock::now().time_since_epoch())).count();
+	  //
+	  // Do degister
+	  d.run(timestamp);
+
+	  //
+	  // Do TESTOUT
+	  /*
+	  e->StoreEnables(false);
+
+	  e->ModifyStreamMap(0, 0, 2); // Capture 0 and 2
+	  e->ModifyEnables(0, 1, 1, 1, 1); // Enable both links
+	  e->burst_trtype = 0;  // Send a normal trigger, which you should see on in link 0
+	  e->burst_ntrigs = 1;
+
+	  burstDisp->SingleBurst(9);
+	  br_testout = BitStringFromBurst(0, 0, false);
+	  std::cout << "TESTOUT = " << br_testout << std::endl;
+
+	  e->StoreEnables(true);
+	  */
 	  sleep(1);
-	  //return;
+
+	  Matt_GetStatusBlock(br_sb, 64);
+	  printf("Edgecount %04x%04x, TimeCount %04x%04x\n", br_sb[61], br_sb[60], br_sb[63], br_sb[62]);
+	  t->Fill();
 	}
 
+      fh->cd();
+      t->Write();
+
+      d.write();
+      fh->Close();
+
+      std::string output=fh->GetPath();
+      output.pop_back(); output.pop_back(); // Remove ":/"
+      std::cout << "Registers dumped to: " << output << std::endl;
+
       //
       // Reset SEU counters
       hcc_star_seu_reset();
       abc_star_seu_reset();
 
+      // Stop more HPR's
+      // They can turn on due to random errors
+      abc_star_hpr_stop();
+      hcc_star_hpr_stop();
+
       // Restore all configurations
       e->ExecuteConfigs();
     }
-- 
GitLab