Skip to content

Update from working on BMPI

Jan Pospisil requested to merge jpospisi_work into master
  • corrected DDR3 documentation errors, added DDR3 IP core preset example
  • improved Avalon-MM interface and Avalon-MM <-> Wishbone bridge
  • improved VME timeout handling in simulation and reporting in RTL code
  • fixed VME clock frequency
  • few typos, comment improvement and simulation default values

Merge request reports