Generate wishbone access via register interface

Certain accesses on wishbone, when accessing very slow devices (like SPI, I2C, uart, ...) might take too long for VME to complete. Hence this small module allows us to generate wishbone transaction via register interface. Thus the transaction can be triggered and polled for completion to prevent VME timeouts.

This should not influence existing projects, as it is an addition, no changes to existing cores. The merge is requested, because this feature is now needed in VFC-HD_System and I would like to cleanly check-out master branch.