Generate wishbone access via register interface
- Aug 02, 2020
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Miha Dolenc authored
interface.
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- Jul 30, 2020
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Miha Dolenc authored
repository.
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Miha Dolenc authored
often and does not need behavior aligned with control bits.
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Miha Dolenc authored
wishbone bus. Newer VME hardware time-outs faster. I guess it could also be used for debugging purposes - access internal WB bus.
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