From b886326d4b9629e4ec4faa11da836b87716ab16c Mon Sep 17 00:00:00 2001
From: Tom Levens <tom.levens@cern.ch>
Date: Mon, 14 Aug 2017 14:06:27 +0200
Subject: [PATCH] Some small fixes:

  * Added ASYNC_REG synthesis attribute to PulseSync.v which is required
    for Vivado
  * Add missing files to BSTDecoder.qip
  * Add BstDecoderPkg.vhd with SDB record for core.
  * Fix BST message URLs in BstDecoder.v
---
 .../bst_decoder/BstDecoder.qip                |  2 +
 cores_for_synthesis/bst_decoder/BstDecoder.v  |  4 +-
 .../bst_decoder/BstDecoderPkg.vhd             | 78 +++++++++++++++++++
 cores_for_synthesis/bst_decoder/doc/README.md | 42 ----------
 cores_for_synthesis/pulse_sync/PulseSync.v    |  2 +
 5 files changed, 84 insertions(+), 44 deletions(-)
 create mode 100644 cores_for_synthesis/bst_decoder/BstDecoderPkg.vhd
 delete mode 100644 cores_for_synthesis/bst_decoder/doc/README.md

diff --git a/cores_for_synthesis/bst_decoder/BstDecoder.qip b/cores_for_synthesis/bst_decoder/BstDecoder.qip
index a5ccda1..984101e 100644
--- a/cores_for_synthesis/bst_decoder/BstDecoder.qip
+++ b/cores_for_synthesis/bst_decoder/BstDecoder.qip
@@ -5,3 +5,5 @@ set_global_assignment -name VHDL_FILE    [file join $::quartus(qip_path) "ttc_rx
 set_global_assignment -name VHDL_FILE    [file join $::quartus(qip_path) "ttc_rx/TTCrx_Frame_Decoder.vhd"]
 set_global_assignment -name VHDL_FILE    [file join $::quartus(qip_path) "ttc_rx/TTCrx_Hamming_Decoder.vhd"]
 set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "../StatusBusSynch.v"]
+set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "../DpramGenericToWb.v"]
+set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "../ip_open_cores/generic_dpram_mod.v"]
diff --git a/cores_for_synthesis/bst_decoder/BstDecoder.v b/cores_for_synthesis/bst_decoder/BstDecoder.v
index 6975e23..3e55f44 100644
--- a/cores_for_synthesis/bst_decoder/BstDecoder.v
+++ b/cores_for_synthesis/bst_decoder/BstDecoder.v
@@ -48,8 +48,8 @@
 //         Error flag
 //     
 //     Meanings of the address/data pairs can be found at these locations:
-//       LHC: http://bdidev1.cern.ch/bdisoft/operational/abbdisw_wiki/LHC/BST-config
-//       SPS: http://bdidev1.cern.ch/bdisoft/operational/abbdisw_wiki/SPS/BST-config
+//       LHC: https://wikis.cern.ch/display/BEBI/LHC+BST+Message
+//       SPS: https://wikis.cern.ch/display/BEBI/SPS+BST+Message
 //     
 //                          _   _   _   _   _   _   _  /  /  _   _   _  
 //     BstClk_ok          _! |_! |_! |_! |_! |_! |_! |_\  \_! |_! |_! |_
diff --git a/cores_for_synthesis/bst_decoder/BstDecoderPkg.vhd b/cores_for_synthesis/bst_decoder/BstDecoderPkg.vhd
new file mode 100644
index 0000000..b043e53
--- /dev/null
+++ b/cores_for_synthesis/bst_decoder/BstDecoderPkg.vhd
@@ -0,0 +1,78 @@
+------------------------------------------------------------------------
+-- Title      : BST Decoder Package
+-- Project    : BST Decoder Core
+------------------------------------------------------------------------
+-- File       : bst_decoder_pkg.vhd
+-- Author     : T. Levens
+-- Company    : CERN BE-BI-QP
+-- Created    : 2016-10-04
+-- Last update: 2016-10-04
+-- Platform   : FPGA-Generic
+-- Standard   : VDHL
+------------------------------------------------------------------------
+-- Description:
+--
+-- Package containing SDB integration record for BST Decoder core
+------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+use work.wishbone_pkg.all;
+
+package BstDecoderPkg is
+
+    constant c_bst_decoder_sdb : t_sdb_device := (
+        abi_class     => x"0000",              -- undocumented device
+        abi_ver_major => x"01",
+        abi_ver_minor => x"01",
+        wbd_endian    => c_sdb_endian_big,
+        wbd_width     => x"4",                 -- 32-bit port granularity
+        sdb_component => (
+            addr_first  => x"0000000000000000",
+            addr_last   => x"00000000000007FF",
+            product     => (
+                vendor_id => x"000000000000CE42",  -- CERN
+                device_id => x"c7da138c",          -- echo "BST-Decoder        " | md5sum | cut -c1-8
+                version   => x"00000001",
+                date      => x"20170517",
+                name      => "BST-Decoder        "
+            )
+        )
+    );
+
+    component BstDecoder
+        port (
+            WbRst_ir            : in  std_logic;
+            WbClk_ik            : in  std_logic;
+            WbCyc_i             : in  std_logic;
+            WbStb_i             : in  std_logic;
+            WbAdr_ib9           : in  std_logic_vector(8 downto 0);
+            WbDat_ob32          : out std_logic_vector(31 downto 0);
+            WbAck_o             : out std_logic;
+            
+            BstCdrLos_i         : in  std_logic;
+            BstCdrLol_i         : in  std_logic;
+            BstSfpPresent_i     : in  std_logic;
+            BstSfpTxFault_i     : in  std_logic;
+            BstSfpLos_i         : in  std_logic;
+            BstSfpTxDisable_i   : in  std_logic;
+            BstSfpRateSelect_i  : in  std_logic;
+
+            BstReset_ir           : in  std_logic;
+            BstCdrClkOut_ik       : in  std_logic;
+            BstCdrDataOut_i       : in  std_logic;  
+            BstOn_o               : out std_logic;
+            BstClk_ok             : out std_logic;
+            BunchClkFlag_oq       : out std_logic;
+            TurnClkFlag_o         : out std_logic;
+            TurnClkFlagDly_ib12   : in  std_logic_vector(11 downto 0);
+            BstByteAddr_ob8       : out std_logic_vector(7 downto 0);
+            BstByte_ob8           : out std_logic_vector(7 downto 0);    
+            BstByteStrobe_o       : out std_logic;
+            BstByteError_o        : out std_logic
+        );
+    end component BstDecoder;
+
+end BstDecoderPkg;
diff --git a/cores_for_synthesis/bst_decoder/doc/README.md b/cores_for_synthesis/bst_decoder/doc/README.md
deleted file mode 100644
index 0a7f9ed..0000000
--- a/cores_for_synthesis/bst_decoder/doc/README.md
+++ /dev/null
@@ -1,42 +0,0 @@
-# bst_decoder
-
-Decoder for LHC/SPS Beam Synchronous Timing (BST).
-
-## Instantiation Template
-
-```verilog
-bst_decoder
-    i_bst_decoder(
-        // Wishbone interface
-        .Rst_ni(),
-        .SysClk_ik(),
-        .WbAdr_ib9(),
-        .WbDat_ib32(),
-        .WbDat_ob32(),
-        .WbCyc_i(),
-        .WbSel_ib4(),
-        .WbStb_i(),
-        .WbWe_i(),
-        .WbAck_o(),
-        .WbStall_o(),
-        .WbIrq_o(),
-
-        // CDR input
-        .CdrClk_ik(),
-        .CdrDat_i(),
-        .CdrLos_i(),
-        .CdrLol_i(),
-        .SfpLos_i(),
-        .SfpPrsnt_i(),
-
-        // Clock outputs
-        .BunchFlag_o(),
-        .TurnFlag_o(),
-
-        // Message output
-        .MsgAddr_ob8(),
-        .MsgData_ob8(),
-        .MsgStrobe_o(),
-        .MsgError_o()
-    );
-```
diff --git a/cores_for_synthesis/pulse_sync/PulseSync.v b/cores_for_synthesis/pulse_sync/PulseSync.v
index e6fc561..e84921c 100644
--- a/cores_for_synthesis/pulse_sync/PulseSync.v
+++ b/cores_for_synthesis/pulse_sync/PulseSync.v
@@ -42,10 +42,12 @@ always @(posedge ClkIn_ik) begin
 end
 
 // Clock crossing in->out
+(* ASYNC_REG = "TRUE" *)
 reg [2:0] CrossingIO = 3'h0;
 always @(posedge ClkOut_ik) CrossingIO <= {CrossingIO[1:0], InSRFF};
 
 // Clock crossing out->in
+(* ASYNC_REG = "TRUE" *)
 reg [1:0] CrossingOI = 2'h0;
 always @(posedge ClkIn_ik) CrossingOI <= {CrossingOI[0], CrossingIO[1]};
 
-- 
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