Critical warnings compiling Base
@boccardi, @mbarrosm: we should probably fix this, no?
Critical Warning (18061): Ignored Power-Up Level option on the following registers
Critical Warning (18010): Register VfcHdApplication:i_VfcHdApplication|VfcHdGbtCoreX4:i_AppSfpGbtBank|alt_av_gbt_example_design_x4:i_AltAvGbtExampleDesignX4|alt_av_gbt_example_design:i_GbtExmplDsgn|gbt_bank:gbtBank|gbt_rx:\gbtRx_param_generic_src_gen:gbtRx_gen:1:gbtRx|gbt_rx_framealigner:frameAligner|gbt_rx_framealigner_wraddr:writeAddressCtrl|gbWriteAddress[1] will power up to High
Critical Warning (18010): Register VfcHdApplication:i_VfcHdApplication|VfcHdGbtCoreX4:i_AppSfpGbtBank|alt_av_gbt_example_design_x4:i_AltAvGbtExampleDesignX4|alt_av_gbt_example_design:i_GbtExmplDsgn|gbt_bank:gbtBank|gbt_rx:\gbtRx_param_generic_src_gen:gbtRx_gen:4:gbtRx|gbt_rx_framealigner:frameAligner|gbt_rx_framealigner_wraddr:writeAddressCtrl|gbWriteAddress[1] will power up to High
Critical Warning (18010): Register VfcHdApplication:i_VfcHdApplication|VfcHdGbtCoreX4:i_AppSfpGbtBank|alt_av_gbt_example_design_x4:i_AltAvGbtExampleDesignX4|alt_av_gbt_example_design:i_GbtExmplDsgn|gbt_bank:gbtBank|gbt_rx:\gbtRx_param_generic_src_gen:gbtRx_gen:2:gbtRx|gbt_rx_framealigner:frameAligner|gbt_rx_framealigner_wraddr:writeAddressCtrl|gbWriteAddress[1] will power up to High
Critical Warning (18010): Register VfcHdApplication:i_VfcHdApplication|VfcHdGbtCoreX4:i_AppSfpGbtBank|alt_av_gbt_example_design_x4:i_AltAvGbtExampleDesignX4|alt_av_gbt_example_design:i_GbtExmplDsgn|gbt_bank:gbtBank|gbt_rx:\gbtRx_param_generic_src_gen:gbtRx_gen:3:gbtRx|gbt_rx_framealigner:frameAligner|gbt_rx_framealigner_wraddr:writeAddressCtrl|gbWriteAddress[1] will power up to High
Critical Warning (18010): Register VfcHdApplication:i_VfcHdApplication|VfcHdGbtCoreX4:i_AppSfpGbtBank|alt_av_gbt_example_design_x4:i_AltAvGbtExampleDesignX4|alt_av_gbt_example_design:i_GbtExmplDsgn|gbt_bank:gbtBank|gbt_tx:\gbtTx_param_generic_src_gen:gbtTx_gen:1:gbtTx|gbt_tx_gearbox:txGearbox|gbt_tx_gearbox_std:\txGearboxStd_gen:txGearboxStd|gbt_tx_gearbox_std_rdwrctrl:readWriteControl|writeAddress[1] will power up to High
Critical Warning (18010): Register VfcHdApplication:i_VfcHdApplication|VfcHdGbtCoreX4:i_AppSfpGbtBank|alt_av_gbt_example_design_x4:i_AltAvGbtExampleDesignX4|alt_av_gbt_example_design:i_GbtExmplDsgn|gbt_bank:gbtBank|gbt_tx:\gbtTx_param_generic_src_gen:gbtTx_gen:1:gbtTx|gbt_tx_gearbox:txGearbox|gbt_tx_gearbox_std:\txGearboxStd_gen:txGearboxStd|gbt_tx_gearbox_std_rdwrctrl:readWriteControl|writeAddress[2] will power up to High
Critical Warning (18010): Register VfcHdApplication:i_VfcHdApplication|VfcHdGbtCoreX4:i_AppSfpGbtBank|alt_av_gbt_example_design_x4:i_AltAvGbtExampleDesignX4|alt_av_gbt_example_design:i_GbtExmplDsgn|gbt_bank:gbtBank|gbt_tx:\gbtTx_param_generic_src_gen:gbtTx_gen:4:gbtTx|gbt_tx_gearbox:txGearbox|gbt_tx_gearbox_std:\txGearboxStd_gen:txGearboxStd|gbt_tx_gearbox_std_rdwrctrl:readWriteControl|writeAddress[1] will power up to High
Critical Warning (18010): Register VfcHdApplication:i_VfcHdApplication|VfcHdGbtCoreX4:i_AppSfpGbtBank|alt_av_gbt_example_design_x4:i_AltAvGbtExampleDesignX4|alt_av_gbt_example_design:i_GbtExmplDsgn|gbt_bank:gbtBank|gbt_tx:\gbtTx_param_generic_src_gen:gbtTx_gen:4:gbtTx|gbt_tx_gearbox:txGearbox|gbt_tx_gearbox_std:\txGearboxStd_gen:txGearboxStd|gbt_tx_gearbox_std_rdwrctrl:readWriteControl|writeAddress[2] will power up to High
Critical Warning (18010): Register VfcHdApplication:i_VfcHdApplication|VfcHdGbtCoreX4:i_AppSfpGbtBank|alt_av_gbt_example_design_x4:i_AltAvGbtExampleDesignX4|alt_av_gbt_example_design:i_GbtExmplDsgn|gbt_bank:gbtBank|gbt_tx:\gbtTx_param_generic_src_gen:gbtTx_gen:2:gbtTx|gbt_tx_gearbox:txGearbox|gbt_tx_gearbox_std:\txGearboxStd_gen:txGearboxStd|gbt_tx_gearbox_std_rdwrctrl:readWriteControl|writeAddress[1] will power up to High
Critical Warning (18010): Register VfcHdApplication:i_VfcHdApplication|VfcHdGbtCoreX4:i_AppSfpGbtBank|alt_av_gbt_example_design_x4:i_AltAvGbtExampleDesignX4|alt_av_gbt_example_design:i_GbtExmplDsgn|gbt_bank:gbtBank|gbt_tx:\gbtTx_param_generic_src_gen:gbtTx_gen:2:gbtTx|gbt_tx_gearbox:txGearbox|gbt_tx_gearbox_std:\txGearboxStd_gen:txGearboxStd|gbt_tx_gearbox_std_rdwrctrl:readWriteControl|writeAddress[2] will power up to High
Critical Warning (18010): Register VfcHdApplication:i_VfcHdApplication|VfcHdGbtCoreX4:i_AppSfpGbtBank|alt_av_gbt_example_design_x4:i_AltAvGbtExampleDesignX4|alt_av_gbt_example_design:i_GbtExmplDsgn|gbt_bank:gbtBank|gbt_tx:\gbtTx_param_generic_src_gen:gbtTx_gen:3:gbtTx|gbt_tx_gearbox:txGearbox|gbt_tx_gearbox_std:\txGearboxStd_gen:txGearboxStd|gbt_tx_gearbox_std_rdwrctrl:readWriteControl|writeAddress[1] will power up to High
Critical Warning (18010): Register VfcHdApplication:i_VfcHdApplication|VfcHdGbtCoreX4:i_AppSfpGbtBank|alt_av_gbt_example_design_x4:i_AltAvGbtExampleDesignX4|alt_av_gbt_example_design:i_GbtExmplDsgn|gbt_bank:gbtBank|gbt_tx:\gbtTx_param_generic_src_gen:gbtTx_gen:3:gbtTx|gbt_tx_gearbox:txGearbox|gbt_tx_gearbox_std:\txGearboxStd_gen:txGearboxStd|gbt_tx_gearbox_std_rdwrctrl:readWriteControl|writeAddress[2] will power up to High
Critical Warning (18010): Register VfcHdApplication:i_VfcHdApplication|VfcHdGbtCoreX4:i_AppSfpGbtBank|alt_av_gbt_example_design_x4:i_AltAvGbtExampleDesignX4|alt_av_gbt_example_design:i_GbtExmplDsgn|gbt_bank:gbtBank|gbt_rx:\gbtRx_param_generic_src_gen:gbtRx_gen:1:gbtRx|gbt_rx_framealigner:frameAligner|gbt_rx_framealigner_wraddr:writeAddressCtrl|gbWriteAddress[1] will power up to High
Critical Warning (18010): Register VfcHdApplication:i_VfcHdApplication|VfcHdGbtCoreX4:i_AppSfpGbtBank|alt_av_gbt_example_design_x4:i_AltAvGbtExampleDesignX4|alt_av_gbt_example_design:i_GbtExmplDsgn|gbt_bank:gbtBank|gbt_rx:\gbtRx_param_generic_src_gen:gbtRx_gen:4:gbtRx|gbt_rx_framealigner:frameAligner|gbt_rx_framealigner_wraddr:writeAddressCtrl|gbWriteAddress[1] will power up to High
Critical Warning (18010): Register VfcHdApplication:i_VfcHdApplication|VfcHdGbtCoreX4:i_AppSfpGbtBank|alt_av_gbt_example_design_x4:i_AltAvGbtExampleDesignX4|alt_av_gbt_example_design:i_GbtExmplDsgn|gbt_bank:gbtBank|gbt_rx:\gbtRx_param_generic_src_gen:gbtRx_gen:2:gbtRx|gbt_rx_framealigner:frameAligner|gbt_rx_framealigner_wraddr:writeAddressCtrl|gbWriteAddress[1] will power up to High
Critical Warning (18010): Register VfcHdApplication:i_VfcHdApplication|VfcHdGbtCoreX4:i_AppSfpGbtBank|alt_av_gbt_example_design_x4:i_AltAvGbtExampleDesignX4|alt_av_gbt_example_design:i_GbtExmplDsgn|gbt_bank:gbtBank|gbt_rx:\gbtRx_param_generic_src_gen:gbtRx_gen:3:gbtRx|gbt_rx_framealigner:frameAligner|gbt_rx_framealigner_wraddr:writeAddressCtrl|gbWriteAddress[1] will power up to High
Critical Warning (18010): Register VfcHdApplication:i_VfcHdApplication|VfcHdGbtCoreX4:i_AppSfpGbtBank|alt_av_gbt_example_design_x4:i_AltAvGbtExampleDesignX4|alt_av_gbt_example_design:i_GbtExmplDsgn|gbt_bank:gbtBank|gbt_tx:\gbtTx_param_generic_src_gen:gbtTx_gen:1:gbtTx|gbt_tx_gearbox:txGearbox|gbt_tx_gearbox_std:\txGearboxStd_gen:txGearboxStd|gbt_tx_gearbox_std_rdwrctrl:readWriteControl|writeAddress[1] will power up to High
Critical Warning (18010): Register VfcHdApplication:i_VfcHdApplication|VfcHdGbtCoreX4:i_AppSfpGbtBank|alt_av_gbt_example_design_x4:i_AltAvGbtExampleDesignX4|alt_av_gbt_example_design:i_GbtExmplDsgn|gbt_bank:gbtBank|gbt_tx:\gbtTx_param_generic_src_gen:gbtTx_gen:1:gbtTx|gbt_tx_gearbox:txGearbox|gbt_tx_gearbox_std:\txGearboxStd_gen:txGearboxStd|gbt_tx_gearbox_std_rdwrctrl:readWriteControl|writeAddress[2] will power up to High
Critical Warning (18010): Register VfcHdApplication:i_VfcHdApplication|VfcHdGbtCoreX4:i_AppSfpGbtBank|alt_av_gbt_example_design_x4:i_AltAvGbtExampleDesignX4|alt_av_gbt_example_design:i_GbtExmplDsgn|gbt_bank:gbtBank|gbt_tx:\gbtTx_param_generic_src_gen:gbtTx_gen:4:gbtTx|gbt_tx_gearbox:txGearbox|gbt_tx_gearbox_std:\txGearboxStd_gen:txGearboxStd|gbt_tx_gearbox_std_rdwrctrl:readWriteControl|writeAddress[1] will power up to High
Critical Warning (18010): Register VfcHdApplication:i_VfcHdApplication|VfcHdGbtCoreX4:i_AppSfpGbtBank|alt_av_gbt_example_design_x4:i_AltAvGbtExampleDesignX4|alt_av_gbt_example_design:i_GbtExmplDsgn|gbt_bank:gbtBank|gbt_tx:\gbtTx_param_generic_src_gen:gbtTx_gen:4:gbtTx|gbt_tx_gearbox:txGearbox|gbt_tx_gearbox_std:\txGearboxStd_gen:txGearboxStd|gbt_tx_gearbox_std_rdwrctrl:readWriteControl|writeAddress[2] will power up to High
Critical Warning (18010): Register VfcHdApplication:i_VfcHdApplication|VfcHdGbtCoreX4:i_AppSfpGbtBank|alt_av_gbt_example_design_x4:i_AltAvGbtExampleDesignX4|alt_av_gbt_example_design:i_GbtExmplDsgn|gbt_bank:gbtBank|gbt_tx:\gbtTx_param_generic_src_gen:gbtTx_gen:2:gbtTx|gbt_tx_gearbox:txGearbox|gbt_tx_gearbox_std:\txGearboxStd_gen:txGearboxStd|gbt_tx_gearbox_std_rdwrctrl:readWriteControl|writeAddress[1] will power up to High
Critical Warning (18010): Register VfcHdApplication:i_VfcHdApplication|VfcHdGbtCoreX4:i_AppSfpGbtBank|alt_av_gbt_example_design_x4:i_AltAvGbtExampleDesignX4|alt_av_gbt_example_design:i_GbtExmplDsgn|gbt_bank:gbtBank|gbt_tx:\gbtTx_param_generic_src_gen:gbtTx_gen:2:gbtTx|gbt_tx_gearbox:txGearbox|gbt_tx_gearbox_std:\txGearboxStd_gen:txGearboxStd|gbt_tx_gearbox_std_rdwrctrl:readWriteControl|writeAddress[2] will power up to High
Critical Warning (18010): Register VfcHdApplication:i_VfcHdApplication|VfcHdGbtCoreX4:i_AppSfpGbtBank|alt_av_gbt_example_design_x4:i_AltAvGbtExampleDesignX4|alt_av_gbt_example_design:i_GbtExmplDsgn|gbt_bank:gbtBank|gbt_tx:\gbtTx_param_generic_src_gen:gbtTx_gen:3:gbtTx|gbt_tx_gearbox:txGearbox|gbt_tx_gearbox_std:\txGearboxStd_gen:txGearboxStd|gbt_tx_gearbox_std_rdwrctrl:readWriteControl|writeAddress[1] will power up to High
Critical Warning (18010): Register VfcHdApplication:i_VfcHdApplication|VfcHdGbtCoreX4:i_AppSfpGbtBank|alt_av_gbt_example_design_x4:i_AltAvGbtExampleDesignX4|alt_av_gbt_example_design:i_GbtExmplDsgn|gbt_bank:gbtBank|gbt_tx:\gbtTx_param_generic_src_gen:gbtTx_gen:3:gbtTx|gbt_tx_gearbox:txGearbox|gbt_tx_gearbox_std:\txGearboxStd_gen:txGearboxStd|gbt_tx_gearbox_std_rdwrctrl:readWriteControl|writeAddress[2] will power up to High
Critical Warning: PLL clock i_VfcHdApplication|i_TopVfcDdr3|i_VfcDdr3|i_Ddr3M|ddr3m_inst|pll0|pll2_phy~PLL_OUTPUT_COUNTER|divclk not driven by a dedicated clock pin or neighboring PLL source. To ensure minimum jitter on memory interface clock outputs, the PLL clock source should be a dedicated PLL input clock pin or an output of the neighboring PLL. Timing analyses may not be valid.
Critical Warning: PLL clock i_VfcHdApplication|i_TopVfcDdr3|i_VfcDdr3|i_Ddr3M|ddr3m_inst|pll0|pll2_phy~PLL_OUTPUT_COUNTER|divclk not driven by a dedicated clock pin or neighboring PLL source. To ensure minimum jitter on memory interface clock outputs, the PLL clock source should be a dedicated PLL input clock pin or an output of the neighboring PLL. Timing analyses may not be valid.
Critical Warning: PLL clock i_VfcHdApplication|i_TopVfcDdr3|i_VfcDdr3|i_Ddr3M|ddr3m_inst|pll0|pll2_phy~PLL_OUTPUT_COUNTER|divclk not driven by a dedicated clock pin or neighboring PLL source. To ensure minimum jitter on memory interface clock outputs, the PLL clock source should be a dedicated PLL input clock pin or an output of the neighboring PLL. Timing analyses may not be valid.
Critical Warning: PLL clock i_VfcHdApplication|i_TopVfcDdr3|i_VfcDdr3|i_Ddr3M|ddr3m_inst|pll0|pll2_phy~PLL_OUTPUT_COUNTER|divclk not driven by a dedicated clock pin or neighboring PLL source. To ensure minimum jitter on memory interface clock outputs, the PLL clock source should be a dedicated PLL input clock pin or an output of the neighboring PLL. Timing analyses may not be valid.
Critical Warning (332148): Timing requirements not met
Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.
Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.
Critical Warning: PLL clock i_VfcHdApplication|i_TopVfcDdr3|i_VfcDdr3|i_Ddr3M|ddr3m_inst|pll0|pll2_phy~PLL_OUTPUT_COUNTER|divclk not driven by a dedicated clock pin or neighboring PLL source. To ensure minimum jitter on memory interface clock outputs, the PLL clock source should be a dedicated PLL input clock pin or an output of the neighboring PLL. Timing analyses may not be valid.
Critical Warning: DDR Timing requirements not met
Critical Warning: PLL clock i_VfcHdApplication|i_TopVfcDdr3|i_VfcDdr3|i_Ddr3M|ddr3m_inst|pll0|pll2_phy~PLL_OUTPUT_COUNTER|divclk not driven by a dedicated clock pin or neighboring PLL source. To ensure minimum jitter on memory interface clock outputs, the PLL clock source should be a dedicated PLL input clock pin or an output of the neighboring PLL. Timing analyses may not be valid.
Critical Warning: DDR Timing requirements not met
Critical Warning (332148): Timing requirements not met
Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.
Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.
Critical Warning: PLL clock i_VfcHdApplication|i_TopVfcDdr3|i_VfcDdr3|i_Ddr3M|ddr3m_inst|pll0|pll2_phy~PLL_OUTPUT_COUNTER|divclk not driven by a dedicated clock pin or neighboring PLL source. To ensure minimum jitter on memory interface clock outputs, the PLL clock source should be a dedicated PLL input clock pin or an output of the neighboring PLL. Timing analyses may not be valid.
Critical Warning: DDR Timing requirements not met
Critical Warning: PLL clock i_VfcHdApplication|i_TopVfcDdr3|i_VfcDdr3|i_Ddr3M|ddr3m_inst|pll0|pll2_phy~PLL_OUTPUT_COUNTER|divclk not driven by a dedicated clock pin or neighboring PLL source. To ensure minimum jitter on memory interface clock outputs, the PLL clock source should be a dedicated PLL input clock pin or an output of the neighboring PLL. Timing analyses may not be valid.
Critical Warning: DDR Timing requirements not met
Critical Warning (332148): Timing requirements not met
Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.
Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.
Critical Warning: PLL clock i_VfcHdApplication|i_TopVfcDdr3|i_VfcDdr3|i_Ddr3M|ddr3m_inst|pll0|pll2_phy~PLL_OUTPUT_COUNTER|divclk not driven by a dedicated clock pin or neighboring PLL source. To ensure minimum jitter on memory interface clock outputs, the PLL clock source should be a dedicated PLL input clock pin or an output of the neighboring PLL. Timing analyses may not be valid.
Critical Warning: DDR Timing requirements not met
Critical Warning: PLL clock i_VfcHdApplication|i_TopVfcDdr3|i_VfcDdr3|i_Ddr3M|ddr3m_inst|pll0|pll2_phy~PLL_OUTPUT_COUNTER|divclk not driven by a dedicated clock pin or neighboring PLL source. To ensure minimum jitter on memory interface clock outputs, the PLL clock source should be a dedicated PLL input clock pin or an output of the neighboring PLL. Timing analyses may not be valid.
Critical Warning: DDR Timing requirements not met
Critical Warning (332148): Timing requirements not met
Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.
Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.
Critical Warning: PLL clock i_VfcHdApplication|i_TopVfcDdr3|i_VfcDdr3|i_Ddr3M|ddr3m_inst|pll0|pll2_phy~PLL_OUTPUT_COUNTER|divclk not driven by a dedicated clock pin or neighboring PLL source. To ensure minimum jitter on memory interface clock outputs, the PLL clock source should be a dedicated PLL input clock pin or an output of the neighboring PLL. Timing analyses may not be valid.
Critical Warning: DDR Timing requirements not met
Critical Warning: PLL clock i_VfcHdApplication|i_TopVfcDdr3|i_VfcDdr3|i_Ddr3M|ddr3m_inst|pll0|pll2_phy~PLL_OUTPUT_COUNTER|divclk not driven by a dedicated clock pin or neighboring PLL source. To ensure minimum jitter on memory interface clock outputs, the PLL clock source should be a dedicated PLL input clock pin or an output of the neighboring PLL. Timing analyses may not be valid.
Critical Warning: DDR Timing requirements not met