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Created date
DDR3 wrapper removed
!24
· created
Mar 26, 2020
by
Andrea Boccardi
Merged
0
updated
Mar 26, 2020
Syncing to system
!25
· created
Mar 26, 2020
by
David Belohrad
Merged
0
updated
Mar 26, 2020
Make sure DDR QIP is first to load.
!26
· created
Mar 31, 2020
by
Tom Levens
Merged
0
updated
Mar 31, 2020
Update libraries for Quartus 19.1
!27
· created
Apr 03, 2020
by
Tom Levens
Merged
0
updated
Apr 03, 2020
updated constant SYS_CLK_FREQ
!28
· created
Apr 08, 2020
by
David Belohrad
Merged
0
updated
Apr 09, 2020
System v2.4
!29
· created
Oct 16, 2020
by
Tom Levens
Merged
0
updated
Oct 26, 2020
Update to release System v2.4
!30
· created
Oct 26, 2020
by
Tom Levens
Merged
0
updated
Oct 26, 2020
Quartus 20.1.1
!31
· created
Apr 16, 2021
by
David Belohrad
Merged
+2
5
updated
Apr 19, 2021
Move some modules to BI_HDL_Cores
!32
· created
Apr 16, 2021
by
Tom Levens
quartus_20.1.1
Merged
0
updated
Apr 19, 2021
Add include directories in the Modelsim compile script for verilog files
!33
· created
Jul 15, 2022
by
Mathieu Saccani
Merged
0
updated
Jul 15, 2022
Add the definition of ENABLE_WR.
!34
· created
Oct 26, 2022
by
Mathieu Saccani
Merged
0
updated
Oct 26, 2022
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