Code aligned with languge support for ModelSim and Altera Quartus

First, I apologize for not splitting non-contentious edits with possibly contentious ones. I regard as non-contentious the edits that do not change functionality, hierarchy:

• Port width mismatch fixes
• Wires used before declared
• Unconnected ports

I am not sure why boot room timing configuration appears, I thought it was merged already.

The contentious part is the vme core wrapper, which I needed to work-around verilog to VHDL parameter/generic passing issues. Modelsim did not like strings passed to boolean or enum generics. When I tried enum to enum passing, modelsim does this position based, not actual name based, which felt too error prone to use. Hence I created another wrapper level which translates one type of generics into another and both modelsim and quartus are able to digest. In hind sight, I don't know why I didn't use string->boolean conversion as well. If this is accepted for merge, maybe additional thing to consider, for cosmetic purposes.