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adding conditional ports assignments for VfcHd_v3_0

David Belohrad requested to merge conditional_simulation into master

this patch makes the top-level instance of VFC simulation configurable via VfcHdConfig file in the same way as the synthesis is.

During synthesis the VfcHdConfig.vh defines what shall be included in the resulting gateware. For example if DDR is not required for the functionality, user usually disables 'ENABLE_DDR3' macro in VfcHdConfig.vh. This results removing the DDR declarations including the signals at the module entries, which are related to DDR.

Up to now this functionality was only implemented for the top-level synthesis (VfcHdTop.sv), but not for top-level simulation instance (VfcHd_v3_0.sv).

This patch generates dynamically ports at the top-level of VfcHd_v3_0 out of configuration file exactly in the same way as top-level synthesis file does. Hence e.g. if user wants to use P2 port, or any of the FMC signals (by default enabled, can be disabled by stating DISABLE_VME_P2, DISABLE_FMC_[LA|HA|HB]) they will be propagated to VfcHd_v3_0 module signals including correct direction (which is affected by DIRECTION_ macros in VfcHdConfig.vh)

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