conditional insertion of DDR3 and WR modules

when the design does not use the DDR3 memories, user does not want to have those pins exposed to the main application. Once exposed and not used, they create lots of warning messages from quartus complaining that those signals do not have any drivers.

This commit updates the behaviour of VfcHdTop and simulation top-level such, that when DDR is not requested to be instantiated, the corresponding memory pins are not propagated to the application level. In addition this causes as well to not to instantiate the ddr3 simulation models in the top-level test bench.

Same warning messages are as well issued for PLL DAC of the White Rabbit. When WR is not used, the PLL DAC functionality can be completely removed from the design.

The above is achieved by implementing a new configuration assignment in VfcHdConfig.vh:

ENABLE_WR

when user uncomments the line, the white rabbit PLL module is automatically added to the design. However when left commented out, the PLL DAC functionality is removed from the design and the pins are not propagated from the top-level (and simulation top-level) into the application, as they are not used.

In turn, this patch removes ~25 compilation warnings in the Quartus, when user synthesizes design without DDRs and WR