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VFC-HD_System
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Created date
Resolve "Integer overflow in OneWireBus due to c_ClkFrequency defined as integer"
!99
· created
Feb 27, 2024
by
Stasa Kostic
Merged
0
updated
Feb 27, 2024
Change WB interface to ports
!98
· created
Jan 26, 2024
by
Tom Levens
dev_prog
Merged
0
updated
Jan 26, 2024
System v2.6.0
!97
· created
Jan 24, 2024
by
Tom Levens
Merged
Approved
6
updated
Apr 30, 2024
Remove old flashing Python script
!96
· created
Jan 06, 2024
by
Tom Levens
Merged
0
updated
Jan 06, 2024
Update driver CSV to EDGE3
!95
· created
Jan 06, 2024
by
Tom Levens
Merged
0
updated
Jan 06, 2024
Update gitattributes
!94
· created
Jan 06, 2024
by
Tom Levens
Merged
0
updated
Jan 06, 2024
Added 2 missing i2c registers
!93
· created
Jun 30, 2023
by
Miha Dolenc
Merged
0
updated
Jul 03, 2023
Add .gitattributes
!92
· created
May 29, 2023
by
Tom Levens
Merged
0
updated
May 29, 2023
Update cheby example file
!91
· created
May 29, 2023
by
Tom Levens
Merged
0
updated
May 29, 2023
Update to latest version of vme64x-core
!90
· created
May 27, 2023
by
Tom Levens
Merged
1
updated
Jun 05, 2023
Add flags to cheby files for automatic driver generation
!89
· created
May 02, 2023
by
Tom Levens
Merged
0
updated
May 03, 2023
Cheby fixes
!88
· created
Apr 26, 2023
by
Tom Levens
Merged
0
updated
Apr 26, 2023
Add cheby memory map description
!87
· created
Oct 20, 2022
by
Tom Levens
Merged
1
updated
Apr 25, 2023
Draft: hdlmake version of system - NEEDS REVIEW BEFORE MERGING!
!86
· created
Oct 19, 2022
by
David Belohrad
2
updated
Jul 20, 2023
VadjControl.sv: remove truncated value warning
!85
· created
Oct 11, 2022
by
Tom Levens
Merged
0
updated
Oct 11, 2022
Add include directory and change the compilation order
!84
· created
Jul 15, 2022
by
Mathieu Saccani
Merged
0
updated
Jul 15, 2022
conditional insertion of DDR3 and WR modules
!83
· created
Nov 12, 2021
by
David Belohrad
Merged
+2
1
2
updated
Nov 30, 2021
Fpga temp sensor simu
!82
· created
Jun 21, 2021
by
Mathieu Saccani
Merged
0
updated
Jun 21, 2021
recompiled ip cores for quartus 20.1.1 std
!81
· created
Apr 16, 2021
by
David Belohrad
Merged
+2
Approved
0
updated
Apr 19, 2021
Change the order of compilation for the VME core vhdl files to be compatible with Modelsim.
!80
· created
Feb 08, 2021
by
Mathieu Saccani
Merged
0
updated
Feb 22, 2021
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