ME0 Segment Monitoring + Testing
Integration of the ME0 segment finder is now reasonably well developed. Primitive tests with the in-FPGA segment finder seem to work, and more detailed simulations are showing good results.
Next steps in integration / testing would be developing a more systematic way to test the firmware in-FPGA while also developing tools for future diagnostics, commissioning, etc.
- Segment monitor
We should develop a segment monitor, similar to the S-bit monitor feature that already exists. Given the limits of VHDL I don't think there would be any way to /easily/ parameterize the same module, but I imagine as a starting point that a copy paste of the exsiting S-bit monitor with the input / output ports substituted would be an easy job.
Segments come out of the sbit_me0 module as type:
me0_segments_o : out segment_list_t (g_NUM_SEGMENTS-1 downto 0);
This is an array of segments. Each segment is of type:
type segment_t is record
lc : unsigned(LC_BITS-1 downto 0);
id : unsigned(PID_BITS-1 downto 0);
strip : unsigned(7 downto 0);
partition : unsigned(PARTITION_BITS-1 downto 0);
end record segment_t;
So fields can be accessed e.g. as me0_segments(0).lc
"Valid" segments are marked with lc>0
, so you can check validity of a segment in the segment monitor with e.g. lc /= "000"
The number of bits currently allocated for the segment is:
lc: 3 bits for layer count 0-6
id : 4 bits for pattern id 0-15. This may increase to 5 bits as presently the simulation has 19 patterns. A 5th bit should probably be allocated for the monitor registers.
strip : 8 bits for strip 0-191
partition : 4 bits for partition 0-15
Other fields may be added in the future for e.g. result of fit so the width should be parameterized.
VHDL functions and attributes are provided that are probably useful:
segment_t'w
gives you the number of bits needed to represent the segment. e.g.
-- this is a slv with the right number of bits for one segment
signal segment0 : std_logic_vector (segment_t'w-1 downto 0);
An overloaded function convert
can transform from slv <--> segment
So e.g.
-- convert segment_t to std_logic_vector
-- the slv must be provided as the 2nd argument which is used to extract the size
segment0 <= convert(me0_segments(0), segment0);
You can convert back with the same overloaded function:
me0_segments_o(0) <= convert(segment0, me0_segments_o(0));
You should use the convert functions for input / output from shift registers + block rams etc.
- Testing of segment finder with injector RAMs
With a segment monitor + segment finder + injector RAMs in place I think we could start serious testing by taking data (e.g. generated simple data, data from the n-tuples etc) and sending it through the injector RAMs and reading the output.
This is maybe something Felix could help with also once the infrastructure is in place, i.e. working on connecting the n-tuples into the generator since I think the interface is very similar.