Relax OptoHybrid timing constraints from the ISERDES to the DRU
The (GE1/1) OptoHybrid builds sometimes fail by a tiny margin... because useless timing constraints... This merge request removes them.
More details are available in the commit message:
The asynchronous oversampling application note used both BUFG and BUFIO
clock buffers with a dynamic alignment of their relative phases.
Specific constraints ensured proper functioning of the circuitry. Since
we are working solely with BUFG, let the tool figure out the timing.
Tested on GE1/1 and GE2/1 both in test setups and at P5.