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Firmware dedicated to the communication with the GBTx ASIC
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This component can able to log inside FPGA frequency value, with accuracy upto 2 decimal digits. (Value Format : XXX.XX00)
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Integration of Linear-Regression High-Level Synthesis in EMP framework project.
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Christos Bakalis / elink_wrapper
GNU General Public License v3.0 onlyArchived 0Updated -
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Demonstration on how a DSP block instantiated as System Generator model is simulated differently in System Generator than (once exported as an IP Core) in Vivado
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Project based on UQDS v2.x to test the new DQQDIDT board.
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HDLC for GBT-SCA communication part of DCS work in CRU project.
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For testing the frequency of Arria 10 Development board
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