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LiteDTU starting from version 1.2

DAQ and test system for the RD53 readout chips

Instantiation of Linear-Regression module in TM Track-Finder extensible firmware framework.

work for upgrading New SL Firmware.

PT6 project

GBT-SC for FPGA: This module (VHDL) allows performing slow-control of the front-end through GBT links (GBTx and SCA configuration)

CMS HGCROC chip common testbench FW repo

Project to teach hdlmake how to use Microsemi Libero SoC v12.x tools. Still under development.

Peary Caribou DAQ firmware

Demonstration on how a DSP block instantiated as System Generator model is simulated differently in System Generator than (once exported as an IP Core) in Vivado

DAQ and test system for the RD53A readout chip

A new time-to-digital converter (TDC) ASIC prototype is required for the ATLAS Monitored Drift Tube (MDT) detector. This the logic part of this ASIC with TMR. The reference version without TMR is ssh://git@gitlab.cern.ch:7999/yuliang/New_TDC.git

This project is for doing more detail simulation for New_MDT_TDC ssh://git@gitlab.cern.ch:7999/yuliang/New_TDC.git