Explore projects
-
-
Archived 0Updated
-
Archived 0Updated
-
Archived 0Updated
-
Christos Bakalis / elink_wrapper
GNU General Public License v3.0 onlyArchived 0Updated -
Demonstration on how a DSP block instantiated as System Generator model is simulated differently in System Generator than (once exported as an IP Core) in Vivado
Archived 0Updated -
Project based on UQDS v2.x to test the new DQQDIDT board.
Archived 0Updated -
Archived 0Updated
-
Declan Millar / delphes
Creative Commons Attribution Share Alike 4.0 InternationalA framework for fast simulation of a generic collider experiment
Archived 0Updated -
Archived 0Updated
-
HDLC for GBT-SCA communication part of DCS work in CRU project.
Archived 0Updated -
-
Ester Maria Silva Jimenez / bdaq53
BSD 3-Clause "New" or "Revised" LicenseDAQ and test system for the RD53A readout chip
Archived 0Updated -
Rafael Goncalves Gama / bdaq53
BSD 3-Clause "New" or "Revised" LicenseDAQ and test system for the RD53 readout chips
Archived 0Updated -
Archived 0Updated
-
-
For testing the frequency of Arria 10 Development board
Archived 0Updated -
Archived 0Updated